stm32h5/stm32h562/tim13/
egr.rs

1#[doc = "Register `EGR` writer"]
2pub type W = crate::W<EGRrs>;
3#[doc = "Update generation This bit can be set by software, it is automatically cleared by hardware.\n\nValue on reset: 0"]
4#[derive(Clone, Copy, Debug, PartialEq, Eq)]
5pub enum UG {
6    #[doc = "1: Re-initializes the timer counter and generates an update of the registers."]
7    Update = 1,
8}
9impl From<UG> for bool {
10    #[inline(always)]
11    fn from(variant: UG) -> Self {
12        variant as u8 != 0
13    }
14}
15#[doc = "Field `UG` writer - Update generation This bit can be set by software, it is automatically cleared by hardware."]
16pub type UG_W<'a, REG> = crate::BitWriter<'a, REG, UG>;
17impl<'a, REG> UG_W<'a, REG>
18where
19    REG: crate::Writable + crate::RegisterSpec,
20{
21    #[doc = "Re-initializes the timer counter and generates an update of the registers."]
22    #[inline(always)]
23    pub fn update(self) -> &'a mut crate::W<REG> {
24        self.variant(UG::Update)
25    }
26}
27#[doc = "Field `CC1G` writer - Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high."]
28pub type CC1G_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl W {
30    #[doc = "Bit 0 - Update generation This bit can be set by software, it is automatically cleared by hardware."]
31    #[inline(always)]
32    #[must_use]
33    pub fn ug(&mut self) -> UG_W<EGRrs> {
34        UG_W::new(self, 0)
35    }
36    #[doc = "Bit 1 - Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high."]
37    #[inline(always)]
38    #[must_use]
39    pub fn cc1g(&mut self) -> CC1G_W<EGRrs> {
40        CC1G_W::new(self, 1)
41    }
42    #[doc = r" Writes raw bits to the register."]
43    #[doc = r""]
44    #[doc = r" # Safety"]
45    #[doc = r""]
46    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
47    #[inline(always)]
48    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
49        self.bits = bits;
50        self
51    }
52}
53#[doc = "TIM2 event generation register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`egr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
54pub struct EGRrs;
55impl crate::RegisterSpec for EGRrs {
56    type Ux = u16;
57}
58#[doc = "`write(|w| ..)` method takes [`egr::W`](W) writer structure"]
59impl crate::Writable for EGRrs {
60    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
61    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
62}
63#[doc = "`reset()` method sets EGR to value 0"]
64impl crate::Resettable for EGRrs {
65    const RESET_VALUE: u16 = 0;
66}
stm32h5/stm32h562/tim13/egr.rs

stm32h5/stm32h562/tim13/
egr.rs
