stm32g4/stm32g431/adc1/
cfgr2.rs

1///Register `CFGR2` reader
2pub type R = crate::R<CFGR2rs>;
3///Register `CFGR2` writer
4pub type W = crate::W<CFGR2rs>;
5/**Regular Oversampling Enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ROVSE {
11    ///0: Regular oversampling disabled
12    Disabled = 0,
13    ///1: Regular oversampling enabled
14    Enabled = 1,
15}
16impl From<ROVSE> for bool {
17    #[inline(always)]
18    fn from(variant: ROVSE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ROVSE` reader - Regular Oversampling Enable
23pub type ROVSE_R = crate::BitReader<ROVSE>;
24impl ROVSE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> ROVSE {
28        match self.bits {
29            false => ROVSE::Disabled,
30            true => ROVSE::Enabled,
31        }
32    }
33    ///Regular oversampling disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == ROVSE::Disabled
37    }
38    ///Regular oversampling enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == ROVSE::Enabled
42    }
43}
44///Field `ROVSE` writer - Regular Oversampling Enable
45pub type ROVSE_W<'a, REG> = crate::BitWriter<'a, REG, ROVSE>;
46impl<'a, REG> ROVSE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Regular oversampling disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(ROVSE::Disabled)
54    }
55    ///Regular oversampling enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(ROVSE::Enabled)
59    }
60}
61/**Injected Oversampling Enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum JOVSE {
67    ///0: Injected oversampling disabled
68    Disabled = 0,
69    ///1: Injected oversampling enabled
70    Enabled = 1,
71}
72impl From<JOVSE> for bool {
73    #[inline(always)]
74    fn from(variant: JOVSE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `JOVSE` reader - Injected Oversampling Enable
79pub type JOVSE_R = crate::BitReader<JOVSE>;
80impl JOVSE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> JOVSE {
84        match self.bits {
85            false => JOVSE::Disabled,
86            true => JOVSE::Enabled,
87        }
88    }
89    ///Injected oversampling disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == JOVSE::Disabled
93    }
94    ///Injected oversampling enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == JOVSE::Enabled
98    }
99}
100///Field `JOVSE` writer - Injected Oversampling Enable
101pub type JOVSE_W<'a, REG> = crate::BitWriter<'a, REG, JOVSE>;
102impl<'a, REG> JOVSE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Injected oversampling disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(JOVSE::Disabled)
110    }
111    ///Injected oversampling enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(JOVSE::Enabled)
115    }
116}
117/**Oversampling ratio
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122#[repr(u8)]
123pub enum OVSR {
124    ///0: Oversampling ratio of 2
125    Os2 = 0,
126    ///1: Oversampling ratio of 4
127    Os4 = 1,
128    ///2: Oversampling ratio of 8
129    Os8 = 2,
130    ///3: Oversampling ratio of 16
131    Os16 = 3,
132    ///4: Oversampling ratio of 32
133    Os32 = 4,
134    ///5: Oversampling ratio of 64
135    Os64 = 5,
136    ///6: Oversampling ratio of 128
137    Os128 = 6,
138    ///7: Oversampling ratio of 256
139    Os256 = 7,
140}
141impl From<OVSR> for u8 {
142    #[inline(always)]
143    fn from(variant: OVSR) -> Self {
144        variant as _
145    }
146}
147impl crate::FieldSpec for OVSR {
148    type Ux = u8;
149}
150impl crate::IsEnum for OVSR {}
151///Field `OVSR` reader - Oversampling ratio
152pub type OVSR_R = crate::FieldReader<OVSR>;
153impl OVSR_R {
154    ///Get enumerated values variant
155    #[inline(always)]
156    pub const fn variant(&self) -> OVSR {
157        match self.bits {
158            0 => OVSR::Os2,
159            1 => OVSR::Os4,
160            2 => OVSR::Os8,
161            3 => OVSR::Os16,
162            4 => OVSR::Os32,
163            5 => OVSR::Os64,
164            6 => OVSR::Os128,
165            7 => OVSR::Os256,
166            _ => unreachable!(),
167        }
168    }
169    ///Oversampling ratio of 2
170    #[inline(always)]
171    pub fn is_os2(&self) -> bool {
172        *self == OVSR::Os2
173    }
174    ///Oversampling ratio of 4
175    #[inline(always)]
176    pub fn is_os4(&self) -> bool {
177        *self == OVSR::Os4
178    }
179    ///Oversampling ratio of 8
180    #[inline(always)]
181    pub fn is_os8(&self) -> bool {
182        *self == OVSR::Os8
183    }
184    ///Oversampling ratio of 16
185    #[inline(always)]
186    pub fn is_os16(&self) -> bool {
187        *self == OVSR::Os16
188    }
189    ///Oversampling ratio of 32
190    #[inline(always)]
191    pub fn is_os32(&self) -> bool {
192        *self == OVSR::Os32
193    }
194    ///Oversampling ratio of 64
195    #[inline(always)]
196    pub fn is_os64(&self) -> bool {
197        *self == OVSR::Os64
198    }
199    ///Oversampling ratio of 128
200    #[inline(always)]
201    pub fn is_os128(&self) -> bool {
202        *self == OVSR::Os128
203    }
204    ///Oversampling ratio of 256
205    #[inline(always)]
206    pub fn is_os256(&self) -> bool {
207        *self == OVSR::Os256
208    }
209}
210///Field `OVSR` writer - Oversampling ratio
211pub type OVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 3, OVSR, crate::Safe>;
212impl<'a, REG> OVSR_W<'a, REG>
213where
214    REG: crate::Writable + crate::RegisterSpec,
215    REG::Ux: From<u8>,
216{
217    ///Oversampling ratio of 2
218    #[inline(always)]
219    pub fn os2(self) -> &'a mut crate::W<REG> {
220        self.variant(OVSR::Os2)
221    }
222    ///Oversampling ratio of 4
223    #[inline(always)]
224    pub fn os4(self) -> &'a mut crate::W<REG> {
225        self.variant(OVSR::Os4)
226    }
227    ///Oversampling ratio of 8
228    #[inline(always)]
229    pub fn os8(self) -> &'a mut crate::W<REG> {
230        self.variant(OVSR::Os8)
231    }
232    ///Oversampling ratio of 16
233    #[inline(always)]
234    pub fn os16(self) -> &'a mut crate::W<REG> {
235        self.variant(OVSR::Os16)
236    }
237    ///Oversampling ratio of 32
238    #[inline(always)]
239    pub fn os32(self) -> &'a mut crate::W<REG> {
240        self.variant(OVSR::Os32)
241    }
242    ///Oversampling ratio of 64
243    #[inline(always)]
244    pub fn os64(self) -> &'a mut crate::W<REG> {
245        self.variant(OVSR::Os64)
246    }
247    ///Oversampling ratio of 128
248    #[inline(always)]
249    pub fn os128(self) -> &'a mut crate::W<REG> {
250        self.variant(OVSR::Os128)
251    }
252    ///Oversampling ratio of 256
253    #[inline(always)]
254    pub fn os256(self) -> &'a mut crate::W<REG> {
255        self.variant(OVSR::Os256)
256    }
257}
258/**Oversampling shift
259
260Value on reset: 0*/
261#[cfg_attr(feature = "defmt", derive(defmt::Format))]
262#[derive(Clone, Copy, Debug, PartialEq, Eq)]
263#[repr(u8)]
264pub enum OVSS {
265    ///0: No right shift applied to oversampling result
266    NoShift = 0,
267    ///1: Shift oversampling result right by 1 bit
268    Shift1 = 1,
269    ///2: Shift oversampling result right by 2 bits
270    Shift2 = 2,
271    ///3: Shift oversampling result right by 3 bits
272    Shift3 = 3,
273    ///4: Shift oversampling result right by 4 bits
274    Shift4 = 4,
275    ///5: Shift oversampling result right by 5 bits
276    Shift5 = 5,
277    ///6: Shift oversampling result right by 6 bits
278    Shift6 = 6,
279    ///7: Shift oversampling result right by 7 bits
280    Shift7 = 7,
281    ///8: Shift oversampling result right by 8 bits
282    Shift8 = 8,
283}
284impl From<OVSS> for u8 {
285    #[inline(always)]
286    fn from(variant: OVSS) -> Self {
287        variant as _
288    }
289}
290impl crate::FieldSpec for OVSS {
291    type Ux = u8;
292}
293impl crate::IsEnum for OVSS {}
294///Field `OVSS` reader - Oversampling shift
295pub type OVSS_R = crate::FieldReader<OVSS>;
296impl OVSS_R {
297    ///Get enumerated values variant
298    #[inline(always)]
299    pub const fn variant(&self) -> Option<OVSS> {
300        match self.bits {
301            0 => Some(OVSS::NoShift),
302            1 => Some(OVSS::Shift1),
303            2 => Some(OVSS::Shift2),
304            3 => Some(OVSS::Shift3),
305            4 => Some(OVSS::Shift4),
306            5 => Some(OVSS::Shift5),
307            6 => Some(OVSS::Shift6),
308            7 => Some(OVSS::Shift7),
309            8 => Some(OVSS::Shift8),
310            _ => None,
311        }
312    }
313    ///No right shift applied to oversampling result
314    #[inline(always)]
315    pub fn is_no_shift(&self) -> bool {
316        *self == OVSS::NoShift
317    }
318    ///Shift oversampling result right by 1 bit
319    #[inline(always)]
320    pub fn is_shift1(&self) -> bool {
321        *self == OVSS::Shift1
322    }
323    ///Shift oversampling result right by 2 bits
324    #[inline(always)]
325    pub fn is_shift2(&self) -> bool {
326        *self == OVSS::Shift2
327    }
328    ///Shift oversampling result right by 3 bits
329    #[inline(always)]
330    pub fn is_shift3(&self) -> bool {
331        *self == OVSS::Shift3
332    }
333    ///Shift oversampling result right by 4 bits
334    #[inline(always)]
335    pub fn is_shift4(&self) -> bool {
336        *self == OVSS::Shift4
337    }
338    ///Shift oversampling result right by 5 bits
339    #[inline(always)]
340    pub fn is_shift5(&self) -> bool {
341        *self == OVSS::Shift5
342    }
343    ///Shift oversampling result right by 6 bits
344    #[inline(always)]
345    pub fn is_shift6(&self) -> bool {
346        *self == OVSS::Shift6
347    }
348    ///Shift oversampling result right by 7 bits
349    #[inline(always)]
350    pub fn is_shift7(&self) -> bool {
351        *self == OVSS::Shift7
352    }
353    ///Shift oversampling result right by 8 bits
354    #[inline(always)]
355    pub fn is_shift8(&self) -> bool {
356        *self == OVSS::Shift8
357    }
358}
359///Field `OVSS` writer - Oversampling shift
360pub type OVSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4, OVSS>;
361impl<'a, REG> OVSS_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364    REG::Ux: From<u8>,
365{
366    ///No right shift applied to oversampling result
367    #[inline(always)]
368    pub fn no_shift(self) -> &'a mut crate::W<REG> {
369        self.variant(OVSS::NoShift)
370    }
371    ///Shift oversampling result right by 1 bit
372    #[inline(always)]
373    pub fn shift1(self) -> &'a mut crate::W<REG> {
374        self.variant(OVSS::Shift1)
375    }
376    ///Shift oversampling result right by 2 bits
377    #[inline(always)]
378    pub fn shift2(self) -> &'a mut crate::W<REG> {
379        self.variant(OVSS::Shift2)
380    }
381    ///Shift oversampling result right by 3 bits
382    #[inline(always)]
383    pub fn shift3(self) -> &'a mut crate::W<REG> {
384        self.variant(OVSS::Shift3)
385    }
386    ///Shift oversampling result right by 4 bits
387    #[inline(always)]
388    pub fn shift4(self) -> &'a mut crate::W<REG> {
389        self.variant(OVSS::Shift4)
390    }
391    ///Shift oversampling result right by 5 bits
392    #[inline(always)]
393    pub fn shift5(self) -> &'a mut crate::W<REG> {
394        self.variant(OVSS::Shift5)
395    }
396    ///Shift oversampling result right by 6 bits
397    #[inline(always)]
398    pub fn shift6(self) -> &'a mut crate::W<REG> {
399        self.variant(OVSS::Shift6)
400    }
401    ///Shift oversampling result right by 7 bits
402    #[inline(always)]
403    pub fn shift7(self) -> &'a mut crate::W<REG> {
404        self.variant(OVSS::Shift7)
405    }
406    ///Shift oversampling result right by 8 bits
407    #[inline(always)]
408    pub fn shift8(self) -> &'a mut crate::W<REG> {
409        self.variant(OVSS::Shift8)
410    }
411}
412/**Triggered Regular Oversampling
413
414Value on reset: 0*/
415#[cfg_attr(feature = "defmt", derive(defmt::Format))]
416#[derive(Clone, Copy, Debug, PartialEq, Eq)]
417pub enum TROVS {
418    ///0: All oversampled conversions for a channel are run following a trigger
419    Automatic = 0,
420    ///1: Each oversampled conversion for a channel needs a new trigger
421    Triggered = 1,
422}
423impl From<TROVS> for bool {
424    #[inline(always)]
425    fn from(variant: TROVS) -> Self {
426        variant as u8 != 0
427    }
428}
429///Field `TROVS` reader - Triggered Regular Oversampling
430pub type TROVS_R = crate::BitReader<TROVS>;
431impl TROVS_R {
432    ///Get enumerated values variant
433    #[inline(always)]
434    pub const fn variant(&self) -> TROVS {
435        match self.bits {
436            false => TROVS::Automatic,
437            true => TROVS::Triggered,
438        }
439    }
440    ///All oversampled conversions for a channel are run following a trigger
441    #[inline(always)]
442    pub fn is_automatic(&self) -> bool {
443        *self == TROVS::Automatic
444    }
445    ///Each oversampled conversion for a channel needs a new trigger
446    #[inline(always)]
447    pub fn is_triggered(&self) -> bool {
448        *self == TROVS::Triggered
449    }
450}
451///Field `TROVS` writer - Triggered Regular Oversampling
452pub type TROVS_W<'a, REG> = crate::BitWriter<'a, REG, TROVS>;
453impl<'a, REG> TROVS_W<'a, REG>
454where
455    REG: crate::Writable + crate::RegisterSpec,
456{
457    ///All oversampled conversions for a channel are run following a trigger
458    #[inline(always)]
459    pub fn automatic(self) -> &'a mut crate::W<REG> {
460        self.variant(TROVS::Automatic)
461    }
462    ///Each oversampled conversion for a channel needs a new trigger
463    #[inline(always)]
464    pub fn triggered(self) -> &'a mut crate::W<REG> {
465        self.variant(TROVS::Triggered)
466    }
467}
468/**Regular Oversampling mode
469
470Value on reset: 0*/
471#[cfg_attr(feature = "defmt", derive(defmt::Format))]
472#[derive(Clone, Copy, Debug, PartialEq, Eq)]
473pub enum ROVSM {
474    ///0: Oversampling is temporary stopped and continued after injection sequence
475    Continued = 0,
476    ///1: Oversampling is aborted and resumed from start after injection sequence
477    Resumed = 1,
478}
479impl From<ROVSM> for bool {
480    #[inline(always)]
481    fn from(variant: ROVSM) -> Self {
482        variant as u8 != 0
483    }
484}
485///Field `ROVSM` reader - Regular Oversampling mode
486pub type ROVSM_R = crate::BitReader<ROVSM>;
487impl ROVSM_R {
488    ///Get enumerated values variant
489    #[inline(always)]
490    pub const fn variant(&self) -> ROVSM {
491        match self.bits {
492            false => ROVSM::Continued,
493            true => ROVSM::Resumed,
494        }
495    }
496    ///Oversampling is temporary stopped and continued after injection sequence
497    #[inline(always)]
498    pub fn is_continued(&self) -> bool {
499        *self == ROVSM::Continued
500    }
501    ///Oversampling is aborted and resumed from start after injection sequence
502    #[inline(always)]
503    pub fn is_resumed(&self) -> bool {
504        *self == ROVSM::Resumed
505    }
506}
507///Field `ROVSM` writer - Regular Oversampling mode
508pub type ROVSM_W<'a, REG> = crate::BitWriter<'a, REG, ROVSM>;
509impl<'a, REG> ROVSM_W<'a, REG>
510where
511    REG: crate::Writable + crate::RegisterSpec,
512{
513    ///Oversampling is temporary stopped and continued after injection sequence
514    #[inline(always)]
515    pub fn continued(self) -> &'a mut crate::W<REG> {
516        self.variant(ROVSM::Continued)
517    }
518    ///Oversampling is aborted and resumed from start after injection sequence
519    #[inline(always)]
520    pub fn resumed(self) -> &'a mut crate::W<REG> {
521        self.variant(ROVSM::Resumed)
522    }
523}
524/**Gain compensation mode
525
526Value on reset: 0*/
527#[cfg_attr(feature = "defmt", derive(defmt::Format))]
528#[derive(Clone, Copy, Debug, PartialEq, Eq)]
529pub enum GCOMP {
530    ///0: Regular ADC operating mode
531    Disabled = 0,
532    ///1: Gain compensation enabled and applies to all channels
533    Enabled = 1,
534}
535impl From<GCOMP> for bool {
536    #[inline(always)]
537    fn from(variant: GCOMP) -> Self {
538        variant as u8 != 0
539    }
540}
541///Field `GCOMP` reader - Gain compensation mode
542pub type GCOMP_R = crate::BitReader<GCOMP>;
543impl GCOMP_R {
544    ///Get enumerated values variant
545    #[inline(always)]
546    pub const fn variant(&self) -> GCOMP {
547        match self.bits {
548            false => GCOMP::Disabled,
549            true => GCOMP::Enabled,
550        }
551    }
552    ///Regular ADC operating mode
553    #[inline(always)]
554    pub fn is_disabled(&self) -> bool {
555        *self == GCOMP::Disabled
556    }
557    ///Gain compensation enabled and applies to all channels
558    #[inline(always)]
559    pub fn is_enabled(&self) -> bool {
560        *self == GCOMP::Enabled
561    }
562}
563///Field `GCOMP` writer - Gain compensation mode
564pub type GCOMP_W<'a, REG> = crate::BitWriter<'a, REG, GCOMP>;
565impl<'a, REG> GCOMP_W<'a, REG>
566where
567    REG: crate::Writable + crate::RegisterSpec,
568{
569    ///Regular ADC operating mode
570    #[inline(always)]
571    pub fn disabled(self) -> &'a mut crate::W<REG> {
572        self.variant(GCOMP::Disabled)
573    }
574    ///Gain compensation enabled and applies to all channels
575    #[inline(always)]
576    pub fn enabled(self) -> &'a mut crate::W<REG> {
577        self.variant(GCOMP::Enabled)
578    }
579}
580/**Software trigger bit for sampling time control trigger mode
581
582Value on reset: 0*/
583#[cfg_attr(feature = "defmt", derive(defmt::Format))]
584#[derive(Clone, Copy, Debug, PartialEq, Eq)]
585pub enum SWTRIG {
586    ///0: End sampling period and start conversion
587    Disabled = 0,
588    ///1: Start sampling period
589    Enabled = 1,
590}
591impl From<SWTRIG> for bool {
592    #[inline(always)]
593    fn from(variant: SWTRIG) -> Self {
594        variant as u8 != 0
595    }
596}
597///Field `SWTRIG` reader - Software trigger bit for sampling time control trigger mode
598pub type SWTRIG_R = crate::BitReader<SWTRIG>;
599impl SWTRIG_R {
600    ///Get enumerated values variant
601    #[inline(always)]
602    pub const fn variant(&self) -> SWTRIG {
603        match self.bits {
604            false => SWTRIG::Disabled,
605            true => SWTRIG::Enabled,
606        }
607    }
608    ///End sampling period and start conversion
609    #[inline(always)]
610    pub fn is_disabled(&self) -> bool {
611        *self == SWTRIG::Disabled
612    }
613    ///Start sampling period
614    #[inline(always)]
615    pub fn is_enabled(&self) -> bool {
616        *self == SWTRIG::Enabled
617    }
618}
619///Field `SWTRIG` writer - Software trigger bit for sampling time control trigger mode
620pub type SWTRIG_W<'a, REG> = crate::BitWriter<'a, REG, SWTRIG>;
621impl<'a, REG> SWTRIG_W<'a, REG>
622where
623    REG: crate::Writable + crate::RegisterSpec,
624{
625    ///End sampling period and start conversion
626    #[inline(always)]
627    pub fn disabled(self) -> &'a mut crate::W<REG> {
628        self.variant(SWTRIG::Disabled)
629    }
630    ///Start sampling period
631    #[inline(always)]
632    pub fn enabled(self) -> &'a mut crate::W<REG> {
633        self.variant(SWTRIG::Enabled)
634    }
635}
636/**Bulb sampling mode
637
638Value on reset: 0*/
639#[cfg_attr(feature = "defmt", derive(defmt::Format))]
640#[derive(Clone, Copy, Debug, PartialEq, Eq)]
641pub enum BULB {
642    ///0: Bulb sampling mode disabled
643    Disabled = 0,
644    ///1: Bulb sampling mode enabled. Immediately start sampling after last conversion finishes.
645    Enabled = 1,
646}
647impl From<BULB> for bool {
648    #[inline(always)]
649    fn from(variant: BULB) -> Self {
650        variant as u8 != 0
651    }
652}
653///Field `BULB` reader - Bulb sampling mode
654pub type BULB_R = crate::BitReader<BULB>;
655impl BULB_R {
656    ///Get enumerated values variant
657    #[inline(always)]
658    pub const fn variant(&self) -> BULB {
659        match self.bits {
660            false => BULB::Disabled,
661            true => BULB::Enabled,
662        }
663    }
664    ///Bulb sampling mode disabled
665    #[inline(always)]
666    pub fn is_disabled(&self) -> bool {
667        *self == BULB::Disabled
668    }
669    ///Bulb sampling mode enabled. Immediately start sampling after last conversion finishes.
670    #[inline(always)]
671    pub fn is_enabled(&self) -> bool {
672        *self == BULB::Enabled
673    }
674}
675///Field `BULB` writer - Bulb sampling mode
676pub type BULB_W<'a, REG> = crate::BitWriter<'a, REG, BULB>;
677impl<'a, REG> BULB_W<'a, REG>
678where
679    REG: crate::Writable + crate::RegisterSpec,
680{
681    ///Bulb sampling mode disabled
682    #[inline(always)]
683    pub fn disabled(self) -> &'a mut crate::W<REG> {
684        self.variant(BULB::Disabled)
685    }
686    ///Bulb sampling mode enabled. Immediately start sampling after last conversion finishes.
687    #[inline(always)]
688    pub fn enabled(self) -> &'a mut crate::W<REG> {
689        self.variant(BULB::Enabled)
690    }
691}
692/**Sampling time control trigger mode
693
694Value on reset: 0*/
695#[cfg_attr(feature = "defmt", derive(defmt::Format))]
696#[derive(Clone, Copy, Debug, PartialEq, Eq)]
697pub enum SMPTRIG {
698    ///0: Sampling time control trigger mode disabled
699    Disabled = 0,
700    ///1: Sampling time control trigger mode enabled
701    Enabled = 1,
702}
703impl From<SMPTRIG> for bool {
704    #[inline(always)]
705    fn from(variant: SMPTRIG) -> Self {
706        variant as u8 != 0
707    }
708}
709///Field `SMPTRIG` reader - Sampling time control trigger mode
710pub type SMPTRIG_R = crate::BitReader<SMPTRIG>;
711impl SMPTRIG_R {
712    ///Get enumerated values variant
713    #[inline(always)]
714    pub const fn variant(&self) -> SMPTRIG {
715        match self.bits {
716            false => SMPTRIG::Disabled,
717            true => SMPTRIG::Enabled,
718        }
719    }
720    ///Sampling time control trigger mode disabled
721    #[inline(always)]
722    pub fn is_disabled(&self) -> bool {
723        *self == SMPTRIG::Disabled
724    }
725    ///Sampling time control trigger mode enabled
726    #[inline(always)]
727    pub fn is_enabled(&self) -> bool {
728        *self == SMPTRIG::Enabled
729    }
730}
731///Field `SMPTRIG` writer - Sampling time control trigger mode
732pub type SMPTRIG_W<'a, REG> = crate::BitWriter<'a, REG, SMPTRIG>;
733impl<'a, REG> SMPTRIG_W<'a, REG>
734where
735    REG: crate::Writable + crate::RegisterSpec,
736{
737    ///Sampling time control trigger mode disabled
738    #[inline(always)]
739    pub fn disabled(self) -> &'a mut crate::W<REG> {
740        self.variant(SMPTRIG::Disabled)
741    }
742    ///Sampling time control trigger mode enabled
743    #[inline(always)]
744    pub fn enabled(self) -> &'a mut crate::W<REG> {
745        self.variant(SMPTRIG::Enabled)
746    }
747}
748impl R {
749    ///Bit 0 - Regular Oversampling Enable
750    #[inline(always)]
751    pub fn rovse(&self) -> ROVSE_R {
752        ROVSE_R::new((self.bits & 1) != 0)
753    }
754    ///Bit 1 - Injected Oversampling Enable
755    #[inline(always)]
756    pub fn jovse(&self) -> JOVSE_R {
757        JOVSE_R::new(((self.bits >> 1) & 1) != 0)
758    }
759    ///Bits 2:4 - Oversampling ratio
760    #[inline(always)]
761    pub fn ovsr(&self) -> OVSR_R {
762        OVSR_R::new(((self.bits >> 2) & 7) as u8)
763    }
764    ///Bits 5:8 - Oversampling shift
765    #[inline(always)]
766    pub fn ovss(&self) -> OVSS_R {
767        OVSS_R::new(((self.bits >> 5) & 0x0f) as u8)
768    }
769    ///Bit 9 - Triggered Regular Oversampling
770    #[inline(always)]
771    pub fn trovs(&self) -> TROVS_R {
772        TROVS_R::new(((self.bits >> 9) & 1) != 0)
773    }
774    ///Bit 10 - Regular Oversampling mode
775    #[inline(always)]
776    pub fn rovsm(&self) -> ROVSM_R {
777        ROVSM_R::new(((self.bits >> 10) & 1) != 0)
778    }
779    ///Bit 16 - Gain compensation mode
780    #[inline(always)]
781    pub fn gcomp(&self) -> GCOMP_R {
782        GCOMP_R::new(((self.bits >> 16) & 1) != 0)
783    }
784    ///Bit 25 - Software trigger bit for sampling time control trigger mode
785    #[inline(always)]
786    pub fn swtrig(&self) -> SWTRIG_R {
787        SWTRIG_R::new(((self.bits >> 25) & 1) != 0)
788    }
789    ///Bit 26 - Bulb sampling mode
790    #[inline(always)]
791    pub fn bulb(&self) -> BULB_R {
792        BULB_R::new(((self.bits >> 26) & 1) != 0)
793    }
794    ///Bit 27 - Sampling time control trigger mode
795    #[inline(always)]
796    pub fn smptrig(&self) -> SMPTRIG_R {
797        SMPTRIG_R::new(((self.bits >> 27) & 1) != 0)
798    }
799}
800impl core::fmt::Debug for R {
801    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
802        f.debug_struct("CFGR2")
803            .field("smptrig", &self.smptrig())
804            .field("bulb", &self.bulb())
805            .field("swtrig", &self.swtrig())
806            .field("gcomp", &self.gcomp())
807            .field("rovsm", &self.rovsm())
808            .field("trovs", &self.trovs())
809            .field("ovss", &self.ovss())
810            .field("ovsr", &self.ovsr())
811            .field("jovse", &self.jovse())
812            .field("rovse", &self.rovse())
813            .finish()
814    }
815}
816impl W {
817    ///Bit 0 - Regular Oversampling Enable
818    #[inline(always)]
819    pub fn rovse(&mut self) -> ROVSE_W<CFGR2rs> {
820        ROVSE_W::new(self, 0)
821    }
822    ///Bit 1 - Injected Oversampling Enable
823    #[inline(always)]
824    pub fn jovse(&mut self) -> JOVSE_W<CFGR2rs> {
825        JOVSE_W::new(self, 1)
826    }
827    ///Bits 2:4 - Oversampling ratio
828    #[inline(always)]
829    pub fn ovsr(&mut self) -> OVSR_W<CFGR2rs> {
830        OVSR_W::new(self, 2)
831    }
832    ///Bits 5:8 - Oversampling shift
833    #[inline(always)]
834    pub fn ovss(&mut self) -> OVSS_W<CFGR2rs> {
835        OVSS_W::new(self, 5)
836    }
837    ///Bit 9 - Triggered Regular Oversampling
838    #[inline(always)]
839    pub fn trovs(&mut self) -> TROVS_W<CFGR2rs> {
840        TROVS_W::new(self, 9)
841    }
842    ///Bit 10 - Regular Oversampling mode
843    #[inline(always)]
844    pub fn rovsm(&mut self) -> ROVSM_W<CFGR2rs> {
845        ROVSM_W::new(self, 10)
846    }
847    ///Bit 16 - Gain compensation mode
848    #[inline(always)]
849    pub fn gcomp(&mut self) -> GCOMP_W<CFGR2rs> {
850        GCOMP_W::new(self, 16)
851    }
852    ///Bit 25 - Software trigger bit for sampling time control trigger mode
853    #[inline(always)]
854    pub fn swtrig(&mut self) -> SWTRIG_W<CFGR2rs> {
855        SWTRIG_W::new(self, 25)
856    }
857    ///Bit 26 - Bulb sampling mode
858    #[inline(always)]
859    pub fn bulb(&mut self) -> BULB_W<CFGR2rs> {
860        BULB_W::new(self, 26)
861    }
862    ///Bit 27 - Sampling time control trigger mode
863    #[inline(always)]
864    pub fn smptrig(&mut self) -> SMPTRIG_W<CFGR2rs> {
865        SMPTRIG_W::new(self, 27)
866    }
867}
868/**configuration register
869
870You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
871
872See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G431.html#ADC1:CFGR2)*/
873pub struct CFGR2rs;
874impl crate::RegisterSpec for CFGR2rs {
875    type Ux = u32;
876}
877///`read()` method returns [`cfgr2::R`](R) reader structure
878impl crate::Readable for CFGR2rs {}
879///`write(|w| ..)` method takes [`cfgr2::W`](W) writer structure
880impl crate::Writable for CFGR2rs {
881    type Safety = crate::Unsafe;
882}
883///`reset()` method sets CFGR2 to value 0
884impl crate::Resettable for CFGR2rs {}