stm32g4 0.16.0

Device support crates for STM32G4 devices
Documentation 
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///Register `CCR5` reader
pub type R = crate::R<CCR5rs>;
///Register `CCR5` writer
pub type W = crate::W<CCR5rs>;
///Field `CCR` reader - Capture/Compare value
pub type CCR_R = crate::FieldReader<u32>;
///Field `CCR` writer - Capture/Compare value
pub type CCR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32, crate::Safe>;
///Field `GC5C1` reader - Group Channel 5 and Channel 1
pub type GC5C1_R = crate::BitReader;
///Field `GC5C1` writer - Group Channel 5 and Channel 1
pub type GC5C1_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `GC5C2` reader - Group Channel 5 and Channel 2
pub type GC5C2_R = crate::BitReader;
///Field `GC5C2` writer - Group Channel 5 and Channel 2
pub type GC5C2_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `GC5C3` reader - Group Channel 5 and Channel 3
pub type GC5C3_R = crate::BitReader;
///Field `GC5C3` writer - Group Channel 5 and Channel 3
pub type GC5C3_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bits 0:31 - Capture/Compare value
    #[inline(always)]
    pub fn ccr(&self) -> CCR_R {
        CCR_R::new(self.bits)
    }
    ///Bit 29 - Group Channel 5 and Channel 1
    #[inline(always)]
    pub fn gc5c1(&self) -> GC5C1_R {
        GC5C1_R::new(((self.bits >> 29) & 1) != 0)
    }
    ///Bit 30 - Group Channel 5 and Channel 2
    #[inline(always)]
    pub fn gc5c2(&self) -> GC5C2_R {
        GC5C2_R::new(((self.bits >> 30) & 1) != 0)
    }
    ///Bit 31 - Group Channel 5 and Channel 3
    #[inline(always)]
    pub fn gc5c3(&self) -> GC5C3_R {
        GC5C3_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CCR5")
            .field("ccr", &self.ccr())
            .field("gc5c1", &self.gc5c1())
            .field("gc5c2", &self.gc5c2())
            .field("gc5c3", &self.gc5c3())
            .finish()
    }
}
impl W {
    ///Bits 0:31 - Capture/Compare value
    #[inline(always)]
    pub fn ccr(&mut self) -> CCR_W<CCR5rs> {
        CCR_W::new(self, 0)
    }
    ///Bit 29 - Group Channel 5 and Channel 1
    #[inline(always)]
    pub fn gc5c1(&mut self) -> GC5C1_W<CCR5rs> {
        GC5C1_W::new(self, 29)
    }
    ///Bit 30 - Group Channel 5 and Channel 2
    #[inline(always)]
    pub fn gc5c2(&mut self) -> GC5C2_W<CCR5rs> {
        GC5C2_W::new(self, 30)
    }
    ///Bit 31 - Group Channel 5 and Channel 3
    #[inline(always)]
    pub fn gc5c3(&mut self) -> GC5C3_W<CCR5rs> {
        GC5C3_W::new(self, 31)
    }
}
/**capture/compare register

You can [`read`](crate::Reg::read) this register and get [`ccr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM2:CCR5)*/
pub struct CCR5rs;
impl crate::RegisterSpec for CCR5rs {
    type Ux = u32;
}
///`read()` method returns [`ccr5::R`](R) reader structure
impl crate::Readable for CCR5rs {}
///`write(|w| ..)` method takes [`ccr5::W`](W) writer structure
impl crate::Writable for CCR5rs {
    type Safety = crate::Safe;
}
///`reset()` method sets CCR5 to value 0
impl crate::Resettable for CCR5rs {}