stm32g4 0.16.0

/*!Peripheral access API for STM32G484 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))

You can find an overview of the generated API [here].

API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.

[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
[repository]: https://github.com/rust-embedded/svd2rust*/
///Number available in the NVIC for configuring priority
pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
    fn WWDG();
    fn PVD_PVM();
    fn RTC_TAMP_CSS_LSE();
    fn RTC_WKUP();
    fn FLASH();
    fn RCC();
    fn EXTI0();
    fn EXTI1();
    fn EXTI2();
    fn EXTI3();
    fn EXTI4();
    fn DMA1_CH1();
    fn DMA1_CH2();
    fn DMA1_CH3();
    fn DMA1_CH4();
    fn DMA1_CH5();
    fn DMA1_CH6();
    fn DMA1_CH7();
    fn ADC1_2();
    fn USB_HP();
    fn USB_LP();
    fn FDCAN1_IT0();
    fn FDCAN1_IT1();
    fn EXTI9_5();
    fn TIM1_BRK_TIM15();
    fn TIM1_UP_TIM16();
    fn TIM1_TRG_COM();
    fn TIM1_CC();
    fn TIM2();
    fn TIM3();
    fn TIM4();
    fn I2C1_EV();
    fn I2C1_ER();
    fn I2C2_EV();
    fn I2C2_ER();
    fn SPI1();
    fn SPI2();
    fn USART1();
    fn USART2();
    fn USART3();
    fn EXTI15_10();
    fn RTC_ALARM();
    fn USBWAKE_UP();
    fn TIM8_BRK();
    fn TIM8_UP();
    fn TIM8_TRG_COM();
    fn TIM8_CC();
    fn ADC3();
    fn FMC();
    fn LPTIM1();
    fn TIM5();
    fn SPI3();
    fn UART4();
    fn UART5();
    fn TIM6_DACUNDER();
    fn TIM7();
    fn DMA2_CH1();
    fn DMA2_CH2();
    fn DMA2_CH3();
    fn DMA2_CH4();
    fn DMA2_CH5();
    fn ADC4();
    fn ADC5();
    fn UCPD1();
    fn COMP1_2_3();
    fn COMP4_5_6();
    fn COMP7();
    fn HRTIM_MASTER_IRQN();
    fn HRTIM_TIMA_IRQN();
    fn HRTIM_TIMB_IRQN();
    fn HRTIM_TIMC_IRQN();
    fn HRTIM_TIMD_IRQN();
    fn HRTIM_TIME_IRQN();
    fn HRTIM_TIM_FLT_IRQN();
    fn HRTIM_TIMF_IRQN();
    fn CRS();
    fn SAI();
    fn TIM20_BRK();
    fn TIM20_UP();
    fn TIM20_TRG_COM();
    fn TIM20_CC();
    fn FPU();
    fn I2C4_EV();
    fn I2C4_ER();
    fn SPI4();
    fn AES();
    fn FDCAN2_IT0();
    fn FDCAN2_IT1();
    fn FDCAN3_IT0();
    fn FDCAN3_IT1();
    fn RNG();
    fn LPUART();
    fn I2C3_EV();
    fn I2C3_ER();
    fn DMAMUX_OVR();
    fn QUADSPI();
    fn DMA1_CH8();
    fn DMA2_CH6();
    fn DMA2_CH7();
    fn DMA2_CH8();
    fn CORDIC();
    fn FMAC();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
    _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 102] = [
    Vector { _handler: WWDG },
    Vector { _handler: PVD_PVM },
    Vector {
        _handler: RTC_TAMP_CSS_LSE,
    },
    Vector { _handler: RTC_WKUP },
    Vector { _handler: FLASH },
    Vector { _handler: RCC },
    Vector { _handler: EXTI0 },
    Vector { _handler: EXTI1 },
    Vector { _handler: EXTI2 },
    Vector { _handler: EXTI3 },
    Vector { _handler: EXTI4 },
    Vector { _handler: DMA1_CH1 },
    Vector { _handler: DMA1_CH2 },
    Vector { _handler: DMA1_CH3 },
    Vector { _handler: DMA1_CH4 },
    Vector { _handler: DMA1_CH5 },
    Vector { _handler: DMA1_CH6 },
    Vector { _handler: DMA1_CH7 },
    Vector { _handler: ADC1_2 },
    Vector { _handler: USB_HP },
    Vector { _handler: USB_LP },
    Vector {
        _handler: FDCAN1_IT0,
    },
    Vector {
        _handler: FDCAN1_IT1,
    },
    Vector { _handler: EXTI9_5 },
    Vector {
        _handler: TIM1_BRK_TIM15,
    },
    Vector {
        _handler: TIM1_UP_TIM16,
    },
    Vector {
        _handler: TIM1_TRG_COM,
    },
    Vector { _handler: TIM1_CC },
    Vector { _handler: TIM2 },
    Vector { _handler: TIM3 },
    Vector { _handler: TIM4 },
    Vector { _handler: I2C1_EV },
    Vector { _handler: I2C1_ER },
    Vector { _handler: I2C2_EV },
    Vector { _handler: I2C2_ER },
    Vector { _handler: SPI1 },
    Vector { _handler: SPI2 },
    Vector { _handler: USART1 },
    Vector { _handler: USART2 },
    Vector { _handler: USART3 },
    Vector {
        _handler: EXTI15_10,
    },
    Vector {
        _handler: RTC_ALARM,
    },
    Vector {
        _handler: USBWAKE_UP,
    },
    Vector { _handler: TIM8_BRK },
    Vector { _handler: TIM8_UP },
    Vector {
        _handler: TIM8_TRG_COM,
    },
    Vector { _handler: TIM8_CC },
    Vector { _handler: ADC3 },
    Vector { _handler: FMC },
    Vector { _handler: LPTIM1 },
    Vector { _handler: TIM5 },
    Vector { _handler: SPI3 },
    Vector { _handler: UART4 },
    Vector { _handler: UART5 },
    Vector {
        _handler: TIM6_DACUNDER,
    },
    Vector { _handler: TIM7 },
    Vector { _handler: DMA2_CH1 },
    Vector { _handler: DMA2_CH2 },
    Vector { _handler: DMA2_CH3 },
    Vector { _handler: DMA2_CH4 },
    Vector { _handler: DMA2_CH5 },
    Vector { _handler: ADC4 },
    Vector { _handler: ADC5 },
    Vector { _handler: UCPD1 },
    Vector {
        _handler: COMP1_2_3,
    },
    Vector {
        _handler: COMP4_5_6,
    },
    Vector { _handler: COMP7 },
    Vector {
        _handler: HRTIM_MASTER_IRQN,
    },
    Vector {
        _handler: HRTIM_TIMA_IRQN,
    },
    Vector {
        _handler: HRTIM_TIMB_IRQN,
    },
    Vector {
        _handler: HRTIM_TIMC_IRQN,
    },
    Vector {
        _handler: HRTIM_TIMD_IRQN,
    },
    Vector {
        _handler: HRTIM_TIME_IRQN,
    },
    Vector {
        _handler: HRTIM_TIM_FLT_IRQN,
    },
    Vector {
        _handler: HRTIM_TIMF_IRQN,
    },
    Vector { _handler: CRS },
    Vector { _handler: SAI },
    Vector {
        _handler: TIM20_BRK,
    },
    Vector { _handler: TIM20_UP },
    Vector {
        _handler: TIM20_TRG_COM,
    },
    Vector { _handler: TIM20_CC },
    Vector { _handler: FPU },
    Vector { _handler: I2C4_EV },
    Vector { _handler: I2C4_ER },
    Vector { _handler: SPI4 },
    Vector { _handler: AES },
    Vector {
        _handler: FDCAN2_IT0,
    },
    Vector {
        _handler: FDCAN2_IT1,
    },
    Vector {
        _handler: FDCAN3_IT0,
    },
    Vector {
        _handler: FDCAN3_IT1,
    },
    Vector { _handler: RNG },
    Vector { _handler: LPUART },
    Vector { _handler: I2C3_EV },
    Vector { _handler: I2C3_ER },
    Vector {
        _handler: DMAMUX_OVR,
    },
    Vector { _handler: QUADSPI },
    Vector { _handler: DMA1_CH8 },
    Vector { _handler: DMA2_CH6 },
    Vector { _handler: DMA2_CH7 },
    Vector { _handler: DMA2_CH8 },
    Vector { _handler: CORDIC },
    Vector { _handler: FMAC },
];
///Enumeration of all the interrupts.
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
    ///0 - Window Watchdog interrupt
    WWDG = 0,
    ///1 - PVD through EXTI line detection
    PVD_PVM = 1,
    ///2 - RTC_TAMP_CSS_LSE
    RTC_TAMP_CSS_LSE = 2,
    ///3 - RTC Wakeup timer
    RTC_WKUP = 3,
    ///4 - FLASH
    FLASH = 4,
    ///5 - RCC global interrupt
    RCC = 5,
    ///6 - EXTI Line0 interrupt
    EXTI0 = 6,
    ///7 - EXTI Line1 interrupt
    EXTI1 = 7,
    ///8 - EXTI Line2 interrupt
    EXTI2 = 8,
    ///9 - EXTI Line3 interrupt
    EXTI3 = 9,
    ///10 - EXTI Line4 interrupt
    EXTI4 = 10,
    ///11 - DMA1 channel 1 interrupt
    DMA1_CH1 = 11,
    ///12 - DMA1 channel 2 interrupt
    DMA1_CH2 = 12,
    ///13 - DMA1 channel 3 interrupt
    DMA1_CH3 = 13,
    ///14 - DMA1 channel 4 interrupt
    DMA1_CH4 = 14,
    ///15 - DMA1 channel 5 interrupt
    DMA1_CH5 = 15,
    ///16 - DMA1 channel 6 interrupt
    DMA1_CH6 = 16,
    ///17 - DMA1 channel 7 interrupt
    DMA1_CH7 = 17,
    ///18 - ADC1 and ADC2 global interrupt
    ADC1_2 = 18,
    ///19 - USB_HP
    USB_HP = 19,
    ///20 - USB_LP
    USB_LP = 20,
    ///21 - FDCAN1 interrupt 0
    FDCAN1_IT0 = 21,
    ///22 - FDCAN1 interrupt 1
    FDCAN1_IT1 = 22,
    ///23 - EXTI9_5
    EXTI9_5 = 23,
    ///24 - TIM1_BRK_TIM15
    TIM1_BRK_TIM15 = 24,
    ///25 - TIM1_UP_TIM16
    TIM1_UP_TIM16 = 25,
    ///26 - TIM1_TRG_COM/
    TIM1_TRG_COM = 26,
    ///27 - TIM1 capture compare interrupt
    TIM1_CC = 27,
    ///28 - TIM2
    TIM2 = 28,
    ///29 - TIM3
    TIM3 = 29,
    ///30 - TIM4
    TIM4 = 30,
    ///31 - I2C1_EV
    I2C1_EV = 31,
    ///32 - I2C1_ER
    I2C1_ER = 32,
    ///33 - I2C2_EV
    I2C2_EV = 33,
    ///34 - I2C2_ER
    I2C2_ER = 34,
    ///35 - SPI1
    SPI1 = 35,
    ///36 - SPI2
    SPI2 = 36,
    ///37 - USART1
    USART1 = 37,
    ///38 - USART2
    USART2 = 38,
    ///39 - USART3
    USART3 = 39,
    ///40 - EXTI15_10
    EXTI15_10 = 40,
    ///41 - RTC_ALARM
    RTC_ALARM = 41,
    ///42 - USBWakeUP
    USBWAKE_UP = 42,
    ///43 - TIM8_BRK
    TIM8_BRK = 43,
    ///44 - TIM8_UP
    TIM8_UP = 44,
    ///45 - TIM8_TRG_COM
    TIM8_TRG_COM = 45,
    ///46 - TIM8_CC
    TIM8_CC = 46,
    ///47 - ADC3
    ADC3 = 47,
    ///48 - FMC
    FMC = 48,
    ///49 - LPTIM1
    LPTIM1 = 49,
    ///50 - TIM5
    TIM5 = 50,
    ///51 - SPI3
    SPI3 = 51,
    ///52 - UART4
    UART4 = 52,
    ///53 - UART5
    UART5 = 53,
    ///54 - TIM6_DACUNDER
    TIM6_DACUNDER = 54,
    ///55 - TIM7
    TIM7 = 55,
    ///56 - DMA2_CH1
    DMA2_CH1 = 56,
    ///57 - DMA2_CH2
    DMA2_CH2 = 57,
    ///58 - DMA2_CH3
    DMA2_CH3 = 58,
    ///59 - DMA2_CH4
    DMA2_CH4 = 59,
    ///60 - DMA2_CH5
    DMA2_CH5 = 60,
    ///61 - ADC4
    ADC4 = 61,
    ///62 - ADC5
    ADC5 = 62,
    ///63 - UCPD1
    UCPD1 = 63,
    ///64 - COMP1_2_3
    COMP1_2_3 = 64,
    ///65 - COMP4_5_6
    COMP4_5_6 = 65,
    ///66 - COMP7
    COMP7 = 66,
    ///67 - HRTIM_Master_IRQn
    HRTIM_MASTER_IRQN = 67,
    ///68 - HRTIM_TIMA_IRQn
    HRTIM_TIMA_IRQN = 68,
    ///69 - HRTIM_TIMB_IRQn
    HRTIM_TIMB_IRQN = 69,
    ///70 - HRTIM_TIMC_IRQn
    HRTIM_TIMC_IRQN = 70,
    ///71 - HRTIM_TIMD_IRQn
    HRTIM_TIMD_IRQN = 71,
    ///72 - HRTIM_TIME_IRQn
    HRTIM_TIME_IRQN = 72,
    ///73 - HRTIM_TIM_FLT_IRQn
    HRTIM_TIM_FLT_IRQN = 73,
    ///74 - HRTIM_TIMF_IRQn
    HRTIM_TIMF_IRQN = 74,
    ///75 - CRS
    CRS = 75,
    ///76 - SAI
    SAI = 76,
    ///77 - TIM20_BRK
    TIM20_BRK = 77,
    ///78 - TIM20_UP
    TIM20_UP = 78,
    ///79 - TIM20_TRG_COM
    TIM20_TRG_COM = 79,
    ///80 - TIM20_CC
    TIM20_CC = 80,
    ///81 - Floating point unit interrupt
    FPU = 81,
    ///82 - I2C4_EV
    I2C4_EV = 82,
    ///83 - I2C4_ER
    I2C4_ER = 83,
    ///84 - SPI4
    SPI4 = 84,
    ///85 - AES
    AES = 85,
    ///86 - FDCAN2 interrupt 0
    FDCAN2_IT0 = 86,
    ///87 - FDCAN2 interrupt 1
    FDCAN2_IT1 = 87,
    ///88 - FDCAN3 interrupt 0
    FDCAN3_IT0 = 88,
    ///89 - FDCAN3 interrupt 1
    FDCAN3_IT1 = 89,
    ///90 - RNG
    RNG = 90,
    ///91 - LPUART
    LPUART = 91,
    ///92 - I2C3_EV
    I2C3_EV = 92,
    ///93 - I2C3_ER
    I2C3_ER = 93,
    ///94 - DMAMUX_OVR
    DMAMUX_OVR = 94,
    ///95 - QUADSPI
    QUADSPI = 95,
    ///96 - DMA1_CH8
    DMA1_CH8 = 96,
    ///97 - DMA2_CH6
    DMA2_CH6 = 97,
    ///98 - DMA2_CH7
    DMA2_CH7 = 98,
    ///99 - DMA2_CH8
    DMA2_CH8 = 99,
    ///100 - Cordic
    CORDIC = 100,
    ///101 - FMAC
    FMAC = 101,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}
///Cyclic redundancy check calculation unit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#CRC)
pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
impl core::fmt::Debug for CRC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRC").finish()
    }
}
///Cyclic redundancy check calculation unit
pub mod crc;
///WinWATCHDOG
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#IWDG)
pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for IWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IWDG").finish()
    }
}
///WinWATCHDOG
pub mod iwdg;
///System window watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#WWDG)
pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
impl core::fmt::Debug for WWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WWDG").finish()
    }
}
///System window watchdog
pub mod wwdg;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#I2C1)
pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
impl core::fmt::Debug for I2C1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C1").finish()
    }
}
///Inter-integrated circuit
pub mod i2c1;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#I2C1)
pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
impl core::fmt::Debug for I2C2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C2").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c2;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#I2C1)
pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_7800>;
impl core::fmt::Debug for I2C3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C3").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c3;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#I2C1)
pub type I2C4 = crate::Periph<i2c1::RegisterBlock, 0x4000_8400>;
impl core::fmt::Debug for I2C4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C4").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c4;
///Flash
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#FLASH)
pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
impl core::fmt::Debug for FLASH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FLASH").finish()
    }
}
///Flash
pub mod flash;
///Debug support
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#DBGMCU)
pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
impl core::fmt::Debug for DBGMCU {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DBGMCU").finish()
    }
}
///Debug support
pub mod dbgmcu;
///Reset and clock control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#RCC)
pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
impl core::fmt::Debug for RCC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RCC").finish()
    }
}
///Reset and clock control
pub mod rcc;
///Power control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#PWR)
pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
impl core::fmt::Debug for PWR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PWR").finish()
    }
}
///Power control
pub mod pwr;
///Random number generator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#RNG)
pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
impl core::fmt::Debug for RNG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RNG").finish()
    }
}
///Random number generator
pub mod rng;
///Advanced encryption standard hardware accelerator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#AES)
pub type AES = crate::Periph<aes::RegisterBlock, 0x5006_0000>;
impl core::fmt::Debug for AES {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("AES").finish()
    }
}
///Advanced encryption standard hardware accelerator
pub mod aes;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#GPIOA)
pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4800_0000>;
impl core::fmt::Debug for GPIOA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOA").finish()
    }
}
///General-purpose I/Os
pub mod gpioa;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#GPIOB)
pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4800_0400>;
impl core::fmt::Debug for GPIOB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOB").finish()
    }
}
///General-purpose I/Os
pub mod gpiob;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#GPIOC)
pub type GPIOC = crate::Periph<gpioc::RegisterBlock, 0x4800_0800>;
impl core::fmt::Debug for GPIOC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOC").finish()
    }
}
///General-purpose I/Os
pub mod gpioc;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#GPIOC)
pub type GPIOD = crate::Periph<gpioc::RegisterBlock, 0x4800_0c00>;
impl core::fmt::Debug for GPIOD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOD").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpiod;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#GPIOC)
pub type GPIOE = crate::Periph<gpioc::RegisterBlock, 0x4800_1000>;
impl core::fmt::Debug for GPIOE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOE").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpioe;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#GPIOC)
pub type GPIOF = crate::Periph<gpioc::RegisterBlock, 0x4800_1400>;
impl core::fmt::Debug for GPIOF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOF").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpiof;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#GPIOC)
pub type GPIOG = crate::Periph<gpioc::RegisterBlock, 0x4800_1800>;
impl core::fmt::Debug for GPIOG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOG").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpiog;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM15)
pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for TIM15 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM15").finish()
    }
}
///General purpose timers
pub mod tim15;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM16)
pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4001_4400>;
impl core::fmt::Debug for TIM16 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM16").finish()
    }
}
///General purpose timers
pub mod tim16;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM16)
pub type TIM17 = crate::Periph<tim16::RegisterBlock, 0x4001_4800>;
impl core::fmt::Debug for TIM17 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM17").finish()
    }
}
///General purpose timers
pub use self::tim16 as tim17;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1)
pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
impl core::fmt::Debug for TIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM1").finish()
    }
}
///Advanced-timers
pub mod tim1;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1)
pub type TIM20 = crate::Periph<tim1::RegisterBlock, 0x4001_5000>;
impl core::fmt::Debug for TIM20 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM20").finish()
    }
}
///Advanced-timers
pub use self::tim1 as tim20;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM1)
pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_3400>;
impl core::fmt::Debug for TIM8 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM8").finish()
    }
}
///Advanced-timers
pub use self::tim1 as tim8;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM2)
pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for TIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM2").finish()
    }
}
///Advanced-timers
pub mod tim2;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM3)
pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
impl core::fmt::Debug for TIM3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM3").finish()
    }
}
///Advanced-timers
pub mod tim3;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM3)
pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
impl core::fmt::Debug for TIM4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM4").finish()
    }
}
///Advanced-timers
pub use self::tim3 as tim4;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM2)
pub type TIM5 = crate::Periph<tim2::RegisterBlock, 0x4000_0c00>;
impl core::fmt::Debug for TIM5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM5").finish()
    }
}
///Advanced-timers
pub use self::tim2 as tim5;
///Basic-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM6)
pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for TIM6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM6").finish()
    }
}
///Basic-timers
pub mod tim6;
///Basic-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TIM6)
pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
impl core::fmt::Debug for TIM7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM7").finish()
    }
}
///Basic-timers
pub use self::tim6 as tim7;
///Low power timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#LPTIMER1)
pub type LPTIMER1 = crate::Periph<lptimer1::RegisterBlock, 0x4000_7c00>;
impl core::fmt::Debug for LPTIMER1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIMER1").finish()
    }
}
///Low power timer
pub mod lptimer1;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#USART1)
pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
impl core::fmt::Debug for USART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod usart1;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#USART1)
pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
impl core::fmt::Debug for USART2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART2").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart2;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#USART1)
pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
impl core::fmt::Debug for USART3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART3").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart3;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#UART4)
pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
impl core::fmt::Debug for UART4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART4").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod uart4;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#UART4)
pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for UART5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART5").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::uart4 as uart5;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#LPUART1)
pub type LPUART1 = crate::Periph<lpuart1::RegisterBlock, 0x4000_8000>;
impl core::fmt::Debug for LPUART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPUART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod lpuart1;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#SPI1)
pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for SPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI1").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub mod spi1;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#SPI1)
pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4001_3c00>;
impl core::fmt::Debug for SPI4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI4").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub use self::spi1 as spi4;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#SPI1)
pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
impl core::fmt::Debug for SPI3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI3").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub use self::spi1 as spi3;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#SPI1)
pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
impl core::fmt::Debug for SPI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI2").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub use self::spi1 as spi2;
///External interrupt/event controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#EXTI)
pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
impl core::fmt::Debug for EXTI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EXTI").finish()
    }
}
///External interrupt/event controller
pub mod exti;
///Real-time clock
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#RTC)
pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
impl core::fmt::Debug for RTC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RTC").finish()
    }
}
///Real-time clock
pub mod rtc;
///Flexible memory controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#FMC)
pub type FMC = crate::Periph<fmc::RegisterBlock, 0xa000_0000>;
impl core::fmt::Debug for FMC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FMC").finish()
    }
}
///Flexible memory controller
pub mod fmc;
///DMA controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#DMA1)
pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for DMA1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA1").finish()
    }
}
///DMA controller
pub mod dma1;
///DMA controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#DMA1)
pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
impl core::fmt::Debug for DMA2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA2").finish()
    }
}
///DMA controller
pub use self::dma1 as dma2;
///DMAMUX
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#DMAMUX)
pub type DMAMUX = crate::Periph<dmamux::RegisterBlock, 0x4002_0800>;
impl core::fmt::Debug for DMAMUX {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMAMUX").finish()
    }
}
///DMAMUX
pub mod dmamux;
///System configuration controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#SYSCFG)
pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for SYSCFG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYSCFG").finish()
    }
}
///System configuration controller
pub mod syscfg;
///Voltage reference buffer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#VREFBUF)
pub type VREFBUF = crate::Periph<vrefbuf::RegisterBlock, 0x4001_0030>;
impl core::fmt::Debug for VREFBUF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("VREFBUF").finish()
    }
}
///Voltage reference buffer
pub mod vrefbuf;
///Comparator control and status register
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#COMP)
pub type COMP = crate::Periph<comp::RegisterBlock, 0x4001_0200>;
impl core::fmt::Debug for COMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("COMP").finish()
    }
}
///Comparator control and status register
pub mod comp;
///Operational amplifiers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#OPAMP)
pub type OPAMP = crate::Periph<opamp::RegisterBlock, 0x4001_0300>;
impl core::fmt::Debug for OPAMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OPAMP").finish()
    }
}
///Operational amplifiers
pub mod opamp;
///High Resolution Timer: Master Timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#HRTIM_Master)
pub type HRTIM_MASTER = crate::Periph<hrtim_master::RegisterBlock, 0x4001_6800>;
impl core::fmt::Debug for HRTIM_MASTER {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HRTIM_MASTER").finish()
    }
}
///High Resolution Timer: Master Timers
pub mod hrtim_master;
///High Resolution Timer: TIMA
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#HRTIM_TIMA)
pub type HRTIM_TIMA = crate::Periph<hrtim_tima::RegisterBlock, 0x4001_6880>;
impl core::fmt::Debug for HRTIM_TIMA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HRTIM_TIMA").finish()
    }
}
///High Resolution Timer: TIMA
pub mod hrtim_tima;
///High Resolution Timer: TIMB
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#HRTIM_TIMB)
pub type HRTIM_TIMB = crate::Periph<hrtim_timb::RegisterBlock, 0x4001_6900>;
impl core::fmt::Debug for HRTIM_TIMB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HRTIM_TIMB").finish()
    }
}
///High Resolution Timer: TIMB
pub mod hrtim_timb;
///High Resolution Timer: TIMC
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#HRTIM_TIMC)
pub type HRTIM_TIMC = crate::Periph<hrtim_timc::RegisterBlock, 0x4001_6980>;
impl core::fmt::Debug for HRTIM_TIMC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HRTIM_TIMC").finish()
    }
}
///High Resolution Timer: TIMC
pub mod hrtim_timc;
///High Resolution Timer: TIMD
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#HRTIM_TIMD)
pub type HRTIM_TIMD = crate::Periph<hrtim_timd::RegisterBlock, 0x4001_6a00>;
impl core::fmt::Debug for HRTIM_TIMD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HRTIM_TIMD").finish()
    }
}
///High Resolution Timer: TIMD
pub mod hrtim_timd;
///High Resolution Timer: TIME
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#HRTIM_TIME)
pub type HRTIM_TIME = crate::Periph<hrtim_time::RegisterBlock, 0x4001_6a80>;
impl core::fmt::Debug for HRTIM_TIME {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HRTIM_TIME").finish()
    }
}
///High Resolution Timer: TIME
pub mod hrtim_time;
///High Resolution Timer: TIMF
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#HRTIM_TIMF)
pub type HRTIM_TIMF = crate::Periph<hrtim_timf::RegisterBlock, 0x4001_6b00>;
impl core::fmt::Debug for HRTIM_TIMF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HRTIM_TIMF").finish()
    }
}
///High Resolution Timer: TIMF
pub mod hrtim_timf;
///High Resolution Timer: Common functions
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#HRTIM_Common)
pub type HRTIM_COMMON = crate::Periph<hrtim_common::RegisterBlock, 0x4001_6b80>;
impl core::fmt::Debug for HRTIM_COMMON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HRTIM_COMMON").finish()
    }
}
///High Resolution Timer: Common functions
pub mod hrtim_common;
///QuadSPI interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#QUADSPI)
pub type QUADSPI = crate::Periph<quadspi::RegisterBlock, 0xa000_1000>;
impl core::fmt::Debug for QUADSPI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("QUADSPI").finish()
    }
}
///QuadSPI interface
pub mod quadspi;
///Digital-to-analog converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#DAC1)
pub type DAC1 = crate::Periph<dac1::RegisterBlock, 0x5000_0800>;
impl core::fmt::Debug for DAC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC1").finish()
    }
}
///Digital-to-analog converter
pub mod dac1;
///Digital-to-analog converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#DAC1)
pub type DAC2 = crate::Periph<dac1::RegisterBlock, 0x5000_0c00>;
impl core::fmt::Debug for DAC2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC2").finish()
    }
}
///Digital-to-analog converter
pub use self::dac1 as dac2;
///Digital-to-analog converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#DAC1)
pub type DAC3 = crate::Periph<dac1::RegisterBlock, 0x5000_1000>;
impl core::fmt::Debug for DAC3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC3").finish()
    }
}
///Digital-to-analog converter
pub use self::dac1 as dac3;
///Digital-to-analog converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#DAC1)
pub type DAC4 = crate::Periph<dac1::RegisterBlock, 0x5000_1400>;
impl core::fmt::Debug for DAC4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC4").finish()
    }
}
///Digital-to-analog converter
pub use self::dac1 as dac4;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#ADC1)
pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x5000_0000>;
impl core::fmt::Debug for ADC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC1").finish()
    }
}
///Analog-to-Digital Converter
pub mod adc1;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#ADC1)
pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x5000_0100>;
impl core::fmt::Debug for ADC2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC2").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc1 as adc2;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#ADC1)
pub type ADC3 = crate::Periph<adc1::RegisterBlock, 0x5000_0400>;
impl core::fmt::Debug for ADC3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC3").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc1 as adc3;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#ADC1)
pub type ADC4 = crate::Periph<adc1::RegisterBlock, 0x5000_0500>;
impl core::fmt::Debug for ADC4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC4").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc1 as adc4;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#ADC1)
pub type ADC5 = crate::Periph<adc1::RegisterBlock, 0x5000_0600>;
impl core::fmt::Debug for ADC5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC5").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc1 as adc5;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#ADC12_Common)
pub type ADC12_COMMON = crate::Periph<adc12_common::RegisterBlock, 0x5000_0300>;
impl core::fmt::Debug for ADC12_COMMON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC12_COMMON").finish()
    }
}
///Analog-to-Digital Converter
pub mod adc12_common;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#ADC12_Common)
pub type ADC345_COMMON = crate::Periph<adc12_common::RegisterBlock, 0x5000_0700>;
impl core::fmt::Debug for ADC345_COMMON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC345_COMMON").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc12_common as adc345_common;
///Filter Math Accelerator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#FMAC)
pub type FMAC = crate::Periph<fmac::RegisterBlock, 0x4002_1400>;
impl core::fmt::Debug for FMAC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FMAC").finish()
    }
}
///Filter Math Accelerator
pub mod fmac;
///CORDIC Co-processor
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#CORDIC)
pub type CORDIC = crate::Periph<cordic::RegisterBlock, 0x4002_0c00>;
impl core::fmt::Debug for CORDIC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CORDIC").finish()
    }
}
///CORDIC Co-processor
pub mod cordic;
///Serial audio interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#SAI)
pub type SAI = crate::Periph<sai::RegisterBlock, 0x4001_5400>;
impl core::fmt::Debug for SAI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SAI").finish()
    }
}
///Serial audio interface
pub mod sai;
///Tamper and backup registers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#TAMP)
pub type TAMP = crate::Periph<tamp::RegisterBlock, 0x4000_2400>;
impl core::fmt::Debug for TAMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TAMP").finish()
    }
}
///Tamper and backup registers
pub mod tamp;
///FDCAN
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#FDCAN)
pub type FDCAN = crate::Periph<fdcan::RegisterBlock, 0x4000_a400>;
impl core::fmt::Debug for FDCAN {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FDCAN").finish()
    }
}
///FDCAN
pub mod fdcan;
///FDCAN
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#FDCAN)
pub type FDCAN1 = crate::Periph<fdcan::RegisterBlock, 0x4000_6400>;
impl core::fmt::Debug for FDCAN1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FDCAN1").finish()
    }
}
///FDCAN
pub use self::fdcan as fdcan1;
///FDCAN
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#FDCAN)
pub type FDCAN2 = crate::Periph<fdcan::RegisterBlock, 0x4000_6800>;
impl core::fmt::Debug for FDCAN2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FDCAN2").finish()
    }
}
///FDCAN
pub use self::fdcan as fdcan2;
///FDCAN
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#FDCAN)
pub type FDCAN3 = crate::Periph<fdcan::RegisterBlock, 0x4000_6c00>;
impl core::fmt::Debug for FDCAN3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FDCAN3").finish()
    }
}
///FDCAN
pub use self::fdcan as fdcan3;
///UCPD1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#UCPD1)
pub type UCPD1 = crate::Periph<ucpd1::RegisterBlock, 0x4000_a000>;
impl core::fmt::Debug for UCPD1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UCPD1").finish()
    }
}
///UCPD1
pub mod ucpd1;
///USB_FS_device
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#USB)
pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
impl core::fmt::Debug for USB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USB").finish()
    }
}
///USB_FS_device
pub mod usb;
///CRS
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32G484.html#CRS)
pub type CRS = crate::Periph<crs::RegisterBlock, 0x4000_2000>;
impl core::fmt::Debug for CRS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRS").finish()
    }
}
///CRS
pub mod crs;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
/// All the peripherals.
#[allow(non_snake_case)]
pub struct Peripherals {
    ///CRC
    pub CRC: CRC,
    ///IWDG
    pub IWDG: IWDG,
    ///WWDG
    pub WWDG: WWDG,
    ///I2C1
    pub I2C1: I2C1,
    ///I2C2
    pub I2C2: I2C2,
    ///I2C3
    pub I2C3: I2C3,
    ///I2C4
    pub I2C4: I2C4,
    ///FLASH
    pub FLASH: FLASH,
    ///DBGMCU
    pub DBGMCU: DBGMCU,
    ///RCC
    pub RCC: RCC,
    ///PWR
    pub PWR: PWR,
    ///RNG
    pub RNG: RNG,
    ///AES
    pub AES: AES,
    ///GPIOA
    pub GPIOA: GPIOA,
    ///GPIOB
    pub GPIOB: GPIOB,
    ///GPIOC
    pub GPIOC: GPIOC,
    ///GPIOD
    pub GPIOD: GPIOD,
    ///GPIOE
    pub GPIOE: GPIOE,
    ///GPIOF
    pub GPIOF: GPIOF,
    ///GPIOG
    pub GPIOG: GPIOG,
    ///TIM15
    pub TIM15: TIM15,
    ///TIM16
    pub TIM16: TIM16,
    ///TIM17
    pub TIM17: TIM17,
    ///TIM1
    pub TIM1: TIM1,
    ///TIM20
    pub TIM20: TIM20,
    ///TIM8
    pub TIM8: TIM8,
    ///TIM2
    pub TIM2: TIM2,
    ///TIM3
    pub TIM3: TIM3,
    ///TIM4
    pub TIM4: TIM4,
    ///TIM5
    pub TIM5: TIM5,
    ///TIM6
    pub TIM6: TIM6,
    ///TIM7
    pub TIM7: TIM7,
    ///LPTIMER1
    pub LPTIMER1: LPTIMER1,
    ///USART1
    pub USART1: USART1,
    ///USART2
    pub USART2: USART2,
    ///USART3
    pub USART3: USART3,
    ///UART4
    pub UART4: UART4,
    ///UART5
    pub UART5: UART5,
    ///LPUART1
    pub LPUART1: LPUART1,
    ///SPI1
    pub SPI1: SPI1,
    ///SPI4
    pub SPI4: SPI4,
    ///SPI3
    pub SPI3: SPI3,
    ///SPI2
    pub SPI2: SPI2,
    ///EXTI
    pub EXTI: EXTI,
    ///RTC
    pub RTC: RTC,
    ///FMC
    pub FMC: FMC,
    ///DMA1
    pub DMA1: DMA1,
    ///DMA2
    pub DMA2: DMA2,
    ///DMAMUX
    pub DMAMUX: DMAMUX,
    ///SYSCFG
    pub SYSCFG: SYSCFG,
    ///VREFBUF
    pub VREFBUF: VREFBUF,
    ///COMP
    pub COMP: COMP,
    ///OPAMP
    pub OPAMP: OPAMP,
    ///HRTIM_Master
    pub HRTIM_MASTER: HRTIM_MASTER,
    ///HRTIM_TIMA
    pub HRTIM_TIMA: HRTIM_TIMA,
    ///HRTIM_TIMB
    pub HRTIM_TIMB: HRTIM_TIMB,
    ///HRTIM_TIMC
    pub HRTIM_TIMC: HRTIM_TIMC,
    ///HRTIM_TIMD
    pub HRTIM_TIMD: HRTIM_TIMD,
    ///HRTIM_TIME
    pub HRTIM_TIME: HRTIM_TIME,
    ///HRTIM_TIMF
    pub HRTIM_TIMF: HRTIM_TIMF,
    ///HRTIM_Common
    pub HRTIM_COMMON: HRTIM_COMMON,
    ///QUADSPI
    pub QUADSPI: QUADSPI,
    ///DAC1
    pub DAC1: DAC1,
    ///DAC2
    pub DAC2: DAC2,
    ///DAC3
    pub DAC3: DAC3,
    ///DAC4
    pub DAC4: DAC4,
    ///ADC1
    pub ADC1: ADC1,
    ///ADC2
    pub ADC2: ADC2,
    ///ADC3
    pub ADC3: ADC3,
    ///ADC4
    pub ADC4: ADC4,
    ///ADC5
    pub ADC5: ADC5,
    ///ADC12_Common
    pub ADC12_COMMON: ADC12_COMMON,
    ///ADC345_Common
    pub ADC345_COMMON: ADC345_COMMON,
    ///FMAC
    pub FMAC: FMAC,
    ///CORDIC
    pub CORDIC: CORDIC,
    ///SAI
    pub SAI: SAI,
    ///TAMP
    pub TAMP: TAMP,
    ///FDCAN
    pub FDCAN: FDCAN,
    ///FDCAN1
    pub FDCAN1: FDCAN1,
    ///FDCAN2
    pub FDCAN2: FDCAN2,
    ///FDCAN3
    pub FDCAN3: FDCAN3,
    ///UCPD1
    pub UCPD1: UCPD1,
    ///USB
    pub USB: USB,
    ///CRS
    pub CRS: CRS,
}
impl Peripherals {
    /// Returns all the peripherals *once*.
    #[cfg(feature = "critical-section")]
    #[inline]
    pub fn take() -> Option<Self> {
        critical_section::with(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                return None;
            }
            Some(unsafe { Peripherals::steal() })
        })
    }
    /// Unchecked version of `Peripherals::take`.
    ///
    /// # Safety
    ///
    /// Each of the returned peripherals must be used at most once.
    #[inline]
    pub unsafe fn steal() -> Self {
        DEVICE_PERIPHERALS = true;
        Peripherals {
            CRC: CRC::steal(),
            IWDG: IWDG::steal(),
            WWDG: WWDG::steal(),
            I2C1: I2C1::steal(),
            I2C2: I2C2::steal(),
            I2C3: I2C3::steal(),
            I2C4: I2C4::steal(),
            FLASH: FLASH::steal(),
            DBGMCU: DBGMCU::steal(),
            RCC: RCC::steal(),
            PWR: PWR::steal(),
            RNG: RNG::steal(),
            AES: AES::steal(),
            GPIOA: GPIOA::steal(),
            GPIOB: GPIOB::steal(),
            GPIOC: GPIOC::steal(),
            GPIOD: GPIOD::steal(),
            GPIOE: GPIOE::steal(),
            GPIOF: GPIOF::steal(),
            GPIOG: GPIOG::steal(),
            TIM15: TIM15::steal(),
            TIM16: TIM16::steal(),
            TIM17: TIM17::steal(),
            TIM1: TIM1::steal(),
            TIM20: TIM20::steal(),
            TIM8: TIM8::steal(),
            TIM2: TIM2::steal(),
            TIM3: TIM3::steal(),
            TIM4: TIM4::steal(),
            TIM5: TIM5::steal(),
            TIM6: TIM6::steal(),
            TIM7: TIM7::steal(),
            LPTIMER1: LPTIMER1::steal(),
            USART1: USART1::steal(),
            USART2: USART2::steal(),
            USART3: USART3::steal(),
            UART4: UART4::steal(),
            UART5: UART5::steal(),
            LPUART1: LPUART1::steal(),
            SPI1: SPI1::steal(),
            SPI4: SPI4::steal(),
            SPI3: SPI3::steal(),
            SPI2: SPI2::steal(),
            EXTI: EXTI::steal(),
            RTC: RTC::steal(),
            FMC: FMC::steal(),
            DMA1: DMA1::steal(),
            DMA2: DMA2::steal(),
            DMAMUX: DMAMUX::steal(),
            SYSCFG: SYSCFG::steal(),
            VREFBUF: VREFBUF::steal(),
            COMP: COMP::steal(),
            OPAMP: OPAMP::steal(),
            HRTIM_MASTER: HRTIM_MASTER::steal(),
            HRTIM_TIMA: HRTIM_TIMA::steal(),
            HRTIM_TIMB: HRTIM_TIMB::steal(),
            HRTIM_TIMC: HRTIM_TIMC::steal(),
            HRTIM_TIMD: HRTIM_TIMD::steal(),
            HRTIM_TIME: HRTIM_TIME::steal(),
            HRTIM_TIMF: HRTIM_TIMF::steal(),
            HRTIM_COMMON: HRTIM_COMMON::steal(),
            QUADSPI: QUADSPI::steal(),
            DAC1: DAC1::steal(),
            DAC2: DAC2::steal(),
            DAC3: DAC3::steal(),
            DAC4: DAC4::steal(),
            ADC1: ADC1::steal(),
            ADC2: ADC2::steal(),
            ADC3: ADC3::steal(),
            ADC4: ADC4::steal(),
            ADC5: ADC5::steal(),
            ADC12_COMMON: ADC12_COMMON::steal(),
            ADC345_COMMON: ADC345_COMMON::steal(),
            FMAC: FMAC::steal(),
            CORDIC: CORDIC::steal(),
            SAI: SAI::steal(),
            TAMP: TAMP::steal(),
            FDCAN: FDCAN::steal(),
            FDCAN1: FDCAN1::steal(),
            FDCAN2: FDCAN2::steal(),
            FDCAN3: FDCAN3::steal(),
            UCPD1: UCPD1::steal(),
            USB: USB::steal(),
            CRS: CRS::steal(),
        }
    }
}