stm32g4-staging 0.22.0

Device support crates for STM32G4 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213

///Register `APB2SMENR` reader
pub type R = crate::R<APB2SMENRrs>;
///Register `APB2SMENR` writer
pub type W = crate::W<APB2SMENRrs>;
///Field `SYSCFGSMEN` reader - SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes Set and cleared by software.
pub type SYSCFGSMEN_R = crate::BitReader;
///Field `SYSCFGSMEN` writer - SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes Set and cleared by software.
pub type SYSCFGSMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIM1SMEN` reader - TIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM1SMEN_R = crate::BitReader;
///Field `TIM1SMEN` writer - TIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM1SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SPI1SMEN` reader - SPI1 clocks enable during Sleep and Stop modes Set and cleared by software.
pub type SPI1SMEN_R = crate::BitReader;
///Field `SPI1SMEN` writer - SPI1 clocks enable during Sleep and Stop modes Set and cleared by software.
pub type SPI1SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIM8SMEN` reader - TIM8 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM8SMEN_R = crate::BitReader;
///Field `TIM8SMEN` writer - TIM8 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM8SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `USART1SMEN` reader - USART1clocks enable during Sleep and Stop modes Set and cleared by software.
pub type USART1SMEN_R = crate::BitReader;
///Field `USART1SMEN` writer - USART1clocks enable during Sleep and Stop modes Set and cleared by software.
pub type USART1SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SPI4SMEN` reader - SPI4 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type SPI4SMEN_R = crate::BitReader;
///Field `SPI4SMEN` writer - SPI4 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type SPI4SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIM15SMEN` reader - TIM15 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM15SMEN_R = crate::BitReader;
///Field `TIM15SMEN` writer - TIM15 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM15SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIM16SMEN` reader - TIM16 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM16SMEN_R = crate::BitReader;
///Field `TIM16SMEN` writer - TIM16 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM16SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIM17SMEN` reader - TIM17 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM17SMEN_R = crate::BitReader;
///Field `TIM17SMEN` writer - TIM17 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM17SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIM20SMEN` reader - TIM20 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM20SMEN_R = crate::BitReader;
///Field `TIM20SMEN` writer - TIM20 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type TIM20SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `SAI1SMEN` reader - SAI1 clocks enable during Sleep and Stop modes Set and cleared by software.
pub type SAI1SMEN_R = crate::BitReader;
///Field `SAI1SMEN` writer - SAI1 clocks enable during Sleep and Stop modes Set and cleared by software.
pub type SAI1SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `HRTIM1SMEN` reader - HRTIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type HRTIM1SMEN_R = crate::BitReader;
///Field `HRTIM1SMEN` writer - HRTIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software.
pub type HRTIM1SMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bit 0 - SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn syscfgsmen(&self) -> SYSCFGSMEN_R {
        SYSCFGSMEN_R::new((self.bits & 1) != 0)
    }
    ///Bit 11 - TIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim1smen(&self) -> TIM1SMEN_R {
        TIM1SMEN_R::new(((self.bits >> 11) & 1) != 0)
    }
    ///Bit 12 - SPI1 clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn spi1smen(&self) -> SPI1SMEN_R {
        SPI1SMEN_R::new(((self.bits >> 12) & 1) != 0)
    }
    ///Bit 13 - TIM8 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim8smen(&self) -> TIM8SMEN_R {
        TIM8SMEN_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - USART1clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn usart1smen(&self) -> USART1SMEN_R {
        USART1SMEN_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - SPI4 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn spi4smen(&self) -> SPI4SMEN_R {
        SPI4SMEN_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - TIM15 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim15smen(&self) -> TIM15SMEN_R {
        TIM15SMEN_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bit 17 - TIM16 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim16smen(&self) -> TIM16SMEN_R {
        TIM16SMEN_R::new(((self.bits >> 17) & 1) != 0)
    }
    ///Bit 18 - TIM17 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim17smen(&self) -> TIM17SMEN_R {
        TIM17SMEN_R::new(((self.bits >> 18) & 1) != 0)
    }
    ///Bit 20 - TIM20 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim20smen(&self) -> TIM20SMEN_R {
        TIM20SMEN_R::new(((self.bits >> 20) & 1) != 0)
    }
    ///Bit 21 - SAI1 clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn sai1smen(&self) -> SAI1SMEN_R {
        SAI1SMEN_R::new(((self.bits >> 21) & 1) != 0)
    }
    ///Bit 26 - HRTIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn hrtim1smen(&self) -> HRTIM1SMEN_R {
        HRTIM1SMEN_R::new(((self.bits >> 26) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("APB2SMENR")
            .field("syscfgsmen", &self.syscfgsmen())
            .field("tim1smen", &self.tim1smen())
            .field("spi1smen", &self.spi1smen())
            .field("tim8smen", &self.tim8smen())
            .field("usart1smen", &self.usart1smen())
            .field("spi4smen", &self.spi4smen())
            .field("tim15smen", &self.tim15smen())
            .field("tim16smen", &self.tim16smen())
            .field("tim17smen", &self.tim17smen())
            .field("tim20smen", &self.tim20smen())
            .field("sai1smen", &self.sai1smen())
            .field("hrtim1smen", &self.hrtim1smen())
            .finish()
    }
}
impl W {
    ///Bit 0 - SYSCFG + COMP + VREFBUF + OPAMP clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn syscfgsmen(&mut self) -> SYSCFGSMEN_W<APB2SMENRrs> {
        SYSCFGSMEN_W::new(self, 0)
    }
    ///Bit 11 - TIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim1smen(&mut self) -> TIM1SMEN_W<APB2SMENRrs> {
        TIM1SMEN_W::new(self, 11)
    }
    ///Bit 12 - SPI1 clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn spi1smen(&mut self) -> SPI1SMEN_W<APB2SMENRrs> {
        SPI1SMEN_W::new(self, 12)
    }
    ///Bit 13 - TIM8 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim8smen(&mut self) -> TIM8SMEN_W<APB2SMENRrs> {
        TIM8SMEN_W::new(self, 13)
    }
    ///Bit 14 - USART1clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn usart1smen(&mut self) -> USART1SMEN_W<APB2SMENRrs> {
        USART1SMEN_W::new(self, 14)
    }
    ///Bit 15 - SPI4 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn spi4smen(&mut self) -> SPI4SMEN_W<APB2SMENRrs> {
        SPI4SMEN_W::new(self, 15)
    }
    ///Bit 16 - TIM15 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim15smen(&mut self) -> TIM15SMEN_W<APB2SMENRrs> {
        TIM15SMEN_W::new(self, 16)
    }
    ///Bit 17 - TIM16 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim16smen(&mut self) -> TIM16SMEN_W<APB2SMENRrs> {
        TIM16SMEN_W::new(self, 17)
    }
    ///Bit 18 - TIM17 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim17smen(&mut self) -> TIM17SMEN_W<APB2SMENRrs> {
        TIM17SMEN_W::new(self, 18)
    }
    ///Bit 20 - TIM20 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn tim20smen(&mut self) -> TIM20SMEN_W<APB2SMENRrs> {
        TIM20SMEN_W::new(self, 20)
    }
    ///Bit 21 - SAI1 clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn sai1smen(&mut self) -> SAI1SMEN_W<APB2SMENRrs> {
        SAI1SMEN_W::new(self, 21)
    }
    ///Bit 26 - HRTIM1 timer clocks enable during Sleep and Stop modes Set and cleared by software.
    #[inline(always)]
    pub fn hrtim1smen(&mut self) -> HRTIM1SMEN_W<APB2SMENRrs> {
        HRTIM1SMEN_W::new(self, 26)
    }
}
/**APB2 peripheral clocks enable in Sleep and Stop modes register

You can [`read`](crate::Reg::read) this register and get [`apb2smenr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2smenr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G474.html#RCC:APB2SMENR)*/
pub struct APB2SMENRrs;
impl crate::RegisterSpec for APB2SMENRrs {
    type Ux = u32;
}
///`read()` method returns [`apb2smenr::R`](R) reader structure
impl crate::Readable for APB2SMENRrs {}
///`write(|w| ..)` method takes [`apb2smenr::W`](W) writer structure
impl crate::Writable for APB2SMENRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets APB2SMENR to value 0x0437_f801
impl crate::Resettable for APB2SMENRrs {
    const RESET_VALUE: u32 = 0x0437_f801;
}