pub struct W(_);
Expand description
Register SR
writer
Implementations
sourceimpl W
impl W
sourcepub fn ceis(&mut self) -> CEIS_W<'_, 5>
pub fn ceis(&mut self) -> CEIS_W<'_, 5>
Bit 5 - Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.
Methods from Deref<Target = W<SR_SPEC>>
Trait Implementations
Auto Trait Implementations
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more