stm32g0/stm32g0c1/tim15/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Register `SR` writer
4pub type W = crate::W<SRrs>;
5/**Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UIFR {
11    ///0: No update occurred
12    NoUpdateOccurred = 0,
13    ///1: Update interrupt pending
14    UpdatePending = 1,
15}
16impl From<UIFR> for bool {
17    #[inline(always)]
18    fn from(variant: UIFR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UIF` reader - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
23pub type UIF_R = crate::BitReader<UIFR>;
24impl UIF_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UIFR {
28        match self.bits {
29            false => UIFR::NoUpdateOccurred,
30            true => UIFR::UpdatePending,
31        }
32    }
33    ///No update occurred
34    #[inline(always)]
35    pub fn is_no_update_occurred(&self) -> bool {
36        *self == UIFR::NoUpdateOccurred
37    }
38    ///Update interrupt pending
39    #[inline(always)]
40    pub fn is_update_pending(&self) -> bool {
41        *self == UIFR::UpdatePending
42    }
43}
44/**Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum UIFW {
50    ///0: Clear flag
51    Clear = 0,
52}
53impl From<UIFW> for bool {
54    #[inline(always)]
55    fn from(variant: UIFW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `UIF` writer - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
60pub type UIF_W<'a, REG> = crate::BitWriter0C<'a, REG, UIFW>;
61impl<'a, REG> UIF_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Clear flag
66    #[inline(always)]
67    pub fn clear(self) -> &'a mut crate::W<REG> {
68        self.variant(UIFW::Clear)
69    }
70}
71/**Capture/compare %s interrupt flag
72
73Value on reset: 0*/
74#[cfg_attr(feature = "defmt", derive(defmt::Format))]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum CC1IFR {
77    ///0: No campture/compare has been detected
78    NoMatch = 0,
79    ///1: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
80    Match = 1,
81}
82impl From<CC1IFR> for bool {
83    #[inline(always)]
84    fn from(variant: CC1IFR) -> Self {
85        variant as u8 != 0
86    }
87}
88///Field `CCIF(1-2)` reader - Capture/compare %s interrupt flag
89pub type CCIF_R = crate::BitReader<CC1IFR>;
90impl CCIF_R {
91    ///Get enumerated values variant
92    #[inline(always)]
93    pub const fn variant(&self) -> CC1IFR {
94        match self.bits {
95            false => CC1IFR::NoMatch,
96            true => CC1IFR::Match,
97        }
98    }
99    ///No campture/compare has been detected
100    #[inline(always)]
101    pub fn is_no_match(&self) -> bool {
102        *self == CC1IFR::NoMatch
103    }
104    ///If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
105    #[inline(always)]
106    pub fn is_match(&self) -> bool {
107        *self == CC1IFR::Match
108    }
109}
110/**Capture/compare %s interrupt flag
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum CC1IFW {
116    ///0: Clear flag
117    Clear = 0,
118}
119impl From<CC1IFW> for bool {
120    #[inline(always)]
121    fn from(variant: CC1IFW) -> Self {
122        variant as u8 != 0
123    }
124}
125///Field `CCIF(1-2)` writer - Capture/compare %s interrupt flag
126pub type CCIF_W<'a, REG> = crate::BitWriter0C<'a, REG, CC1IFW>;
127impl<'a, REG> CCIF_W<'a, REG>
128where
129    REG: crate::Writable + crate::RegisterSpec,
130{
131    ///Clear flag
132    #[inline(always)]
133    pub fn clear(self) -> &'a mut crate::W<REG> {
134        self.variant(CC1IFW::Clear)
135    }
136}
137/**COM interrupt flag.
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum COMIFR {
143    ///0: No COM event occurred
144    NoCom = 0,
145    ///1: COM interrupt pending
146    Com = 1,
147}
148impl From<COMIFR> for bool {
149    #[inline(always)]
150    fn from(variant: COMIFR) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `COMIF` reader - COM interrupt flag.
155pub type COMIF_R = crate::BitReader<COMIFR>;
156impl COMIF_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> COMIFR {
160        match self.bits {
161            false => COMIFR::NoCom,
162            true => COMIFR::Com,
163        }
164    }
165    ///No COM event occurred
166    #[inline(always)]
167    pub fn is_no_com(&self) -> bool {
168        *self == COMIFR::NoCom
169    }
170    ///COM interrupt pending
171    #[inline(always)]
172    pub fn is_com(&self) -> bool {
173        *self == COMIFR::Com
174    }
175}
176/**COM interrupt flag.
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum COMIFW {
182    ///0: Clear flag
183    Clear = 0,
184}
185impl From<COMIFW> for bool {
186    #[inline(always)]
187    fn from(variant: COMIFW) -> Self {
188        variant as u8 != 0
189    }
190}
191///Field `COMIF` writer - COM interrupt flag.
192pub type COMIF_W<'a, REG> = crate::BitWriter0C<'a, REG, COMIFW>;
193impl<'a, REG> COMIF_W<'a, REG>
194where
195    REG: crate::Writable + crate::RegisterSpec,
196{
197    ///Clear flag
198    #[inline(always)]
199    pub fn clear(self) -> &'a mut crate::W<REG> {
200        self.variant(COMIFW::Clear)
201    }
202}
203/**Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
204
205Value on reset: 0*/
206#[cfg_attr(feature = "defmt", derive(defmt::Format))]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208pub enum TIFR {
209    ///0: No trigger event occurred
210    NoTrigger = 0,
211    ///1: Trigger interrupt pending
212    Trigger = 1,
213}
214impl From<TIFR> for bool {
215    #[inline(always)]
216    fn from(variant: TIFR) -> Self {
217        variant as u8 != 0
218    }
219}
220///Field `TIF` reader - Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
221pub type TIF_R = crate::BitReader<TIFR>;
222impl TIF_R {
223    ///Get enumerated values variant
224    #[inline(always)]
225    pub const fn variant(&self) -> TIFR {
226        match self.bits {
227            false => TIFR::NoTrigger,
228            true => TIFR::Trigger,
229        }
230    }
231    ///No trigger event occurred
232    #[inline(always)]
233    pub fn is_no_trigger(&self) -> bool {
234        *self == TIFR::NoTrigger
235    }
236    ///Trigger interrupt pending
237    #[inline(always)]
238    pub fn is_trigger(&self) -> bool {
239        *self == TIFR::Trigger
240    }
241}
242/**Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
243
244Value on reset: 0*/
245#[cfg_attr(feature = "defmt", derive(defmt::Format))]
246#[derive(Clone, Copy, Debug, PartialEq, Eq)]
247pub enum TIFW {
248    ///0: Clear flag
249    Clear = 0,
250}
251impl From<TIFW> for bool {
252    #[inline(always)]
253    fn from(variant: TIFW) -> Self {
254        variant as u8 != 0
255    }
256}
257///Field `TIF` writer - Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
258pub type TIF_W<'a, REG> = crate::BitWriter0C<'a, REG, TIFW>;
259impl<'a, REG> TIF_W<'a, REG>
260where
261    REG: crate::Writable + crate::RegisterSpec,
262{
263    ///Clear flag
264    #[inline(always)]
265    pub fn clear(self) -> &'a mut crate::W<REG> {
266        self.variant(TIFW::Clear)
267    }
268}
269/**Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
270
271Value on reset: 0*/
272#[cfg_attr(feature = "defmt", derive(defmt::Format))]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum BIFR {
275    ///0: No break event occurred
276    NoTrigger = 0,
277    ///1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
278    Trigger = 1,
279}
280impl From<BIFR> for bool {
281    #[inline(always)]
282    fn from(variant: BIFR) -> Self {
283        variant as u8 != 0
284    }
285}
286///Field `BIF` reader - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
287pub type BIF_R = crate::BitReader<BIFR>;
288impl BIF_R {
289    ///Get enumerated values variant
290    #[inline(always)]
291    pub const fn variant(&self) -> BIFR {
292        match self.bits {
293            false => BIFR::NoTrigger,
294            true => BIFR::Trigger,
295        }
296    }
297    ///No break event occurred
298    #[inline(always)]
299    pub fn is_no_trigger(&self) -> bool {
300        *self == BIFR::NoTrigger
301    }
302    ///An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
303    #[inline(always)]
304    pub fn is_trigger(&self) -> bool {
305        *self == BIFR::Trigger
306    }
307}
308/**Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
309
310Value on reset: 0*/
311#[cfg_attr(feature = "defmt", derive(defmt::Format))]
312#[derive(Clone, Copy, Debug, PartialEq, Eq)]
313pub enum BIFW {
314    ///0: Clear flag
315    Clear = 0,
316}
317impl From<BIFW> for bool {
318    #[inline(always)]
319    fn from(variant: BIFW) -> Self {
320        variant as u8 != 0
321    }
322}
323///Field `BIF` writer - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
324pub type BIF_W<'a, REG> = crate::BitWriter0C<'a, REG, BIFW>;
325impl<'a, REG> BIF_W<'a, REG>
326where
327    REG: crate::Writable + crate::RegisterSpec,
328{
329    ///Clear flag
330    #[inline(always)]
331    pub fn clear(self) -> &'a mut crate::W<REG> {
332        self.variant(BIFW::Clear)
333    }
334}
335/**Capture/Compare %s overcapture flag
336
337Value on reset: 0*/
338#[cfg_attr(feature = "defmt", derive(defmt::Format))]
339#[derive(Clone, Copy, Debug, PartialEq, Eq)]
340pub enum CC1OFR {
341    ///0: No overcapture has been detected
342    NoOvercapture = 0,
343    ///1: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
344    Overcapture = 1,
345}
346impl From<CC1OFR> for bool {
347    #[inline(always)]
348    fn from(variant: CC1OFR) -> Self {
349        variant as u8 != 0
350    }
351}
352///Field `CCOF(1-2)` reader - Capture/Compare %s overcapture flag
353pub type CCOF_R = crate::BitReader<CC1OFR>;
354impl CCOF_R {
355    ///Get enumerated values variant
356    #[inline(always)]
357    pub const fn variant(&self) -> CC1OFR {
358        match self.bits {
359            false => CC1OFR::NoOvercapture,
360            true => CC1OFR::Overcapture,
361        }
362    }
363    ///No overcapture has been detected
364    #[inline(always)]
365    pub fn is_no_overcapture(&self) -> bool {
366        *self == CC1OFR::NoOvercapture
367    }
368    ///The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
369    #[inline(always)]
370    pub fn is_overcapture(&self) -> bool {
371        *self == CC1OFR::Overcapture
372    }
373}
374/**Capture/Compare %s overcapture flag
375
376Value on reset: 0*/
377#[cfg_attr(feature = "defmt", derive(defmt::Format))]
378#[derive(Clone, Copy, Debug, PartialEq, Eq)]
379pub enum CC1OFW {
380    ///0: Clear flag
381    Clear = 0,
382}
383impl From<CC1OFW> for bool {
384    #[inline(always)]
385    fn from(variant: CC1OFW) -> Self {
386        variant as u8 != 0
387    }
388}
389///Field `CCOF(1-2)` writer - Capture/Compare %s overcapture flag
390pub type CCOF_W<'a, REG> = crate::BitWriter0C<'a, REG, CC1OFW>;
391impl<'a, REG> CCOF_W<'a, REG>
392where
393    REG: crate::Writable + crate::RegisterSpec,
394{
395    ///Clear flag
396    #[inline(always)]
397    pub fn clear(self) -> &'a mut crate::W<REG> {
398        self.variant(CC1OFW::Clear)
399    }
400}
401impl R {
402    ///Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
403    #[inline(always)]
404    pub fn uif(&self) -> UIF_R {
405        UIF_R::new((self.bits & 1) != 0)
406    }
407    ///Capture/compare (1-2) interrupt flag
408    ///
409    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IF` field.</div>
410    #[inline(always)]
411    pub fn ccif(&self, n: u8) -> CCIF_R {
412        #[allow(clippy::no_effect)]
413        [(); 2][n as usize];
414        CCIF_R::new(((self.bits >> (n + 1)) & 1) != 0)
415    }
416    ///Iterator for array of:
417    ///Capture/compare (1-2) interrupt flag
418    #[inline(always)]
419    pub fn ccif_iter(&self) -> impl Iterator<Item = CCIF_R> + '_ {
420        (0..2).map(move |n| CCIF_R::new(((self.bits >> (n + 1)) & 1) != 0))
421    }
422    ///Bit 1 - Capture/compare 1 interrupt flag
423    #[inline(always)]
424    pub fn cc1if(&self) -> CCIF_R {
425        CCIF_R::new(((self.bits >> 1) & 1) != 0)
426    }
427    ///Bit 2 - Capture/compare 2 interrupt flag
428    #[inline(always)]
429    pub fn cc2if(&self) -> CCIF_R {
430        CCIF_R::new(((self.bits >> 2) & 1) != 0)
431    }
432    ///Bit 5 - COM interrupt flag.
433    #[inline(always)]
434    pub fn comif(&self) -> COMIF_R {
435        COMIF_R::new(((self.bits >> 5) & 1) != 0)
436    }
437    ///Bit 6 - Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
438    #[inline(always)]
439    pub fn tif(&self) -> TIF_R {
440        TIF_R::new(((self.bits >> 6) & 1) != 0)
441    }
442    ///Bit 7 - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
443    #[inline(always)]
444    pub fn bif(&self) -> BIF_R {
445        BIF_R::new(((self.bits >> 7) & 1) != 0)
446    }
447    ///Capture/Compare (1-2) overcapture flag
448    ///
449    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1OF` field.</div>
450    #[inline(always)]
451    pub fn ccof(&self, n: u8) -> CCOF_R {
452        #[allow(clippy::no_effect)]
453        [(); 2][n as usize];
454        CCOF_R::new(((self.bits >> (n + 9)) & 1) != 0)
455    }
456    ///Iterator for array of:
457    ///Capture/Compare (1-2) overcapture flag
458    #[inline(always)]
459    pub fn ccof_iter(&self) -> impl Iterator<Item = CCOF_R> + '_ {
460        (0..2).map(move |n| CCOF_R::new(((self.bits >> (n + 9)) & 1) != 0))
461    }
462    ///Bit 9 - Capture/Compare 1 overcapture flag
463    #[inline(always)]
464    pub fn cc1of(&self) -> CCOF_R {
465        CCOF_R::new(((self.bits >> 9) & 1) != 0)
466    }
467    ///Bit 10 - Capture/Compare 2 overcapture flag
468    #[inline(always)]
469    pub fn cc2of(&self) -> CCOF_R {
470        CCOF_R::new(((self.bits >> 10) & 1) != 0)
471    }
472}
473impl core::fmt::Debug for R {
474    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
475        f.debug_struct("SR")
476            .field("uif", &self.uif())
477            .field("cc1if", &self.cc1if())
478            .field("cc2if", &self.cc2if())
479            .field("comif", &self.comif())
480            .field("tif", &self.tif())
481            .field("bif", &self.bif())
482            .field("cc1of", &self.cc1of())
483            .field("cc2of", &self.cc2of())
484            .finish()
485    }
486}
487impl W {
488    ///Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
489    #[inline(always)]
490    pub fn uif(&mut self) -> UIF_W<SRrs> {
491        UIF_W::new(self, 0)
492    }
493    ///Capture/compare (1-2) interrupt flag
494    ///
495    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IF` field.</div>
496    #[inline(always)]
497    pub fn ccif(&mut self, n: u8) -> CCIF_W<SRrs> {
498        #[allow(clippy::no_effect)]
499        [(); 2][n as usize];
500        CCIF_W::new(self, n + 1)
501    }
502    ///Bit 1 - Capture/compare 1 interrupt flag
503    #[inline(always)]
504    pub fn cc1if(&mut self) -> CCIF_W<SRrs> {
505        CCIF_W::new(self, 1)
506    }
507    ///Bit 2 - Capture/compare 2 interrupt flag
508    #[inline(always)]
509    pub fn cc2if(&mut self) -> CCIF_W<SRrs> {
510        CCIF_W::new(self, 2)
511    }
512    ///Bit 5 - COM interrupt flag.
513    #[inline(always)]
514    pub fn comif(&mut self) -> COMIF_W<SRrs> {
515        COMIF_W::new(self, 5)
516    }
517    ///Bit 6 - Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
518    #[inline(always)]
519    pub fn tif(&mut self) -> TIF_W<SRrs> {
520        TIF_W::new(self, 6)
521    }
522    ///Bit 7 - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
523    #[inline(always)]
524    pub fn bif(&mut self) -> BIF_W<SRrs> {
525        BIF_W::new(self, 7)
526    }
527    ///Capture/Compare (1-2) overcapture flag
528    ///
529    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1OF` field.</div>
530    #[inline(always)]
531    pub fn ccof(&mut self, n: u8) -> CCOF_W<SRrs> {
532        #[allow(clippy::no_effect)]
533        [(); 2][n as usize];
534        CCOF_W::new(self, n + 9)
535    }
536    ///Bit 9 - Capture/Compare 1 overcapture flag
537    #[inline(always)]
538    pub fn cc1of(&mut self) -> CCOF_W<SRrs> {
539        CCOF_W::new(self, 9)
540    }
541    ///Bit 10 - Capture/Compare 2 overcapture flag
542    #[inline(always)]
543    pub fn cc2of(&mut self) -> CCOF_W<SRrs> {
544        CCOF_W::new(self, 10)
545    }
546}
547/**status register
548
549You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
550
551See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM15:SR)*/
552pub struct SRrs;
553impl crate::RegisterSpec for SRrs {
554    type Ux = u32;
555}
556///`read()` method returns [`sr::R`](R) reader structure
557impl crate::Readable for SRrs {}
558///`write(|w| ..)` method takes [`sr::W`](W) writer structure
559impl crate::Writable for SRrs {
560    type Safety = crate::Unsafe;
561    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x06e7;
562}
563///`reset()` method sets SR to value 0
564impl crate::Resettable for SRrs {}
stm32g0/stm32g0c1/tim15/sr.rs

stm32g0/stm32g0c1/tim15/
sr.rs
