stm32g0/stm32g041/pwr/
cr3.rs

1///Register `CR3` reader
2pub type R = crate::R<CR3rs>;
3///Register `CR3` writer
4pub type W = crate::W<CR3rs>;
5///Field `EWUP1` reader - Enable Wakeup pin WKUP1
6pub type EWUP1_R = crate::BitReader;
7///Field `EWUP1` writer - Enable Wakeup pin WKUP1
8pub type EWUP1_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `EWUP2` reader - Enable Wakeup pin WKUP2
10pub type EWUP2_R = crate::BitReader;
11///Field `EWUP2` writer - Enable Wakeup pin WKUP2
12pub type EWUP2_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `EWUP3` reader - Enable Wakeup pin WKUP3
14pub type EWUP3_R = crate::BitReader;
15///Field `EWUP3` writer - Enable Wakeup pin WKUP3
16pub type EWUP3_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `EWUP4` reader - Enable Wakeup pin WKUP4
18pub type EWUP4_R = crate::BitReader;
19///Field `EWUP4` writer - Enable Wakeup pin WKUP4
20pub type EWUP4_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `EWUP5` reader - Enable WKUP5 wakeup pin
22pub type EWUP5_R = crate::BitReader;
23///Field `EWUP5` writer - Enable WKUP5 wakeup pin
24pub type EWUP5_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `EWUP6` reader - Enable WKUP6 wakeup pin
26pub type EWUP6_R = crate::BitReader;
27///Field `EWUP6` writer - Enable WKUP6 wakeup pin
28pub type EWUP6_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `RRS` reader - SRAM retention in Standby mode
30pub type RRS_R = crate::BitReader;
31///Field `RRS` writer - SRAM retention in Standby mode
32pub type RRS_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `ENB_ULP` reader - Ultra-low-power enable
34pub type ENB_ULP_R = crate::BitReader;
35///Field `ENB_ULP` writer - Ultra-low-power enable
36pub type ENB_ULP_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `APC` reader - Apply pull-up and pull-down configuration
38pub type APC_R = crate::BitReader;
39///Field `APC` writer - Apply pull-up and pull-down configuration
40pub type APC_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `EIWUL` reader - Enable internal wakeup line
42pub type EIWUL_R = crate::BitReader;
43///Field `EIWUL` writer - Enable internal wakeup line
44pub type EIWUL_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    ///Bit 0 - Enable Wakeup pin WKUP1
47    #[inline(always)]
48    pub fn ewup1(&self) -> EWUP1_R {
49        EWUP1_R::new((self.bits & 1) != 0)
50    }
51    ///Bit 1 - Enable Wakeup pin WKUP2
52    #[inline(always)]
53    pub fn ewup2(&self) -> EWUP2_R {
54        EWUP2_R::new(((self.bits >> 1) & 1) != 0)
55    }
56    ///Bit 2 - Enable Wakeup pin WKUP3
57    #[inline(always)]
58    pub fn ewup3(&self) -> EWUP3_R {
59        EWUP3_R::new(((self.bits >> 2) & 1) != 0)
60    }
61    ///Bit 3 - Enable Wakeup pin WKUP4
62    #[inline(always)]
63    pub fn ewup4(&self) -> EWUP4_R {
64        EWUP4_R::new(((self.bits >> 3) & 1) != 0)
65    }
66    ///Bit 4 - Enable WKUP5 wakeup pin
67    #[inline(always)]
68    pub fn ewup5(&self) -> EWUP5_R {
69        EWUP5_R::new(((self.bits >> 4) & 1) != 0)
70    }
71    ///Bit 5 - Enable WKUP6 wakeup pin
72    #[inline(always)]
73    pub fn ewup6(&self) -> EWUP6_R {
74        EWUP6_R::new(((self.bits >> 5) & 1) != 0)
75    }
76    ///Bit 8 - SRAM retention in Standby mode
77    #[inline(always)]
78    pub fn rrs(&self) -> RRS_R {
79        RRS_R::new(((self.bits >> 8) & 1) != 0)
80    }
81    ///Bit 9 - Ultra-low-power enable
82    #[inline(always)]
83    pub fn enb_ulp(&self) -> ENB_ULP_R {
84        ENB_ULP_R::new(((self.bits >> 9) & 1) != 0)
85    }
86    ///Bit 10 - Apply pull-up and pull-down configuration
87    #[inline(always)]
88    pub fn apc(&self) -> APC_R {
89        APC_R::new(((self.bits >> 10) & 1) != 0)
90    }
91    ///Bit 15 - Enable internal wakeup line
92    #[inline(always)]
93    pub fn eiwul(&self) -> EIWUL_R {
94        EIWUL_R::new(((self.bits >> 15) & 1) != 0)
95    }
96}
97impl core::fmt::Debug for R {
98    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
99        f.debug_struct("CR3")
100            .field("ewup1", &self.ewup1())
101            .field("ewup2", &self.ewup2())
102            .field("ewup3", &self.ewup3())
103            .field("ewup4", &self.ewup4())
104            .field("ewup5", &self.ewup5())
105            .field("ewup6", &self.ewup6())
106            .field("rrs", &self.rrs())
107            .field("enb_ulp", &self.enb_ulp())
108            .field("apc", &self.apc())
109            .field("eiwul", &self.eiwul())
110            .finish()
111    }
112}
113impl W {
114    ///Bit 0 - Enable Wakeup pin WKUP1
115    #[inline(always)]
116    pub fn ewup1(&mut self) -> EWUP1_W<CR3rs> {
117        EWUP1_W::new(self, 0)
118    }
119    ///Bit 1 - Enable Wakeup pin WKUP2
120    #[inline(always)]
121    pub fn ewup2(&mut self) -> EWUP2_W<CR3rs> {
122        EWUP2_W::new(self, 1)
123    }
124    ///Bit 2 - Enable Wakeup pin WKUP3
125    #[inline(always)]
126    pub fn ewup3(&mut self) -> EWUP3_W<CR3rs> {
127        EWUP3_W::new(self, 2)
128    }
129    ///Bit 3 - Enable Wakeup pin WKUP4
130    #[inline(always)]
131    pub fn ewup4(&mut self) -> EWUP4_W<CR3rs> {
132        EWUP4_W::new(self, 3)
133    }
134    ///Bit 4 - Enable WKUP5 wakeup pin
135    #[inline(always)]
136    pub fn ewup5(&mut self) -> EWUP5_W<CR3rs> {
137        EWUP5_W::new(self, 4)
138    }
139    ///Bit 5 - Enable WKUP6 wakeup pin
140    #[inline(always)]
141    pub fn ewup6(&mut self) -> EWUP6_W<CR3rs> {
142        EWUP6_W::new(self, 5)
143    }
144    ///Bit 8 - SRAM retention in Standby mode
145    #[inline(always)]
146    pub fn rrs(&mut self) -> RRS_W<CR3rs> {
147        RRS_W::new(self, 8)
148    }
149    ///Bit 9 - Ultra-low-power enable
150    #[inline(always)]
151    pub fn enb_ulp(&mut self) -> ENB_ULP_W<CR3rs> {
152        ENB_ULP_W::new(self, 9)
153    }
154    ///Bit 10 - Apply pull-up and pull-down configuration
155    #[inline(always)]
156    pub fn apc(&mut self) -> APC_W<CR3rs> {
157        APC_W::new(self, 10)
158    }
159    ///Bit 15 - Enable internal wakeup line
160    #[inline(always)]
161    pub fn eiwul(&mut self) -> EIWUL_W<CR3rs> {
162        EIWUL_W::new(self, 15)
163    }
164}
165/**Power control register 3
166
167You can [`read`](crate::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
168
169See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#PWR:CR3)*/
170pub struct CR3rs;
171impl crate::RegisterSpec for CR3rs {
172    type Ux = u32;
173}
174///`read()` method returns [`cr3::R`](R) reader structure
175impl crate::Readable for CR3rs {}
176///`write(|w| ..)` method takes [`cr3::W`](W) writer structure
177impl crate::Writable for CR3rs {
178    type Safety = crate::Unsafe;
179}
180///`reset()` method sets CR3 to value 0x8000
181impl crate::Resettable for CR3rs {
182    const RESET_VALUE: u32 = 0x8000;
183}
stm32g0/stm32g041/pwr/cr3.rs

stm32g0/stm32g041/pwr/
cr3.rs
