stm32g0 0.16.0

Device support crates for STM32G0 devices
Documentation 
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///Register `TISEL` reader
pub type R = crate::R<TISELrs>;
///Register `TISEL` writer
pub type W = crate::W<TISELrs>;
///Field `TI1SEL3_0` reader - selects TI1\[0\] to TI1\[15\] input
pub type TI1SEL3_0_R = crate::FieldReader;
///Field `TI1SEL3_0` writer - selects TI1\[0\] to TI1\[15\] input
pub type TI1SEL3_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
///Field `TI2SEL3_0` reader - selects TI2\[0\] to TI2\[15\] input
pub type TI2SEL3_0_R = crate::FieldReader;
///Field `TI2SEL3_0` writer - selects TI2\[0\] to TI2\[15\] input
pub type TI2SEL3_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
///Field `TI3SEL3_0` reader - selects TI3\[0\] to TI3\[15\] input
pub type TI3SEL3_0_R = crate::FieldReader;
///Field `TI3SEL3_0` writer - selects TI3\[0\] to TI3\[15\] input
pub type TI3SEL3_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
///Field `TI4SEL3_0` reader - selects TI4\[0\] to TI4\[15\] input
pub type TI4SEL3_0_R = crate::FieldReader;
///Field `TI4SEL3_0` writer - selects TI4\[0\] to TI4\[15\] input
pub type TI4SEL3_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
    ///Bits 0:3 - selects TI1\[0\] to TI1\[15\] input
    #[inline(always)]
    pub fn ti1sel3_0(&self) -> TI1SEL3_0_R {
        TI1SEL3_0_R::new((self.bits & 0x0f) as u8)
    }
    ///Bits 8:11 - selects TI2\[0\] to TI2\[15\] input
    #[inline(always)]
    pub fn ti2sel3_0(&self) -> TI2SEL3_0_R {
        TI2SEL3_0_R::new(((self.bits >> 8) & 0x0f) as u8)
    }
    ///Bits 16:19 - selects TI3\[0\] to TI3\[15\] input
    #[inline(always)]
    pub fn ti3sel3_0(&self) -> TI3SEL3_0_R {
        TI3SEL3_0_R::new(((self.bits >> 16) & 0x0f) as u8)
    }
    ///Bits 24:27 - selects TI4\[0\] to TI4\[15\] input
    #[inline(always)]
    pub fn ti4sel3_0(&self) -> TI4SEL3_0_R {
        TI4SEL3_0_R::new(((self.bits >> 24) & 0x0f) as u8)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TISEL")
            .field("ti1sel3_0", &self.ti1sel3_0())
            .field("ti2sel3_0", &self.ti2sel3_0())
            .field("ti3sel3_0", &self.ti3sel3_0())
            .field("ti4sel3_0", &self.ti4sel3_0())
            .finish()
    }
}
impl W {
    ///Bits 0:3 - selects TI1\[0\] to TI1\[15\] input
    #[inline(always)]
    pub fn ti1sel3_0(&mut self) -> TI1SEL3_0_W<TISELrs> {
        TI1SEL3_0_W::new(self, 0)
    }
    ///Bits 8:11 - selects TI2\[0\] to TI2\[15\] input
    #[inline(always)]
    pub fn ti2sel3_0(&mut self) -> TI2SEL3_0_W<TISELrs> {
        TI2SEL3_0_W::new(self, 8)
    }
    ///Bits 16:19 - selects TI3\[0\] to TI3\[15\] input
    #[inline(always)]
    pub fn ti3sel3_0(&mut self) -> TI3SEL3_0_W<TISELrs> {
        TI3SEL3_0_W::new(self, 16)
    }
    ///Bits 24:27 - selects TI4\[0\] to TI4\[15\] input
    #[inline(always)]
    pub fn ti4sel3_0(&mut self) -> TI4SEL3_0_W<TISELrs> {
        TI4SEL3_0_W::new(self, 24)
    }
}
/**TIM1 timer input selection register

You can [`read`](crate::Reg::read) this register and get [`tisel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#TIM1:TISEL)*/
pub struct TISELrs;
impl crate::RegisterSpec for TISELrs {
    type Ux = u32;
}
///`read()` method returns [`tisel::R`](R) reader structure
impl crate::Readable for TISELrs {}
///`write(|w| ..)` method takes [`tisel::W`](W) writer structure
impl crate::Writable for TISELrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets TISEL to value 0
impl crate::Resettable for TISELrs {}