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#[doc = "Reader of register APBSMENR1"] pub type R = crate::R<u32, super::APBSMENR1>; #[doc = "Writer for register APBSMENR1"] pub type W = crate::W<u32, super::APBSMENR1>; #[doc = "Register APBSMENR1 `reset()`'s with value 0"] impl crate::ResetValue for super::APBSMENR1 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `TIM2SMEN`"] pub type TIM2SMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TIM2SMEN`"] pub struct TIM2SMEN_W<'a> { w: &'a mut W, } impl<'a> TIM2SMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = "Reader of field `TIM3SMEN`"] pub type TIM3SMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TIM3SMEN`"] pub struct TIM3SMEN_W<'a> { w: &'a mut W, } impl<'a> TIM3SMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `RTCAPBSMEN`"] pub type RTCAPBSMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `RTCAPBSMEN`"] pub struct RTCAPBSMEN_W<'a> { w: &'a mut W, } impl<'a> RTCAPBSMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); self.w } } #[doc = "Reader of field `WWDGSMEN`"] pub type WWDGSMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `WWDGSMEN`"] pub struct WWDGSMEN_W<'a> { w: &'a mut W, } impl<'a> WWDGSMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); self.w } } #[doc = "Reader of field `SPI2SMEN`"] pub type SPI2SMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SPI2SMEN`"] pub struct SPI2SMEN_W<'a> { w: &'a mut W, } impl<'a> SPI2SMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); self.w } } #[doc = "Reader of field `USART2SMEN`"] pub type USART2SMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `USART2SMEN`"] pub struct USART2SMEN_W<'a> { w: &'a mut W, } impl<'a> USART2SMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); self.w } } #[doc = "Reader of field `LPUART1SMEN`"] pub type LPUART1SMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `LPUART1SMEN`"] pub struct LPUART1SMEN_W<'a> { w: &'a mut W, } impl<'a> LPUART1SMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); self.w } } #[doc = "Reader of field `I2C1SMEN`"] pub type I2C1SMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `I2C1SMEN`"] pub struct I2C1SMEN_W<'a> { w: &'a mut W, } impl<'a> I2C1SMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); self.w } } #[doc = "Reader of field `I2C2SMEN`"] pub type I2C2SMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `I2C2SMEN`"] pub struct I2C2SMEN_W<'a> { w: &'a mut W, } impl<'a> I2C2SMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); self.w } } #[doc = "Reader of field `DBGSMEN`"] pub type DBGSMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBGSMEN`"] pub struct DBGSMEN_W<'a> { w: &'a mut W, } impl<'a> DBGSMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27); self.w } } #[doc = "Reader of field `PWRSMEN`"] pub type PWRSMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PWRSMEN`"] pub struct PWRSMEN_W<'a> { w: &'a mut W, } impl<'a> PWRSMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28); self.w } } #[doc = "Reader of field `LPTIM2SMEN`"] pub type LPTIM2SMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `LPTIM2SMEN`"] pub struct LPTIM2SMEN_W<'a> { w: &'a mut W, } impl<'a> LPTIM2SMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); self.w } } #[doc = "Reader of field `LPTIM1SMEN`"] pub type LPTIM1SMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `LPTIM1SMEN`"] pub struct LPTIM1SMEN_W<'a> { w: &'a mut W, } impl<'a> LPTIM1SMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); self.w } } impl R { #[doc = "Bit 0 - TIM2 timer clock enable during Sleep mode"] #[inline(always)] pub fn tim2smen(&self) -> TIM2SMEN_R { TIM2SMEN_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - TIM3 timer clock enable during Sleep mode"] #[inline(always)] pub fn tim3smen(&self) -> TIM3SMEN_R { TIM3SMEN_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 10 - RTC APB clock enable during Sleep mode"] #[inline(always)] pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R { RTCAPBSMEN_R::new(((self.bits >> 10) & 0x01) != 0) } #[doc = "Bit 11 - WWDG clock enable during Sleep mode"] #[inline(always)] pub fn wwdgsmen(&self) -> WWDGSMEN_R { WWDGSMEN_R::new(((self.bits >> 11) & 0x01) != 0) } #[doc = "Bit 14 - SPI2 clock enable during Sleep mode"] #[inline(always)] pub fn spi2smen(&self) -> SPI2SMEN_R { SPI2SMEN_R::new(((self.bits >> 14) & 0x01) != 0) } #[doc = "Bit 17 - USART2 clock enable during Sleep mode"] #[inline(always)] pub fn usart2smen(&self) -> USART2SMEN_R { USART2SMEN_R::new(((self.bits >> 17) & 0x01) != 0) } #[doc = "Bit 20 - LPUART1 clock enable during Sleep mode"] #[inline(always)] pub fn lpuart1smen(&self) -> LPUART1SMEN_R { LPUART1SMEN_R::new(((self.bits >> 20) & 0x01) != 0) } #[doc = "Bit 21 - I2C1 clock enable during Sleep mode"] #[inline(always)] pub fn i2c1smen(&self) -> I2C1SMEN_R { I2C1SMEN_R::new(((self.bits >> 21) & 0x01) != 0) } #[doc = "Bit 22 - I2C2 clock enable during Sleep mode"] #[inline(always)] pub fn i2c2smen(&self) -> I2C2SMEN_R { I2C2SMEN_R::new(((self.bits >> 22) & 0x01) != 0) } #[doc = "Bit 27 - Debug support clock enable during Sleep mode"] #[inline(always)] pub fn dbgsmen(&self) -> DBGSMEN_R { DBGSMEN_R::new(((self.bits >> 27) & 0x01) != 0) } #[doc = "Bit 28 - Power interface clock enable during Sleep mode"] #[inline(always)] pub fn pwrsmen(&self) -> PWRSMEN_R { PWRSMEN_R::new(((self.bits >> 28) & 0x01) != 0) } #[doc = "Bit 30 - Low Power Timer 2 clock enable during Sleep mode"] #[inline(always)] pub fn lptim2smen(&self) -> LPTIM2SMEN_R { LPTIM2SMEN_R::new(((self.bits >> 30) & 0x01) != 0) } #[doc = "Bit 31 - Low Power Timer 1 clock enable during Sleep mode"] #[inline(always)] pub fn lptim1smen(&self) -> LPTIM1SMEN_R { LPTIM1SMEN_R::new(((self.bits >> 31) & 0x01) != 0) } } impl W { #[doc = "Bit 0 - TIM2 timer clock enable during Sleep mode"] #[inline(always)] pub fn tim2smen(&mut self) -> TIM2SMEN_W { TIM2SMEN_W { w: self } } #[doc = "Bit 1 - TIM3 timer clock enable during Sleep mode"] #[inline(always)] pub fn tim3smen(&mut self) -> TIM3SMEN_W { TIM3SMEN_W { w: self } } #[doc = "Bit 10 - RTC APB clock enable during Sleep mode"] #[inline(always)] pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W { RTCAPBSMEN_W { w: self } } #[doc = "Bit 11 - WWDG clock enable during Sleep mode"] #[inline(always)] pub fn wwdgsmen(&mut self) -> WWDGSMEN_W { WWDGSMEN_W { w: self } } #[doc = "Bit 14 - SPI2 clock enable during Sleep mode"] #[inline(always)] pub fn spi2smen(&mut self) -> SPI2SMEN_W { SPI2SMEN_W { w: self } } #[doc = "Bit 17 - USART2 clock enable during Sleep mode"] #[inline(always)] pub fn usart2smen(&mut self) -> USART2SMEN_W { USART2SMEN_W { w: self } } #[doc = "Bit 20 - LPUART1 clock enable during Sleep mode"] #[inline(always)] pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W { LPUART1SMEN_W { w: self } } #[doc = "Bit 21 - I2C1 clock enable during Sleep mode"] #[inline(always)] pub fn i2c1smen(&mut self) -> I2C1SMEN_W { I2C1SMEN_W { w: self } } #[doc = "Bit 22 - I2C2 clock enable during Sleep mode"] #[inline(always)] pub fn i2c2smen(&mut self) -> I2C2SMEN_W { I2C2SMEN_W { w: self } } #[doc = "Bit 27 - Debug support clock enable during Sleep mode"] #[inline(always)] pub fn dbgsmen(&mut self) -> DBGSMEN_W { DBGSMEN_W { w: self } } #[doc = "Bit 28 - Power interface clock enable during Sleep mode"] #[inline(always)] pub fn pwrsmen(&mut self) -> PWRSMEN_W { PWRSMEN_W { w: self } } #[doc = "Bit 30 - Low Power Timer 2 clock enable during Sleep mode"] #[inline(always)] pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W { LPTIM2SMEN_W { w: self } } #[doc = "Bit 31 - Low Power Timer 1 clock enable during Sleep mode"] #[inline(always)] pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W { LPTIM1SMEN_W { w: self } } }