Trait Target

pub trait Target {
    type Instance: Deref<Target = RegisterBlock>;
    type Stream: Stream;
    type Channel: Channel;

    const INTERRUPT: Interrupt;
}

Implemented for all peripheral APIs that support DMA transfers

This is an internal trait. End users neither need to implement it, nor use it directly.

Required Associated Constants

const INTERRUPT: Interrupt

Required Associated Types

type Instance: Deref<Target = RegisterBlock>

type Stream: Stream

type Channel: Channel

Dyn Compatibility

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety", so this trait is not object safe.

Implementors

impl Target for RxTx<QUADSPI>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM7

type Instance = DMA2

type Stream = Stream7<DMA2>

type Channel = Channel3

impl Target for stm32f7xx_hal::serial::Rx<UART4>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM2

type Instance = DMA1

type Stream = Stream2<DMA1>

type Channel = Channel4

impl Target for stm32f7xx_hal::serial::Rx<UART5>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM0

type Instance = DMA1

type Stream = Stream0<DMA1>

type Channel = Channel4

impl Target for stm32f7xx_hal::serial::Rx<UART7>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM3

type Instance = DMA1

type Stream = Stream3<DMA1>

type Channel = Channel5

impl Target for stm32f7xx_hal::serial::Rx<UART8>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM6

type Instance = DMA1

type Stream = Stream6<DMA1>

type Channel = Channel5

impl Target for stm32f7xx_hal::serial::Rx<USART1>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM2

type Instance = DMA2

type Stream = Stream2<DMA2>

type Channel = Channel4

impl Target for stm32f7xx_hal::serial::Rx<USART2>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM5

type Instance = DMA1

type Stream = Stream5<DMA1>

type Channel = Channel4

impl Target for stm32f7xx_hal::serial::Rx<USART3>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM1

type Instance = DMA1

type Stream = Stream1<DMA1>

type Channel = Channel4

impl Target for stm32f7xx_hal::serial::Rx<USART6>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM1

type Instance = DMA2

type Stream = Stream1<DMA2>

type Channel = Channel5

impl Target for stm32f7xx_hal::serial::Tx<UART4>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM4

type Instance = DMA1

type Stream = Stream4<DMA1>

type Channel = Channel4

impl Target for stm32f7xx_hal::serial::Tx<UART5>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM7

type Instance = DMA1

type Stream = Stream7<DMA1>

type Channel = Channel4

impl Target for stm32f7xx_hal::serial::Tx<UART7>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM1

type Instance = DMA1

type Stream = Stream1<DMA1>

type Channel = Channel5

impl Target for stm32f7xx_hal::serial::Tx<UART8>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM0

type Instance = DMA1

type Stream = Stream0<DMA1>

type Channel = Channel5

impl Target for stm32f7xx_hal::serial::Tx<USART1>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM7

type Instance = DMA2

type Stream = Stream7<DMA2>

type Channel = Channel4

impl Target for stm32f7xx_hal::serial::Tx<USART2>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM6

type Instance = DMA1

type Stream = Stream6<DMA1>

type Channel = Channel4

impl Target for stm32f7xx_hal::serial::Tx<USART3>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM3

type Instance = DMA1

type Stream = Stream3<DMA1>

type Channel = Channel4

impl Target for stm32f7xx_hal::serial::Tx<USART6>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM6

type Instance = DMA2

type Stream = Stream6<DMA2>

type Channel = Channel5

impl Target for stm32f7xx_hal::spi::Rx<SPI1>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM0

type Instance = DMA2

type Stream = Stream0<DMA2>

type Channel = Channel3

impl Target for stm32f7xx_hal::spi::Rx<SPI2>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM3

type Instance = DMA1

type Stream = Stream3<DMA1>

type Channel = Channel0

impl Target for stm32f7xx_hal::spi::Rx<SPI3>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM0

type Instance = DMA1

type Stream = Stream0<DMA1>

type Channel = Channel0

impl Target for stm32f7xx_hal::spi::Rx<SPI4>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM0

type Instance = DMA2

type Stream = Stream0<DMA2>

type Channel = Channel4

impl Target for stm32f7xx_hal::spi::Rx<SPI5>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM3

type Instance = DMA2

type Stream = Stream3<DMA2>

type Channel = Channel2

impl Target for stm32f7xx_hal::spi::Rx<SPI6>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM6

type Instance = DMA2

type Stream = Stream6<DMA2>

type Channel = Channel1

impl Target for stm32f7xx_hal::spi::Tx<SPI1>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM3

type Instance = DMA2

type Stream = Stream3<DMA2>

type Channel = Channel3

impl Target for stm32f7xx_hal::spi::Tx<SPI2>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM4

type Instance = DMA1

type Stream = Stream4<DMA1>

type Channel = Channel0

impl Target for stm32f7xx_hal::spi::Tx<SPI3>

const INTERRUPT: Interrupt = Interrupt::DMA1_STREAM5

type Instance = DMA1

type Stream = Stream5<DMA1>

type Channel = Channel0

impl Target for stm32f7xx_hal::spi::Tx<SPI4>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM1

type Instance = DMA2

type Stream = Stream1<DMA2>

type Channel = Channel4

impl Target for stm32f7xx_hal::spi::Tx<SPI5>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM4

type Instance = DMA2

type Stream = Stream4<DMA2>

type Channel = Channel2

impl Target for stm32f7xx_hal::spi::Tx<SPI6>

const INTERRUPT: Interrupt = Interrupt::DMA2_STREAM5

type Instance = DMA2

type Stream = Stream5<DMA2>

type Channel = Channel1