[−][src]Struct stm32f7::stm32f7x9::dfsdm::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub dfsdm_chcfg0r1: DFSDM_CHCFG0R1,
    pub dfsdm_chcfg1r1: DFSDM_CHCFG1R1,
    pub dfsdm_chcfg2r1: DFSDM_CHCFG2R1,
    pub dfsdm_chcfg3r1: DFSDM_CHCFG3R1,
    pub dfsdm_chcfg4r1: DFSDM_CHCFG4R1,
    pub dfsdm_chcfg5r1: DFSDM_CHCFG5R1,
    pub dfsdm_chcfg6r1: DFSDM_CHCFG6R1,
    pub dfsdm_chcfg7r1: DFSDM_CHCFG7R1,
    pub dfsdm_chcfg0r2: DFSDM_CHCFG0R2,
    pub dfsdm_chcfg1r2: DFSDM_CHCFG1R2,
    pub dfsdm_chcfg2r2: DFSDM_CHCFG2R2,
    pub dfsdm_chcfg3r2: DFSDM_CHCFG3R2,
    pub dfsdm_chcfg4r2: DFSDM_CHCFG4R2,
    pub dfsdm_chcfg5r2: DFSDM_CHCFG5R2,
    pub dfsdm_chcfg6r2: DFSDM_CHCFG6R2,
    pub dfsdm_chcfg7r2: DFSDM_CHCFG7R2,
    pub dfsdm_awscd0r: DFSDM_AWSCD0R,
    pub dfsdm_awscd1r: DFSDM_AWSCD1R,
    pub dfsdm_awscd2r: DFSDM_AWSCD2R,
    pub dfsdm_awscd3r: DFSDM_AWSCD3R,
    pub dfsdm_awscd4r: DFSDM_AWSCD4R,
    pub dfsdm_awscd5r: DFSDM_AWSCD5R,
    pub dfsdm_awscd6r: DFSDM_AWSCD6R,
    pub dfsdm_awscd7r: DFSDM_AWSCD7R,
    pub dfsdm_chwdat0r: DFSDM_CHWDAT0R,
    pub dfsdm_chwdat1r: DFSDM_CHWDAT1R,
    pub dfsdm_chwdat2r: DFSDM_CHWDAT2R,
    pub dfsdm_chwdat3r: DFSDM_CHWDAT3R,
    pub dfsdm_chwdat4r: DFSDM_CHWDAT4R,
    pub dfsdm_chwdat5r: DFSDM_CHWDAT5R,
    pub dfsdm_chwdat6r: DFSDM_CHWDAT6R,
    pub dfsdm_chwdat7r: DFSDM_CHWDAT7R,
    pub dfsdm_chdatin0r: DFSDM_CHDATIN0R,
    pub dfsdm_chdatin1r: DFSDM_CHDATIN1R,
    pub dfsdm_chdatin2r: DFSDM_CHDATIN2R,
    pub dfsdm_chdatin3r: DFSDM_CHDATIN3R,
    pub dfsdm_chdatin4r: DFSDM_CHDATIN4R,
    pub dfsdm_chdatin5r: DFSDM_CHDATIN5R,
    pub dfsdm_chdatin6r: DFSDM_CHDATIN6R,
    pub dfsdm_chdatin7r: DFSDM_CHDATIN7R,
    pub dfsdm0_cr1: DFSDM0_CR1,
    pub dfsdm1_cr1: DFSDM1_CR1,
    pub dfsdm2_cr1: DFSDM2_CR1,
    pub dfsdm3_cr1: DFSDM3_CR1,
    pub dfsdm0_cr2: DFSDM0_CR2,
    pub dfsdm1_cr2: DFSDM1_CR2,
    pub dfsdm2_cr2: DFSDM2_CR2,
    pub dfsdm3_cr2: DFSDM3_CR2,
    pub dfsdm0_isr: DFSDM0_ISR,
    pub dfsdm1_isr: DFSDM1_ISR,
    pub dfsdm2_isr: DFSDM2_ISR,
    pub dfsdm3_isr: DFSDM3_ISR,
    pub dfsdm0_icr: DFSDM0_ICR,
    pub dfsdm1_icr: DFSDM1_ICR,
    pub dfsdm2_icr: DFSDM2_ICR,
    pub dfsdm3_icr: DFSDM3_ICR,
    pub dfsdm0_jchgr: DFSDM0_JCHGR,
    pub dfsdm1_jchgr: DFSDM1_JCHGR,
    pub dfsdm2_jchgr: DFSDM2_JCHGR,
    pub dfsdm3_jchgr: DFSDM3_JCHGR,
    pub dfsdm0_fcr: DFSDM0_FCR,
    pub dfsdm1_fcr: DFSDM1_FCR,
    pub dfsdm2_fcr: DFSDM2_FCR,
    pub dfsdm3_fcr: DFSDM3_FCR,
    pub dfsdm0_jdatar: DFSDM0_JDATAR,
    pub dfsdm1_jdatar: DFSDM1_JDATAR,
    pub dfsdm2_jdatar: DFSDM2_JDATAR,
    pub dfsdm3_jdatar: DFSDM3_JDATAR,
    pub dfsdm0_rdatar: DFSDM0_RDATAR,
    pub dfsdm1_rdatar: DFSDM1_RDATAR,
    pub dfsdm2_rdatar: DFSDM2_RDATAR,
    pub dfsdm3_rdatar: DFSDM3_RDATAR,
    pub dfsdm0_awhtr: DFSDM0_AWHTR,
    pub dfsdm1_awhtr: DFSDM1_AWHTR,
    pub dfsdm2_awhtr: DFSDM2_AWHTR,
    pub dfsdm3_awhtr: DFSDM3_AWHTR,
    pub dfsdm0_awltr: DFSDM0_AWLTR,
    pub dfsdm1_awltr: DFSDM1_AWLTR,
    pub dfsdm2_awltr: DFSDM2_AWLTR,
    pub dfsdm3_awltr: DFSDM3_AWLTR,
    pub dfsdm0_awsr: DFSDM0_AWSR,
    pub dfsdm1_awsr: DFSDM1_AWSR,
    pub dfsdm2_awsr: DFSDM2_AWSR,
    pub dfsdm3_awsr: DFSDM3_AWSR,
    pub dfsdm0_awcfr: DFSDM0_AWCFR,
    pub dfsdm1_awcfr: DFSDM1_AWCFR,
    pub dfsdm2_awcfr: DFSDM2_AWCFR,
    pub dfsdm3_awcfr: DFSDM3_AWCFR,
    pub dfsdm0_exmax: DFSDM0_EXMAX,
    pub dfsdm1_exmax: DFSDM1_EXMAX,
    pub dfsdm2_exmax: DFSDM2_EXMAX,
    pub dfsdm3_exmax: DFSDM3_EXMAX,
    pub dfsdm0_exmin: DFSDM0_EXMIN,
    pub dfsdm1_exmin: DFSDM1_EXMIN,
    pub dfsdm2_exmin: DFSDM2_EXMIN,
    pub dfsdm3_exmin: DFSDM3_EXMIN,
    pub dfsdm0_cnvtimr: DFSDM0_CNVTIMR,
    pub dfsdm1_cnvtimr: DFSDM1_CNVTIMR,
    pub dfsdm2_cnvtimr: DFSDM2_CNVTIMR,
    pub dfsdm3_cnvtimr: DFSDM3_CNVTIMR,
}

Register block

Fields

dfsdm_chcfg0r1: DFSDM_CHCFG0R1

0x00 - DFSDM channel configuration 0 register 1

dfsdm_chcfg1r1: DFSDM_CHCFG1R1

0x04 - DFSDM channel configuration 1 register 1

dfsdm_chcfg2r1: DFSDM_CHCFG2R1

0x08 - DFSDM channel configuration 2 register 1

dfsdm_chcfg3r1: DFSDM_CHCFG3R1

0x0c - DFSDM channel configuration 3 register 1

dfsdm_chcfg4r1: DFSDM_CHCFG4R1

0x10 - DFSDM channel configuration 4 register 1

dfsdm_chcfg5r1: DFSDM_CHCFG5R1

0x14 - DFSDM channel configuration 5 register 1

dfsdm_chcfg6r1: DFSDM_CHCFG6R1

0x18 - DFSDM channel configuration 6 register 1

dfsdm_chcfg7r1: DFSDM_CHCFG7R1

0x1c - DFSDM channel configuration 7 register 1

dfsdm_chcfg0r2: DFSDM_CHCFG0R2

0x20 - DFSDM channel configuration 0 register 2

dfsdm_chcfg1r2: DFSDM_CHCFG1R2

0x24 - DFSDM channel configuration 1 register 2

dfsdm_chcfg2r2: DFSDM_CHCFG2R2

0x28 - DFSDM channel configuration 2 register 2

dfsdm_chcfg3r2: DFSDM_CHCFG3R2

0x2c - DFSDM channel configuration 3 register 2

dfsdm_chcfg4r2: DFSDM_CHCFG4R2

0x30 - DFSDM channel configuration 4 register 2

dfsdm_chcfg5r2: DFSDM_CHCFG5R2

0x34 - DFSDM channel configuration 5 register 2

dfsdm_chcfg6r2: DFSDM_CHCFG6R2

0x38 - DFSDM channel configuration 6 register 2

dfsdm_chcfg7r2: DFSDM_CHCFG7R2

0x3c - DFSDM channel configuration 7 register 2

dfsdm_awscd0r: DFSDM_AWSCD0R

0x40 - DFSDM analog watchdog and short-circuit detector register

dfsdm_awscd1r: DFSDM_AWSCD1R

0x44 - DFSDM analog watchdog and short-circuit detector register

dfsdm_awscd2r: DFSDM_AWSCD2R

0x48 - DFSDM analog watchdog and short-circuit detector register

dfsdm_awscd3r: DFSDM_AWSCD3R

0x4c - DFSDM analog watchdog and short-circuit detector register

dfsdm_awscd4r: DFSDM_AWSCD4R

0x50 - DFSDM analog watchdog and short-circuit detector register

dfsdm_awscd5r: DFSDM_AWSCD5R

0x54 - DFSDM analog watchdog and short-circuit detector register

dfsdm_awscd6r: DFSDM_AWSCD6R

0x58 - DFSDM analog watchdog and short-circuit detector register

dfsdm_awscd7r: DFSDM_AWSCD7R

0x5c - DFSDM analog watchdog and short-circuit detector register

dfsdm_chwdat0r: DFSDM_CHWDAT0R

0x60 - DFSDM channel watchdog filter data register

dfsdm_chwdat1r: DFSDM_CHWDAT1R

0x64 - DFSDM channel watchdog filter data register

dfsdm_chwdat2r: DFSDM_CHWDAT2R

0x68 - DFSDM channel watchdog filter data register

dfsdm_chwdat3r: DFSDM_CHWDAT3R

0x6c - DFSDM channel watchdog filter data register

dfsdm_chwdat4r: DFSDM_CHWDAT4R

0x70 - DFSDM channel watchdog filter data register

dfsdm_chwdat5r: DFSDM_CHWDAT5R

0x74 - DFSDM channel watchdog filter data register

dfsdm_chwdat6r: DFSDM_CHWDAT6R

0x78 - DFSDM channel watchdog filter data register

dfsdm_chwdat7r: DFSDM_CHWDAT7R

0x7c - DFSDM channel watchdog filter data register

dfsdm_chdatin0r: DFSDM_CHDATIN0R

0x80 - DFSDM channel data input register

dfsdm_chdatin1r: DFSDM_CHDATIN1R

0x84 - DFSDM channel data input register

dfsdm_chdatin2r: DFSDM_CHDATIN2R

0x88 - DFSDM channel data input register

dfsdm_chdatin3r: DFSDM_CHDATIN3R

0x8c - DFSDM channel data input register

dfsdm_chdatin4r: DFSDM_CHDATIN4R

0x90 - DFSDM channel data input register

dfsdm_chdatin5r: DFSDM_CHDATIN5R

0x94 - DFSDM channel data input register

dfsdm_chdatin6r: DFSDM_CHDATIN6R

0x98 - DFSDM channel data input register

dfsdm_chdatin7r: DFSDM_CHDATIN7R

0x9c - DFSDM channel data input register

dfsdm0_cr1: DFSDM0_CR1

0xa0 - DFSDM control register 1

dfsdm1_cr1: DFSDM1_CR1

0xa4 - DFSDM control register 1

dfsdm2_cr1: DFSDM2_CR1

0xa8 - DFSDM control register 1

dfsdm3_cr1: DFSDM3_CR1

0xac - DFSDM control register 1

dfsdm0_cr2: DFSDM0_CR2

0xb0 - DFSDM control register 2

dfsdm1_cr2: DFSDM1_CR2

0xb4 - DFSDM control register 2

dfsdm2_cr2: DFSDM2_CR2

0xb8 - DFSDM control register 2

dfsdm3_cr2: DFSDM3_CR2

0xbc - DFSDM control register 2

dfsdm0_isr: DFSDM0_ISR

0xc0 - DFSDM interrupt and status register

dfsdm1_isr: DFSDM1_ISR

0xc4 - DFSDM interrupt and status register

dfsdm2_isr: DFSDM2_ISR

0xc8 - DFSDM interrupt and status register

dfsdm3_isr: DFSDM3_ISR

0xcc - DFSDM interrupt and status register

dfsdm0_icr: DFSDM0_ICR

0xd0 - DFSDM interrupt flag clear register

dfsdm1_icr: DFSDM1_ICR

0xd4 - DFSDM interrupt flag clear register

dfsdm2_icr: DFSDM2_ICR

0xd8 - DFSDM interrupt flag clear register

dfsdm3_icr: DFSDM3_ICR

0xdc - DFSDM interrupt flag clear register

dfsdm0_jchgr: DFSDM0_JCHGR

0xe0 - DFSDM injected channel group selection register

dfsdm1_jchgr: DFSDM1_JCHGR

0xe4 - DFSDM injected channel group selection register

dfsdm2_jchgr: DFSDM2_JCHGR

0xe8 - DFSDM injected channel group selection register

dfsdm3_jchgr: DFSDM3_JCHGR

0xec - DFSDM injected channel group selection register

dfsdm0_fcr: DFSDM0_FCR

0xf0 - DFSDM filter control register

dfsdm1_fcr: DFSDM1_FCR

0xf4 - DFSDM filter control register

dfsdm2_fcr: DFSDM2_FCR

0xf8 - DFSDM filter control register

dfsdm3_fcr: DFSDM3_FCR

0xfc - DFSDM filter control register

dfsdm0_jdatar: DFSDM0_JDATAR

0x100 - DFSDM data register for injected group

dfsdm1_jdatar: DFSDM1_JDATAR

0x104 - DFSDM data register for injected group

dfsdm2_jdatar: DFSDM2_JDATAR

0x108 - DFSDM data register for injected group

dfsdm3_jdatar: DFSDM3_JDATAR

0x10c - DFSDM data register for injected group

dfsdm0_rdatar: DFSDM0_RDATAR

0x110 - DFSDM data register for the regular channel

dfsdm1_rdatar: DFSDM1_RDATAR

0x114 - DFSDM data register for the regular channel

dfsdm2_rdatar: DFSDM2_RDATAR

0x118 - DFSDM data register for the regular channel

dfsdm3_rdatar: DFSDM3_RDATAR

0x11c - DFSDM data register for the regular channel

dfsdm0_awhtr: DFSDM0_AWHTR

0x120 - DFSDM analog watchdog high threshold register

dfsdm1_awhtr: DFSDM1_AWHTR

0x124 - DFSDM analog watchdog high threshold register

dfsdm2_awhtr: DFSDM2_AWHTR

0x128 - DFSDM analog watchdog high threshold register

dfsdm3_awhtr: DFSDM3_AWHTR

0x12c - DFSDM analog watchdog high threshold register

dfsdm0_awltr: DFSDM0_AWLTR

0x130 - DFSDM analog watchdog low threshold register

dfsdm1_awltr: DFSDM1_AWLTR

0x134 - DFSDM analog watchdog low threshold register

dfsdm2_awltr: DFSDM2_AWLTR

0x138 - DFSDM analog watchdog low threshold register

dfsdm3_awltr: DFSDM3_AWLTR

0x13c - DFSDM analog watchdog low threshold register

dfsdm0_awsr: DFSDM0_AWSR

0x140 - DFSDM analog watchdog status register

dfsdm1_awsr: DFSDM1_AWSR

0x144 - DFSDM analog watchdog status register

dfsdm2_awsr: DFSDM2_AWSR

0x148 - DFSDM analog watchdog status register

dfsdm3_awsr: DFSDM3_AWSR

0x14c - DFSDM analog watchdog status register

dfsdm0_awcfr: DFSDM0_AWCFR

0x150 - DFSDM analog watchdog clear flag register

dfsdm1_awcfr: DFSDM1_AWCFR

0x154 - DFSDM analog watchdog clear flag register

dfsdm2_awcfr: DFSDM2_AWCFR

0x158 - DFSDM analog watchdog clear flag register

dfsdm3_awcfr: DFSDM3_AWCFR

0x15c - DFSDM analog watchdog clear flag register

dfsdm0_exmax: DFSDM0_EXMAX

0x160 - DFSDM Extremes detector maximum register

dfsdm1_exmax: DFSDM1_EXMAX

0x164 - DFSDM Extremes detector maximum register

dfsdm2_exmax: DFSDM2_EXMAX

0x168 - DFSDM Extremes detector maximum register

dfsdm3_exmax: DFSDM3_EXMAX

0x16c - DFSDM Extremes detector maximum register

dfsdm0_exmin: DFSDM0_EXMIN

0x170 - DFSDM Extremes detector minimum register

dfsdm1_exmin: DFSDM1_EXMIN

0x174 - DFSDM Extremes detector minimum register

dfsdm2_exmin: DFSDM2_EXMIN

0x178 - DFSDM Extremes detector minimum register

dfsdm3_exmin: DFSDM3_EXMIN

0x17c - DFSDM Extremes detector minimum register

dfsdm0_cnvtimr: DFSDM0_CNVTIMR

0x180 - DFSDM conversion timer register

dfsdm1_cnvtimr: DFSDM1_CNVTIMR

0x184 - DFSDM conversion timer register

dfsdm2_cnvtimr: DFSDM2_CNVTIMR

0x188 - DFSDM conversion timer register

dfsdm3_cnvtimr: DFSDM3_CNVTIMR

0x18c - DFSDM conversion timer register

Auto Trait Implementations

`impl Unpin for RegisterBlock`

`impl Send for RegisterBlock`

`impl !Sync for RegisterBlock`

Blanket Implementations

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

`fn try_into(self) -> Result<U, >::Error>`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Same<T> for T`

`type Output = T`

Should always be Self

[−][src]Struct stm32f7::stm32f7x9::dfsdm::RegisterBlock

Fields

Auto Trait Implementations

`impl Unpin for RegisterBlock`

`impl Send for RegisterBlock`

`impl !Sync for RegisterBlock`

Blanket Implementations

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> TryFrom<U> for T where U: Into<T>,` [src]

`type Error = Infallible`

`fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>`[src]

`impl<T, U> Into<U> for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T, U> TryInto<U> for T where U: TryFrom<T>,` [src]

`type Error = <U as TryFrom<T>>::Error`

`fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Same<T> for T`

`type Output = T`

[−][src]Struct stm32f7::stm32f7x9::dfsdm::RegisterBlock

Fields

Auto Trait Implementations

impl Unpin for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

Blanket Implementations

impl<T> From<T> for T[src]

fn from(t: T) -> T[src]

impl<T, U> TryFrom<U> for T where U: Into<T>, [src]

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>[src]

impl<T, U> Into<U> for T where U: From<T>, [src]

fn into(self) -> U[src]

impl<T, U> TryInto<U> for T where U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>[src]

impl<T> Borrow<T> for T where T: ?Sized, [src]

fn borrow(&self) -> &T[src]

impl<T> BorrowMut<T> for T where T: ?Sized, [src]

fn borrow_mut(&mut self) -> &mut T[src]

impl<T> Any for T where T: 'static + ?Sized, [src]

fn type_id(&self) -> TypeId[src]

impl<T> Same<T> for T

type Output = T

`impl Unpin for RegisterBlock`

`impl Send for RegisterBlock`

`impl !Sync for RegisterBlock`

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> TryFrom<U> for T where U: Into<T>,` [src]

`type Error = Infallible`

`fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>`[src]

`impl<T, U> Into<U> for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T, U> TryInto<U> for T where U: TryFrom<T>,` [src]

`type Error = <U as TryFrom<T>>::Error`

`fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Same<T> for T`

`type Output = T`