1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265

#[doc = r"Value read from the register"]
pub struct R {
    bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
    bits: u32,
}
impl super::PLLSAICFGR {
    #[doc = r"Modifies the contents of the register"]
    #[inline(always)]
    pub fn modify<F>(&self, f: F)
    where
        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
    {
        let bits = self.register.get();
        self.register.set(f(&R { bits }, &mut W { bits }).bits);
    }
    #[doc = r"Reads the contents of the register"]
    #[inline(always)]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
    #[doc = r"Writes to the register"]
    #[inline(always)]
    pub fn write<F>(&self, f: F)
    where
        F: FnOnce(&mut W) -> &mut W,
    {
        self.register.set(
            f(&mut W {
                bits: Self::reset_value(),
            })
            .bits,
        );
    }
    #[doc = r"Reset value of the register"]
    #[inline(always)]
    pub const fn reset_value() -> u32 {
        0x2000_3000
    }
    #[doc = r"Writes the reset value to the register"]
    #[inline(always)]
    pub fn reset(&self) {
        self.register.set(Self::reset_value())
    }
}
#[doc = r"Value of the field"]
pub struct PLLSAINR {
    bits: u16,
}
impl PLLSAINR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u16 {
        self.bits
    }
}
#[doc = r"Proxy"]
pub struct _PLLSAINW<'a> {
    w: &'a mut W,
}
impl<'a> _PLLSAINW<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u16) -> &'a mut W {
        self.w.bits &= !(0x01ff << 6);
        self.w.bits |= ((value as u32) & 0x01ff) << 6;
        self.w
    }
}
#[doc = "Possible values of the field `PLLSAIP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLLSAIPR {
    #[doc = "PLL*P=2"]
    DIV2,
    #[doc = "PLL*P=4"]
    DIV4,
    #[doc = "PLL*P=6"]
    DIV6,
    #[doc = "PLL*P=8"]
    DIV8,
}
impl PLLSAIPR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        match *self {
            PLLSAIPR::DIV2 => 0,
            PLLSAIPR::DIV4 => 0x01,
            PLLSAIPR::DIV6 => 0x02,
            PLLSAIPR::DIV8 => 0x03,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _from(value: u8) -> PLLSAIPR {
        match value {
            0 => PLLSAIPR::DIV2,
            1 => PLLSAIPR::DIV4,
            2 => PLLSAIPR::DIV6,
            3 => PLLSAIPR::DIV8,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `DIV2`"]
    #[inline(always)]
    pub fn is_div2(&self) -> bool {
        *self == PLLSAIPR::DIV2
    }
    #[doc = "Checks if the value of the field is `DIV4`"]
    #[inline(always)]
    pub fn is_div4(&self) -> bool {
        *self == PLLSAIPR::DIV4
    }
    #[doc = "Checks if the value of the field is `DIV6`"]
    #[inline(always)]
    pub fn is_div6(&self) -> bool {
        *self == PLLSAIPR::DIV6
    }
    #[doc = "Checks if the value of the field is `DIV8`"]
    #[inline(always)]
    pub fn is_div8(&self) -> bool {
        *self == PLLSAIPR::DIV8
    }
}
#[doc = "Values that can be written to the field `PLLSAIP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLLSAIPW {
    #[doc = "PLL*P=2"]
    DIV2,
    #[doc = "PLL*P=4"]
    DIV4,
    #[doc = "PLL*P=6"]
    DIV6,
    #[doc = "PLL*P=8"]
    DIV8,
}
impl PLLSAIPW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _bits(&self) -> u8 {
        match *self {
            PLLSAIPW::DIV2 => 0,
            PLLSAIPW::DIV4 => 1,
            PLLSAIPW::DIV6 => 2,
            PLLSAIPW::DIV8 => 3,
        }
    }
}
#[doc = r"Proxy"]
pub struct _PLLSAIPW<'a> {
    w: &'a mut W,
}
impl<'a> _PLLSAIPW<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: PLLSAIPW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "PLL*P=2"]
    #[inline(always)]
    pub fn div2(self) -> &'a mut W {
        self.variant(PLLSAIPW::DIV2)
    }
    #[doc = "PLL*P=4"]
    #[inline(always)]
    pub fn div4(self) -> &'a mut W {
        self.variant(PLLSAIPW::DIV4)
    }
    #[doc = "PLL*P=6"]
    #[inline(always)]
    pub fn div6(self) -> &'a mut W {
        self.variant(PLLSAIPW::DIV6)
    }
    #[doc = "PLL*P=8"]
    #[inline(always)]
    pub fn div8(self) -> &'a mut W {
        self.variant(PLLSAIPW::DIV8)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x03 << 16);
        self.w.bits |= ((value as u32) & 0x03) << 16;
        self.w
    }
}
#[doc = r"Value of the field"]
pub struct PLLSAIQR {
    bits: u8,
}
impl PLLSAIQR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r"Proxy"]
pub struct _PLLSAIQW<'a> {
    w: &'a mut W,
}
impl<'a> _PLLSAIQW<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x0f << 24);
        self.w.bits |= ((value as u32) & 0x0f) << 24;
        self.w
    }
}
impl R {
    #[doc = r"Value of the register as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 6:14 - PLLSAI division factor for VCO"]
    #[inline(always)]
    pub fn pllsain(&self) -> PLLSAINR {
        let bits = ((self.bits >> 6) & 0x01ff) as u16;
        PLLSAINR { bits }
    }
    #[doc = "Bits 16:17 - PLLSAI division factor for 48MHz clock"]
    #[inline(always)]
    pub fn pllsaip(&self) -> PLLSAIPR {
        PLLSAIPR::_from(((self.bits >> 16) & 0x03) as u8)
    }
    #[doc = "Bits 24:27 - PLLSAI division factor for SAI clock"]
    #[inline(always)]
    pub fn pllsaiq(&self) -> PLLSAIQR {
        let bits = ((self.bits >> 24) & 0x0f) as u8;
        PLLSAIQR { bits }
    }
}
impl W {
    #[doc = r"Writes raw bits to the register"]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
    #[doc = "Bits 6:14 - PLLSAI division factor for VCO"]
    #[inline(always)]
    pub fn pllsain(&mut self) -> _PLLSAINW {
        _PLLSAINW { w: self }
    }
    #[doc = "Bits 16:17 - PLLSAI division factor for 48MHz clock"]
    #[inline(always)]
    pub fn pllsaip(&mut self) -> _PLLSAIPW {
        _PLLSAIPW { w: self }
    }
    #[doc = "Bits 24:27 - PLLSAI division factor for SAI clock"]
    #[inline(always)]
    pub fn pllsaiq(&mut self) -> _PLLSAIQW {
        _PLLSAIQW { w: self }
    }
}