#[doc = r" Value read from the register"]
pub struct R {
    bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
    bits: u32,
}
impl super::DCKCFGR2 {
    #[doc = r" Modifies the contents of the register"]
    #[inline]
    pub fn modify<F>(&self, f: F)
    where
        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
    {
        let bits = self.register.get();
        let r = R { bits: bits };
        let mut w = W { bits: bits };
        f(&r, &mut w);
        self.register.set(w.bits);
    }
    #[doc = r" Reads the contents of the register"]
    #[inline]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
    #[doc = r" Writes to the register"]
    #[inline]
    pub fn write<F>(&self, f: F)
    where
        F: FnOnce(&mut W) -> &mut W,
    {
        let mut w = W::reset_value();
        f(&mut w);
        self.register.set(w.bits);
    }
    #[doc = r" Writes the reset value to the register"]
    #[inline]
    pub fn reset(&self) {
        self.write(|w| w)
    }
}
#[doc = "Possible values of the field `USART1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USART1SELR {
    #[doc = "APB2 clock (PCLK2) is selected as USART clock"]
    APB2,
    #[doc = "System clock is selected as USART clock"]
    SYSCLK,
    #[doc = "HSI clock is selected as USART clock"]
    HSI,
    #[doc = "LSE clock is selected as USART clock"]
    LSE,
}
impl USART1SELR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        match *self {
            USART1SELR::APB2 => 0,
            USART1SELR::SYSCLK => 1,
            USART1SELR::HSI => 2,
            USART1SELR::LSE => 3,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: u8) -> USART1SELR {
        match value {
            0 => USART1SELR::APB2,
            1 => USART1SELR::SYSCLK,
            2 => USART1SELR::HSI,
            3 => USART1SELR::LSE,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `APB2`"]
    #[inline]
    pub fn is_apb2(&self) -> bool {
        *self == USART1SELR::APB2
    }
    #[doc = "Checks if the value of the field is `SYSCLK`"]
    #[inline]
    pub fn is_sysclk(&self) -> bool {
        *self == USART1SELR::SYSCLK
    }
    #[doc = "Checks if the value of the field is `HSI`"]
    #[inline]
    pub fn is_hsi(&self) -> bool {
        *self == USART1SELR::HSI
    }
    #[doc = "Checks if the value of the field is `LSE`"]
    #[inline]
    pub fn is_lse(&self) -> bool {
        *self == USART1SELR::LSE
    }
}
#[doc = "Possible values of the field `USART2SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USART2SELR {
    #[doc = "APB1 clock (PCLK1) is selected as USART clock"]
    APB1,
    #[doc = "System clock is selected as USART clock"]
    SYSCLK,
    #[doc = "HSI clock is selected as USART clock"]
    HSI,
    #[doc = "LSE clock is selected as USART clock"]
    LSE,
}
impl USART2SELR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        match *self {
            USART2SELR::APB1 => 0,
            USART2SELR::SYSCLK => 1,
            USART2SELR::HSI => 2,
            USART2SELR::LSE => 3,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: u8) -> USART2SELR {
        match value {
            0 => USART2SELR::APB1,
            1 => USART2SELR::SYSCLK,
            2 => USART2SELR::HSI,
            3 => USART2SELR::LSE,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `APB1`"]
    #[inline]
    pub fn is_apb1(&self) -> bool {
        *self == USART2SELR::APB1
    }
    #[doc = "Checks if the value of the field is `SYSCLK`"]
    #[inline]
    pub fn is_sysclk(&self) -> bool {
        *self == USART2SELR::SYSCLK
    }
    #[doc = "Checks if the value of the field is `HSI`"]
    #[inline]
    pub fn is_hsi(&self) -> bool {
        *self == USART2SELR::HSI
    }
    #[doc = "Checks if the value of the field is `LSE`"]
    #[inline]
    pub fn is_lse(&self) -> bool {
        *self == USART2SELR::LSE
    }
}
#[doc = "Possible values of the field `USART3SEL`"]
pub type USART3SELR = USART2SELR;
#[doc = "Possible values of the field `UART4SEL`"]
pub type UART4SELR = USART2SELR;
#[doc = "Possible values of the field `UART5SEL`"]
pub type UART5SELR = USART2SELR;
#[doc = "Possible values of the field `USART6SEL`"]
pub type USART6SELR = USART1SELR;
#[doc = "Possible values of the field `UART7SEL`"]
pub type UART7SELR = USART2SELR;
#[doc = "Possible values of the field `UART8SEL`"]
pub type UART8SELR = USART2SELR;
#[doc = "Possible values of the field `I2C1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C1SELR {
    #[doc = "APB1 clock (PCLK1) is selected as I2C clock"]
    APB1,
    #[doc = "System clock is selected as I2C clock"]
    SYSCLK,
    #[doc = "HSI clock is selected as I2C clock"]
    HSI,
    #[doc = r" Reserved"]
    _Reserved(u8),
}
impl I2C1SELR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        match *self {
            I2C1SELR::APB1 => 0,
            I2C1SELR::SYSCLK => 1,
            I2C1SELR::HSI => 2,
            I2C1SELR::_Reserved(bits) => bits,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: u8) -> I2C1SELR {
        match value {
            0 => I2C1SELR::APB1,
            1 => I2C1SELR::SYSCLK,
            2 => I2C1SELR::HSI,
            i => I2C1SELR::_Reserved(i),
        }
    }
    #[doc = "Checks if the value of the field is `APB1`"]
    #[inline]
    pub fn is_apb1(&self) -> bool {
        *self == I2C1SELR::APB1
    }
    #[doc = "Checks if the value of the field is `SYSCLK`"]
    #[inline]
    pub fn is_sysclk(&self) -> bool {
        *self == I2C1SELR::SYSCLK
    }
    #[doc = "Checks if the value of the field is `HSI`"]
    #[inline]
    pub fn is_hsi(&self) -> bool {
        *self == I2C1SELR::HSI
    }
}
#[doc = "Possible values of the field `I2C2SEL`"]
pub type I2C2SELR = I2C1SELR;
#[doc = "Possible values of the field `I2C3SEL`"]
pub type I2C3SELR = I2C1SELR;
#[doc = "Possible values of the field `I2C4SEL`"]
pub type I2C4SELR = I2C1SELR;
#[doc = "Possible values of the field `LPTIM1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPTIM1SELR {
    #[doc = "APB1 clock (PCLK1) selected as LPTILM1 clock"]
    APB1,
    #[doc = "LSI clock is selected as LPTILM1 clock"]
    LSI,
    #[doc = "HSI clock is selected as LPTILM1 clock"]
    HSI,
    #[doc = "LSE clock is selected as LPTILM1 clock"]
    LSE,
}
impl LPTIM1SELR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        match *self {
            LPTIM1SELR::APB1 => 0,
            LPTIM1SELR::LSI => 1,
            LPTIM1SELR::HSI => 2,
            LPTIM1SELR::LSE => 3,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: u8) -> LPTIM1SELR {
        match value {
            0 => LPTIM1SELR::APB1,
            1 => LPTIM1SELR::LSI,
            2 => LPTIM1SELR::HSI,
            3 => LPTIM1SELR::LSE,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `APB1`"]
    #[inline]
    pub fn is_apb1(&self) -> bool {
        *self == LPTIM1SELR::APB1
    }
    #[doc = "Checks if the value of the field is `LSI`"]
    #[inline]
    pub fn is_lsi(&self) -> bool {
        *self == LPTIM1SELR::LSI
    }
    #[doc = "Checks if the value of the field is `HSI`"]
    #[inline]
    pub fn is_hsi(&self) -> bool {
        *self == LPTIM1SELR::HSI
    }
    #[doc = "Checks if the value of the field is `LSE`"]
    #[inline]
    pub fn is_lse(&self) -> bool {
        *self == LPTIM1SELR::LSE
    }
}
#[doc = "Possible values of the field `CECSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CECSELR {
    #[doc = "LSE clock is selected as HDMI-CEC clock"]
    LSE,
    #[doc = "HSI divided by 488 clock is selected as HDMI-CEC clock"]
    HSI_DIV488,
}
impl CECSELR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            CECSELR::LSE => false,
            CECSELR::HSI_DIV488 => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> CECSELR {
        match value {
            false => CECSELR::LSE,
            true => CECSELR::HSI_DIV488,
        }
    }
    #[doc = "Checks if the value of the field is `LSE`"]
    #[inline]
    pub fn is_lse(&self) -> bool {
        *self == CECSELR::LSE
    }
    #[doc = "Checks if the value of the field is `HSI_DIV488`"]
    #[inline]
    pub fn is_hsi_div488(&self) -> bool {
        *self == CECSELR::HSI_DIV488
    }
}
#[doc = "Possible values of the field `CK48MSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CK48MSELR {
    #[doc = "48MHz clock from PLL is selected"]
    PLL,
    #[doc = "48MHz clock from PLLSAI is selected"]
    PLLSAI,
}
impl CK48MSELR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            CK48MSELR::PLL => false,
            CK48MSELR::PLLSAI => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> CK48MSELR {
        match value {
            false => CK48MSELR::PLL,
            true => CK48MSELR::PLLSAI,
        }
    }
    #[doc = "Checks if the value of the field is `PLL`"]
    #[inline]
    pub fn is_pll(&self) -> bool {
        *self == CK48MSELR::PLL
    }
    #[doc = "Checks if the value of the field is `PLLSAI`"]
    #[inline]
    pub fn is_pllsai(&self) -> bool {
        *self == CK48MSELR::PLLSAI
    }
}
#[doc = "Possible values of the field `SDMMC1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SDMMC1SELR {
    #[doc = "48 MHz clock is selected as SD clock"]
    CK48M,
    #[doc = "System clock is selected as SD clock"]
    SYSCLK,
}
impl SDMMC1SELR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            SDMMC1SELR::CK48M => false,
            SDMMC1SELR::SYSCLK => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> SDMMC1SELR {
        match value {
            false => SDMMC1SELR::CK48M,
            true => SDMMC1SELR::SYSCLK,
        }
    }
    #[doc = "Checks if the value of the field is `CK48M`"]
    #[inline]
    pub fn is_ck48m(&self) -> bool {
        *self == SDMMC1SELR::CK48M
    }
    #[doc = "Checks if the value of the field is `SYSCLK`"]
    #[inline]
    pub fn is_sysclk(&self) -> bool {
        *self == SDMMC1SELR::SYSCLK
    }
}
#[doc = "Possible values of the field `SDMMC2SEL`"]
pub type SDMMC2SELR = SDMMC1SELR;
#[doc = "Possible values of the field `DSISEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DSISELR {
    #[doc = "DSI-PHY used as DSI byte lane clock source (usual case)"]
    DSI_PHY,
    #[doc = "PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)"]
    PLLR,
}
impl DSISELR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            DSISELR::DSI_PHY => false,
            DSISELR::PLLR => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> DSISELR {
        match value {
            false => DSISELR::DSI_PHY,
            true => DSISELR::PLLR,
        }
    }
    #[doc = "Checks if the value of the field is `DSI_PHY`"]
    #[inline]
    pub fn is_dsi_phy(&self) -> bool {
        *self == DSISELR::DSI_PHY
    }
    #[doc = "Checks if the value of the field is `PLLR`"]
    #[inline]
    pub fn is_pllr(&self) -> bool {
        *self == DSISELR::PLLR
    }
}
#[doc = "Values that can be written to the field `USART1SEL`"]
pub enum USART1SELW {
    #[doc = "APB2 clock (PCLK2) is selected as USART clock"]
    APB2,
    #[doc = "System clock is selected as USART clock"]
    SYSCLK,
    #[doc = "HSI clock is selected as USART clock"]
    HSI,
    #[doc = "LSE clock is selected as USART clock"]
    LSE,
}
impl USART1SELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> u8 {
        match *self {
            USART1SELW::APB2 => 0,
            USART1SELW::SYSCLK => 1,
            USART1SELW::HSI => 2,
            USART1SELW::LSE => 3,
        }
    }
}
#[doc = r" Proxy"]
pub struct _USART1SELW<'a> {
    w: &'a mut W,
}
impl<'a> _USART1SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: USART1SELW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "APB2 clock (PCLK2) is selected as USART clock"]
    #[inline]
    pub fn apb2(self) -> &'a mut W {
        self.variant(USART1SELW::APB2)
    }
    #[doc = "System clock is selected as USART clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART1SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as USART clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART1SELW::HSI)
    }
    #[doc = "LSE clock is selected as USART clock"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART1SELW::LSE)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 0;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `USART2SEL`"]
pub enum USART2SELW {
    #[doc = "APB1 clock (PCLK1) is selected as USART clock"]
    APB1,
    #[doc = "System clock is selected as USART clock"]
    SYSCLK,
    #[doc = "HSI clock is selected as USART clock"]
    HSI,
    #[doc = "LSE clock is selected as USART clock"]
    LSE,
}
impl USART2SELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> u8 {
        match *self {
            USART2SELW::APB1 => 0,
            USART2SELW::SYSCLK => 1,
            USART2SELW::HSI => 2,
            USART2SELW::LSE => 3,
        }
    }
}
#[doc = r" Proxy"]
pub struct _USART2SELW<'a> {
    w: &'a mut W,
}
impl<'a> _USART2SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: USART2SELW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "APB1 clock (PCLK1) is selected as USART clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(USART2SELW::APB1)
    }
    #[doc = "System clock is selected as USART clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART2SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as USART clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART2SELW::HSI)
    }
    #[doc = "LSE clock is selected as USART clock"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART2SELW::LSE)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 2;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `USART3SEL`"]
pub type USART3SELW = USART2SELW;
#[doc = r" Proxy"]
pub struct _USART3SELW<'a> {
    w: &'a mut W,
}
impl<'a> _USART3SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: USART3SELW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "APB1 clock (PCLK1) is selected as USART clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(USART2SELW::APB1)
    }
    #[doc = "System clock is selected as USART clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART2SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as USART clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART2SELW::HSI)
    }
    #[doc = "LSE clock is selected as USART clock"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART2SELW::LSE)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 4;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `UART4SEL`"]
pub type UART4SELW = USART2SELW;
#[doc = r" Proxy"]
pub struct _UART4SELW<'a> {
    w: &'a mut W,
}
impl<'a> _UART4SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: UART4SELW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "APB1 clock (PCLK1) is selected as USART clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(USART2SELW::APB1)
    }
    #[doc = "System clock is selected as USART clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART2SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as USART clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART2SELW::HSI)
    }
    #[doc = "LSE clock is selected as USART clock"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART2SELW::LSE)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 6;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `UART5SEL`"]
pub type UART5SELW = USART2SELW;
#[doc = r" Proxy"]
pub struct _UART5SELW<'a> {
    w: &'a mut W,
}
impl<'a> _UART5SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: UART5SELW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "APB1 clock (PCLK1) is selected as USART clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(USART2SELW::APB1)
    }
    #[doc = "System clock is selected as USART clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART2SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as USART clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART2SELW::HSI)
    }
    #[doc = "LSE clock is selected as USART clock"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART2SELW::LSE)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 8;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `USART6SEL`"]
pub type USART6SELW = USART1SELW;
#[doc = r" Proxy"]
pub struct _USART6SELW<'a> {
    w: &'a mut W,
}
impl<'a> _USART6SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: USART6SELW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "APB2 clock (PCLK2) is selected as USART clock"]
    #[inline]
    pub fn apb2(self) -> &'a mut W {
        self.variant(USART1SELW::APB2)
    }
    #[doc = "System clock is selected as USART clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART1SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as USART clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART1SELW::HSI)
    }
    #[doc = "LSE clock is selected as USART clock"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART1SELW::LSE)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 10;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `UART7SEL`"]
pub type UART7SELW = USART2SELW;
#[doc = r" Proxy"]
pub struct _UART7SELW<'a> {
    w: &'a mut W,
}
impl<'a> _UART7SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: UART7SELW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "APB1 clock (PCLK1) is selected as USART clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(USART2SELW::APB1)
    }
    #[doc = "System clock is selected as USART clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART2SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as USART clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART2SELW::HSI)
    }
    #[doc = "LSE clock is selected as USART clock"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART2SELW::LSE)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 12;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `UART8SEL`"]
pub type UART8SELW = USART2SELW;
#[doc = r" Proxy"]
pub struct _UART8SELW<'a> {
    w: &'a mut W,
}
impl<'a> _UART8SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: UART8SELW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "APB1 clock (PCLK1) is selected as USART clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(USART2SELW::APB1)
    }
    #[doc = "System clock is selected as USART clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(USART2SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as USART clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(USART2SELW::HSI)
    }
    #[doc = "LSE clock is selected as USART clock"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(USART2SELW::LSE)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 14;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `I2C1SEL`"]
pub enum I2C1SELW {
    #[doc = "APB1 clock (PCLK1) is selected as I2C clock"]
    APB1,
    #[doc = "System clock is selected as I2C clock"]
    SYSCLK,
    #[doc = "HSI clock is selected as I2C clock"]
    HSI,
}
impl I2C1SELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> u8 {
        match *self {
            I2C1SELW::APB1 => 0,
            I2C1SELW::SYSCLK => 1,
            I2C1SELW::HSI => 2,
        }
    }
}
#[doc = r" Proxy"]
pub struct _I2C1SELW<'a> {
    w: &'a mut W,
}
impl<'a> _I2C1SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: I2C1SELW) -> &'a mut W {
        unsafe { self.bits(variant._bits()) }
    }
    #[doc = "APB1 clock (PCLK1) is selected as I2C clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(I2C1SELW::APB1)
    }
    #[doc = "System clock is selected as I2C clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(I2C1SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as I2C clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(I2C1SELW::HSI)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 16;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `I2C2SEL`"]
pub type I2C2SELW = I2C1SELW;
#[doc = r" Proxy"]
pub struct _I2C2SELW<'a> {
    w: &'a mut W,
}
impl<'a> _I2C2SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: I2C2SELW) -> &'a mut W {
        unsafe { self.bits(variant._bits()) }
    }
    #[doc = "APB1 clock (PCLK1) is selected as I2C clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(I2C1SELW::APB1)
    }
    #[doc = "System clock is selected as I2C clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(I2C1SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as I2C clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(I2C1SELW::HSI)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 18;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `I2C3SEL`"]
pub type I2C3SELW = I2C1SELW;
#[doc = r" Proxy"]
pub struct _I2C3SELW<'a> {
    w: &'a mut W,
}
impl<'a> _I2C3SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: I2C3SELW) -> &'a mut W {
        unsafe { self.bits(variant._bits()) }
    }
    #[doc = "APB1 clock (PCLK1) is selected as I2C clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(I2C1SELW::APB1)
    }
    #[doc = "System clock is selected as I2C clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(I2C1SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as I2C clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(I2C1SELW::HSI)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 20;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `I2C4SEL`"]
pub type I2C4SELW = I2C1SELW;
#[doc = r" Proxy"]
pub struct _I2C4SELW<'a> {
    w: &'a mut W,
}
impl<'a> _I2C4SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: I2C4SELW) -> &'a mut W {
        unsafe { self.bits(variant._bits()) }
    }
    #[doc = "APB1 clock (PCLK1) is selected as I2C clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(I2C1SELW::APB1)
    }
    #[doc = "System clock is selected as I2C clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(I2C1SELW::SYSCLK)
    }
    #[doc = "HSI clock is selected as I2C clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(I2C1SELW::HSI)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 22;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `LPTIM1SEL`"]
pub enum LPTIM1SELW {
    #[doc = "APB1 clock (PCLK1) selected as LPTILM1 clock"]
    APB1,
    #[doc = "LSI clock is selected as LPTILM1 clock"]
    LSI,
    #[doc = "HSI clock is selected as LPTILM1 clock"]
    HSI,
    #[doc = "LSE clock is selected as LPTILM1 clock"]
    LSE,
}
impl LPTIM1SELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> u8 {
        match *self {
            LPTIM1SELW::APB1 => 0,
            LPTIM1SELW::LSI => 1,
            LPTIM1SELW::HSI => 2,
            LPTIM1SELW::LSE => 3,
        }
    }
}
#[doc = r" Proxy"]
pub struct _LPTIM1SELW<'a> {
    w: &'a mut W,
}
impl<'a> _LPTIM1SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: LPTIM1SELW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "APB1 clock (PCLK1) selected as LPTILM1 clock"]
    #[inline]
    pub fn apb1(self) -> &'a mut W {
        self.variant(LPTIM1SELW::APB1)
    }
    #[doc = "LSI clock is selected as LPTILM1 clock"]
    #[inline]
    pub fn lsi(self) -> &'a mut W {
        self.variant(LPTIM1SELW::LSI)
    }
    #[doc = "HSI clock is selected as LPTILM1 clock"]
    #[inline]
    pub fn hsi(self) -> &'a mut W {
        self.variant(LPTIM1SELW::HSI)
    }
    #[doc = "LSE clock is selected as LPTILM1 clock"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(LPTIM1SELW::LSE)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 3;
        const OFFSET: u8 = 24;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `CECSEL`"]
pub enum CECSELW {
    #[doc = "LSE clock is selected as HDMI-CEC clock"]
    LSE,
    #[doc = "HSI divided by 488 clock is selected as HDMI-CEC clock"]
    HSI_DIV488,
}
impl CECSELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            CECSELW::LSE => false,
            CECSELW::HSI_DIV488 => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _CECSELW<'a> {
    w: &'a mut W,
}
impl<'a> _CECSELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: CECSELW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "LSE clock is selected as HDMI-CEC clock"]
    #[inline]
    pub fn lse(self) -> &'a mut W {
        self.variant(CECSELW::LSE)
    }
    #[doc = "HSI divided by 488 clock is selected as HDMI-CEC clock"]
    #[inline]
    pub fn hsi_div488(self) -> &'a mut W {
        self.variant(CECSELW::HSI_DIV488)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 26;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `CK48MSEL`"]
pub enum CK48MSELW {
    #[doc = "48MHz clock from PLL is selected"]
    PLL,
    #[doc = "48MHz clock from PLLSAI is selected"]
    PLLSAI,
}
impl CK48MSELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            CK48MSELW::PLL => false,
            CK48MSELW::PLLSAI => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _CK48MSELW<'a> {
    w: &'a mut W,
}
impl<'a> _CK48MSELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: CK48MSELW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "48MHz clock from PLL is selected"]
    #[inline]
    pub fn pll(self) -> &'a mut W {
        self.variant(CK48MSELW::PLL)
    }
    #[doc = "48MHz clock from PLLSAI is selected"]
    #[inline]
    pub fn pllsai(self) -> &'a mut W {
        self.variant(CK48MSELW::PLLSAI)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 27;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `SDMMC1SEL`"]
pub enum SDMMC1SELW {
    #[doc = "48 MHz clock is selected as SD clock"]
    CK48M,
    #[doc = "System clock is selected as SD clock"]
    SYSCLK,
}
impl SDMMC1SELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            SDMMC1SELW::CK48M => false,
            SDMMC1SELW::SYSCLK => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _SDMMC1SELW<'a> {
    w: &'a mut W,
}
impl<'a> _SDMMC1SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: SDMMC1SELW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "48 MHz clock is selected as SD clock"]
    #[inline]
    pub fn ck48m(self) -> &'a mut W {
        self.variant(SDMMC1SELW::CK48M)
    }
    #[doc = "System clock is selected as SD clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(SDMMC1SELW::SYSCLK)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 28;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `SDMMC2SEL`"]
pub type SDMMC2SELW = SDMMC1SELW;
#[doc = r" Proxy"]
pub struct _SDMMC2SELW<'a> {
    w: &'a mut W,
}
impl<'a> _SDMMC2SELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: SDMMC2SELW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "48 MHz clock is selected as SD clock"]
    #[inline]
    pub fn ck48m(self) -> &'a mut W {
        self.variant(SDMMC1SELW::CK48M)
    }
    #[doc = "System clock is selected as SD clock"]
    #[inline]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(SDMMC1SELW::SYSCLK)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 29;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `DSISEL`"]
pub enum DSISELW {
    #[doc = "DSI-PHY used as DSI byte lane clock source (usual case)"]
    DSI_PHY,
    #[doc = "PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)"]
    PLLR,
}
impl DSISELW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            DSISELW::DSI_PHY => false,
            DSISELW::PLLR => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _DSISELW<'a> {
    w: &'a mut W,
}
impl<'a> _DSISELW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: DSISELW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "DSI-PHY used as DSI byte lane clock source (usual case)"]
    #[inline]
    pub fn dsi_phy(self) -> &'a mut W {
        self.variant(DSISELW::DSI_PHY)
    }
    #[doc = "PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)"]
    #[inline]
    pub fn pllr(self) -> &'a mut W {
        self.variant(DSISELW::PLLR)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 30;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
impl R {
    #[doc = r" Value of the register as raw bits"]
    #[inline]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 0:1 - USART 1 clock source selection"]
    #[inline]
    pub fn usart1sel(&self) -> USART1SELR {
        USART1SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 0;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 2:3 - USART 2 clock source selection"]
    #[inline]
    pub fn usart2sel(&self) -> USART2SELR {
        USART2SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 2;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 4:5 - USART 3 clock source selection"]
    #[inline]
    pub fn usart3sel(&self) -> USART3SELR {
        USART3SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 4;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 6:7 - UART 4 clock source selection"]
    #[inline]
    pub fn uart4sel(&self) -> UART4SELR {
        UART4SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 6;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 8:9 - UART 5 clock source selection"]
    #[inline]
    pub fn uart5sel(&self) -> UART5SELR {
        UART5SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 8;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 10:11 - USART 6 clock source selection"]
    #[inline]
    pub fn usart6sel(&self) -> USART6SELR {
        USART6SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 10;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 12:13 - UART 7 clock source selection"]
    #[inline]
    pub fn uart7sel(&self) -> UART7SELR {
        UART7SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 12;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 14:15 - UART 8 clock source selection"]
    #[inline]
    pub fn uart8sel(&self) -> UART8SELR {
        UART8SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 14;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 16:17 - I2C1 clock source selection"]
    #[inline]
    pub fn i2c1sel(&self) -> I2C1SELR {
        I2C1SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 16;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 18:19 - I2C2 clock source selection"]
    #[inline]
    pub fn i2c2sel(&self) -> I2C2SELR {
        I2C2SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 18;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 20:21 - I2C3 clock source selection"]
    #[inline]
    pub fn i2c3sel(&self) -> I2C3SELR {
        I2C3SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 20;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 22:23 - I2C4 clock source selection"]
    #[inline]
    pub fn i2c4sel(&self) -> I2C4SELR {
        I2C4SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 22;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bits 24:25 - Low power timer 1 clock source selection"]
    #[inline]
    pub fn lptim1sel(&self) -> LPTIM1SELR {
        LPTIM1SELR::_from({
            const MASK: u8 = 3;
            const OFFSET: u8 = 24;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        })
    }
    #[doc = "Bit 26 - HDMI-CEC clock source selection"]
    #[inline]
    pub fn cecsel(&self) -> CECSELR {
        CECSELR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 26;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 27 - 48MHz clock source selection"]
    #[inline]
    pub fn ck48msel(&self) -> CK48MSELR {
        CK48MSELR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 27;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 28 - SDMMC1 clock source selection"]
    #[inline]
    pub fn sdmmc1sel(&self) -> SDMMC1SELR {
        SDMMC1SELR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 28;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 29 - SDMMC2 clock source selection"]
    #[inline]
    pub fn sdmmc2sel(&self) -> SDMMC2SELR {
        SDMMC2SELR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 29;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bit 30 - DSI clock source selection"]
    #[inline]
    pub fn dsisel(&self) -> DSISELR {
        DSISELR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 30;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
}
impl W {
    #[doc = r" Reset value of the register"]
    #[inline]
    pub fn reset_value() -> W {
        W { bits: 0 }
    }
    #[doc = r" Writes raw bits to the register"]
    #[inline]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
    #[doc = "Bits 0:1 - USART 1 clock source selection"]
    #[inline]
    pub fn usart1sel(&mut self) -> _USART1SELW {
        _USART1SELW { w: self }
    }
    #[doc = "Bits 2:3 - USART 2 clock source selection"]
    #[inline]
    pub fn usart2sel(&mut self) -> _USART2SELW {
        _USART2SELW { w: self }
    }
    #[doc = "Bits 4:5 - USART 3 clock source selection"]
    #[inline]
    pub fn usart3sel(&mut self) -> _USART3SELW {
        _USART3SELW { w: self }
    }
    #[doc = "Bits 6:7 - UART 4 clock source selection"]
    #[inline]
    pub fn uart4sel(&mut self) -> _UART4SELW {
        _UART4SELW { w: self }
    }
    #[doc = "Bits 8:9 - UART 5 clock source selection"]
    #[inline]
    pub fn uart5sel(&mut self) -> _UART5SELW {
        _UART5SELW { w: self }
    }
    #[doc = "Bits 10:11 - USART 6 clock source selection"]
    #[inline]
    pub fn usart6sel(&mut self) -> _USART6SELW {
        _USART6SELW { w: self }
    }
    #[doc = "Bits 12:13 - UART 7 clock source selection"]
    #[inline]
    pub fn uart7sel(&mut self) -> _UART7SELW {
        _UART7SELW { w: self }
    }
    #[doc = "Bits 14:15 - UART 8 clock source selection"]
    #[inline]
    pub fn uart8sel(&mut self) -> _UART8SELW {
        _UART8SELW { w: self }
    }
    #[doc = "Bits 16:17 - I2C1 clock source selection"]
    #[inline]
    pub fn i2c1sel(&mut self) -> _I2C1SELW {
        _I2C1SELW { w: self }
    }
    #[doc = "Bits 18:19 - I2C2 clock source selection"]
    #[inline]
    pub fn i2c2sel(&mut self) -> _I2C2SELW {
        _I2C2SELW { w: self }
    }
    #[doc = "Bits 20:21 - I2C3 clock source selection"]
    #[inline]
    pub fn i2c3sel(&mut self) -> _I2C3SELW {
        _I2C3SELW { w: self }
    }
    #[doc = "Bits 22:23 - I2C4 clock source selection"]
    #[inline]
    pub fn i2c4sel(&mut self) -> _I2C4SELW {
        _I2C4SELW { w: self }
    }
    #[doc = "Bits 24:25 - Low power timer 1 clock source selection"]
    #[inline]
    pub fn lptim1sel(&mut self) -> _LPTIM1SELW {
        _LPTIM1SELW { w: self }
    }
    #[doc = "Bit 26 - HDMI-CEC clock source selection"]
    #[inline]
    pub fn cecsel(&mut self) -> _CECSELW {
        _CECSELW { w: self }
    }
    #[doc = "Bit 27 - 48MHz clock source selection"]
    #[inline]
    pub fn ck48msel(&mut self) -> _CK48MSELW {
        _CK48MSELW { w: self }
    }
    #[doc = "Bit 28 - SDMMC1 clock source selection"]
    #[inline]
    pub fn sdmmc1sel(&mut self) -> _SDMMC1SELW {
        _SDMMC1SELW { w: self }
    }
    #[doc = "Bit 29 - SDMMC2 clock source selection"]
    #[inline]
    pub fn sdmmc2sel(&mut self) -> _SDMMC2SELW {
        _SDMMC2SELW { w: self }
    }
    #[doc = "Bit 30 - DSI clock source selection"]
    #[inline]
    pub fn dsisel(&mut self) -> _DSISELW {
        _DSISELW { w: self }
    }
}