stm32f7/stm32f779/rcc/
ahb2lpenr.rs

1///Register `AHB2LPENR` reader
2pub type R = crate::R<AHB2LPENRrs>;
3///Register `AHB2LPENR` writer
4pub type W = crate::W<AHB2LPENRrs>;
5/**Camera interface enable during Sleep mode
6
7Value on reset: 1*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum DCMILPEN {
11    ///0: Selected module is disabled during Sleep mode
12    DisabledInSleep = 0,
13    ///1: Selected module is enabled during Sleep mode
14    EnabledInSleep = 1,
15}
16impl From<DCMILPEN> for bool {
17    #[inline(always)]
18    fn from(variant: DCMILPEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `DCMILPEN` reader - Camera interface enable during Sleep mode
23pub type DCMILPEN_R = crate::BitReader<DCMILPEN>;
24impl DCMILPEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> DCMILPEN {
28        match self.bits {
29            false => DCMILPEN::DisabledInSleep,
30            true => DCMILPEN::EnabledInSleep,
31        }
32    }
33    ///Selected module is disabled during Sleep mode
34    #[inline(always)]
35    pub fn is_disabled_in_sleep(&self) -> bool {
36        *self == DCMILPEN::DisabledInSleep
37    }
38    ///Selected module is enabled during Sleep mode
39    #[inline(always)]
40    pub fn is_enabled_in_sleep(&self) -> bool {
41        *self == DCMILPEN::EnabledInSleep
42    }
43}
44///Field `DCMILPEN` writer - Camera interface enable during Sleep mode
45pub type DCMILPEN_W<'a, REG> = crate::BitWriter<'a, REG, DCMILPEN>;
46impl<'a, REG> DCMILPEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Selected module is disabled during Sleep mode
51    #[inline(always)]
52    pub fn disabled_in_sleep(self) -> &'a mut crate::W<REG> {
53        self.variant(DCMILPEN::DisabledInSleep)
54    }
55    ///Selected module is enabled during Sleep mode
56    #[inline(always)]
57    pub fn enabled_in_sleep(self) -> &'a mut crate::W<REG> {
58        self.variant(DCMILPEN::EnabledInSleep)
59    }
60}
61///Field `JPEGLPEN` reader - JPEG module enabled during Sleep mode
62pub use DCMILPEN_R as JPEGLPEN_R;
63///Field `CRYPLPEN` reader - Cryptography modules clock enable during Sleep mode
64pub use DCMILPEN_R as CRYPLPEN_R;
65///Field `HASHLPEN` reader - Hash modules clock enable during Sleep mode
66pub use DCMILPEN_R as HASHLPEN_R;
67///Field `RNGLPEN` reader - Random number generator clock enable during Sleep mode
68pub use DCMILPEN_R as RNGLPEN_R;
69///Field `OTGFSLPEN` reader - USB OTG FS clock enable during Sleep mode
70pub use DCMILPEN_R as OTGFSLPEN_R;
71///Field `JPEGLPEN` writer - JPEG module enabled during Sleep mode
72pub use DCMILPEN_W as JPEGLPEN_W;
73///Field `CRYPLPEN` writer - Cryptography modules clock enable during Sleep mode
74pub use DCMILPEN_W as CRYPLPEN_W;
75///Field `HASHLPEN` writer - Hash modules clock enable during Sleep mode
76pub use DCMILPEN_W as HASHLPEN_W;
77///Field `RNGLPEN` writer - Random number generator clock enable during Sleep mode
78pub use DCMILPEN_W as RNGLPEN_W;
79///Field `OTGFSLPEN` writer - USB OTG FS clock enable during Sleep mode
80pub use DCMILPEN_W as OTGFSLPEN_W;
81impl R {
82    ///Bit 0 - Camera interface enable during Sleep mode
83    #[inline(always)]
84    pub fn dcmilpen(&self) -> DCMILPEN_R {
85        DCMILPEN_R::new((self.bits & 1) != 0)
86    }
87    ///Bit 1 - JPEG module enabled during Sleep mode
88    #[inline(always)]
89    pub fn jpeglpen(&self) -> JPEGLPEN_R {
90        JPEGLPEN_R::new(((self.bits >> 1) & 1) != 0)
91    }
92    ///Bit 4 - Cryptography modules clock enable during Sleep mode
93    #[inline(always)]
94    pub fn cryplpen(&self) -> CRYPLPEN_R {
95        CRYPLPEN_R::new(((self.bits >> 4) & 1) != 0)
96    }
97    ///Bit 5 - Hash modules clock enable during Sleep mode
98    #[inline(always)]
99    pub fn hashlpen(&self) -> HASHLPEN_R {
100        HASHLPEN_R::new(((self.bits >> 5) & 1) != 0)
101    }
102    ///Bit 6 - Random number generator clock enable during Sleep mode
103    #[inline(always)]
104    pub fn rnglpen(&self) -> RNGLPEN_R {
105        RNGLPEN_R::new(((self.bits >> 6) & 1) != 0)
106    }
107    ///Bit 7 - USB OTG FS clock enable during Sleep mode
108    #[inline(always)]
109    pub fn otgfslpen(&self) -> OTGFSLPEN_R {
110        OTGFSLPEN_R::new(((self.bits >> 7) & 1) != 0)
111    }
112}
113impl core::fmt::Debug for R {
114    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
115        f.debug_struct("AHB2LPENR")
116            .field("dcmilpen", &self.dcmilpen())
117            .field("otgfslpen", &self.otgfslpen())
118            .field("rnglpen", &self.rnglpen())
119            .field("hashlpen", &self.hashlpen())
120            .field("cryplpen", &self.cryplpen())
121            .field("jpeglpen", &self.jpeglpen())
122            .finish()
123    }
124}
125impl W {
126    ///Bit 0 - Camera interface enable during Sleep mode
127    #[inline(always)]
128    pub fn dcmilpen(&mut self) -> DCMILPEN_W<AHB2LPENRrs> {
129        DCMILPEN_W::new(self, 0)
130    }
131    ///Bit 1 - JPEG module enabled during Sleep mode
132    #[inline(always)]
133    pub fn jpeglpen(&mut self) -> JPEGLPEN_W<AHB2LPENRrs> {
134        JPEGLPEN_W::new(self, 1)
135    }
136    ///Bit 4 - Cryptography modules clock enable during Sleep mode
137    #[inline(always)]
138    pub fn cryplpen(&mut self) -> CRYPLPEN_W<AHB2LPENRrs> {
139        CRYPLPEN_W::new(self, 4)
140    }
141    ///Bit 5 - Hash modules clock enable during Sleep mode
142    #[inline(always)]
143    pub fn hashlpen(&mut self) -> HASHLPEN_W<AHB2LPENRrs> {
144        HASHLPEN_W::new(self, 5)
145    }
146    ///Bit 6 - Random number generator clock enable during Sleep mode
147    #[inline(always)]
148    pub fn rnglpen(&mut self) -> RNGLPEN_W<AHB2LPENRrs> {
149        RNGLPEN_W::new(self, 6)
150    }
151    ///Bit 7 - USB OTG FS clock enable during Sleep mode
152    #[inline(always)]
153    pub fn otgfslpen(&mut self) -> OTGFSLPEN_W<AHB2LPENRrs> {
154        OTGFSLPEN_W::new(self, 7)
155    }
156}
157/**AHB2 peripheral clock enable in low power mode register
158
159You can [`read`](crate::Reg::read) this register and get [`ahb2lpenr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb2lpenr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
160
161See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#RCC:AHB2LPENR)*/
162pub struct AHB2LPENRrs;
163impl crate::RegisterSpec for AHB2LPENRrs {
164    type Ux = u32;
165}
166///`read()` method returns [`ahb2lpenr::R`](R) reader structure
167impl crate::Readable for AHB2LPENRrs {}
168///`write(|w| ..)` method takes [`ahb2lpenr::W`](W) writer structure
169impl crate::Writable for AHB2LPENRrs {
170    type Safety = crate::Unsafe;
171}
172///`reset()` method sets AHB2LPENR to value 0xf1
173impl crate::Resettable for AHB2LPENRrs {
174    const RESET_VALUE: u32 = 0xf1;
175}
stm32f7/stm32f779/rcc/ahb2lpenr.rs

stm32f7/stm32f779/rcc/
ahb2lpenr.rs
