stm32f7 0.15.0

Device support crates for STM32F7 devices
Documentation 
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#[doc = "Register `OTG_FS_GRSTCTL` reader"]
pub struct R(crate::R<OTG_FS_GRSTCTL_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<OTG_FS_GRSTCTL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<OTG_FS_GRSTCTL_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<OTG_FS_GRSTCTL_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `OTG_FS_GRSTCTL` writer"]
pub struct W(crate::W<OTG_FS_GRSTCTL_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<OTG_FS_GRSTCTL_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<OTG_FS_GRSTCTL_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<OTG_FS_GRSTCTL_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `CSRST` reader - Core soft reset"]
pub type CSRST_R = crate::BitReader<bool>;
#[doc = "Field `CSRST` writer - Core soft reset"]
pub type CSRST_W<'a> = crate::BitWriter<'a, u32, OTG_FS_GRSTCTL_SPEC, bool, 0>;
#[doc = "Field `HSRST` reader - HCLK soft reset"]
pub type HSRST_R = crate::BitReader<bool>;
#[doc = "Field `HSRST` writer - HCLK soft reset"]
pub type HSRST_W<'a> = crate::BitWriter<'a, u32, OTG_FS_GRSTCTL_SPEC, bool, 1>;
#[doc = "Field `FCRST` reader - Host frame counter reset"]
pub type FCRST_R = crate::BitReader<bool>;
#[doc = "Field `FCRST` writer - Host frame counter reset"]
pub type FCRST_W<'a> = crate::BitWriter<'a, u32, OTG_FS_GRSTCTL_SPEC, bool, 2>;
#[doc = "Field `RXFFLSH` reader - RxFIFO flush"]
pub type RXFFLSH_R = crate::BitReader<bool>;
#[doc = "Field `RXFFLSH` writer - RxFIFO flush"]
pub type RXFFLSH_W<'a> = crate::BitWriter<'a, u32, OTG_FS_GRSTCTL_SPEC, bool, 4>;
#[doc = "Field `TXFFLSH` reader - TxFIFO flush"]
pub type TXFFLSH_R = crate::BitReader<bool>;
#[doc = "Field `TXFFLSH` writer - TxFIFO flush"]
pub type TXFFLSH_W<'a> = crate::BitWriter<'a, u32, OTG_FS_GRSTCTL_SPEC, bool, 5>;
#[doc = "Field `TXFNUM` reader - TxFIFO number"]
pub type TXFNUM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TXFNUM` writer - TxFIFO number"]
pub type TXFNUM_W<'a> = crate::FieldWriter<'a, u32, OTG_FS_GRSTCTL_SPEC, u8, u8, 5, 6>;
#[doc = "Field `AHBIDL` reader - AHB master idle"]
pub type AHBIDL_R = crate::BitReader<bool>;
impl R {
    #[doc = "Bit 0 - Core soft reset"]
    #[inline(always)]
    pub fn csrst(&self) -> CSRST_R {
        CSRST_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - HCLK soft reset"]
    #[inline(always)]
    pub fn hsrst(&self) -> HSRST_R {
        HSRST_R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Host frame counter reset"]
    #[inline(always)]
    pub fn fcrst(&self) -> FCRST_R {
        FCRST_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 4 - RxFIFO flush"]
    #[inline(always)]
    pub fn rxfflsh(&self) -> RXFFLSH_R {
        RXFFLSH_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - TxFIFO flush"]
    #[inline(always)]
    pub fn txfflsh(&self) -> TXFFLSH_R {
        TXFFLSH_R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bits 6:10 - TxFIFO number"]
    #[inline(always)]
    pub fn txfnum(&self) -> TXFNUM_R {
        TXFNUM_R::new(((self.bits >> 6) & 0x1f) as u8)
    }
    #[doc = "Bit 31 - AHB master idle"]
    #[inline(always)]
    pub fn ahbidl(&self) -> AHBIDL_R {
        AHBIDL_R::new(((self.bits >> 31) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Core soft reset"]
    #[inline(always)]
    pub fn csrst(&mut self) -> CSRST_W {
        CSRST_W::new(self)
    }
    #[doc = "Bit 1 - HCLK soft reset"]
    #[inline(always)]
    pub fn hsrst(&mut self) -> HSRST_W {
        HSRST_W::new(self)
    }
    #[doc = "Bit 2 - Host frame counter reset"]
    #[inline(always)]
    pub fn fcrst(&mut self) -> FCRST_W {
        FCRST_W::new(self)
    }
    #[doc = "Bit 4 - RxFIFO flush"]
    #[inline(always)]
    pub fn rxfflsh(&mut self) -> RXFFLSH_W {
        RXFFLSH_W::new(self)
    }
    #[doc = "Bit 5 - TxFIFO flush"]
    #[inline(always)]
    pub fn txfflsh(&mut self) -> TXFFLSH_W {
        TXFFLSH_W::new(self)
    }
    #[doc = "Bits 6:10 - TxFIFO number"]
    #[inline(always)]
    pub fn txfnum(&mut self) -> TXFNUM_W {
        TXFNUM_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "OTG_FS reset register (OTG_FS_GRSTCTL)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [otg_fs_grstctl](index.html) module"]
pub struct OTG_FS_GRSTCTL_SPEC;
impl crate::RegisterSpec for OTG_FS_GRSTCTL_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [otg_fs_grstctl::R](R) reader structure"]
impl crate::Readable for OTG_FS_GRSTCTL_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [otg_fs_grstctl::W](W) writer structure"]
impl crate::Writable for OTG_FS_GRSTCTL_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets OTG_FS_GRSTCTL to value 0x2000_0000"]
impl crate::Resettable for OTG_FS_GRSTCTL_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0x2000_0000
    }
}