#[doc = "Register `CCMR3_Output` reader"]
pub struct R(crate::R<CCMR3_OUTPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR3_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR3_OUTPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR3_OUTPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR3_Output` writer"]
pub struct W(crate::W<CCMR3_OUTPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR3_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR3_OUTPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR3_OUTPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `OC5FE` reader - Output compare 5 fast enable"]
pub struct OC5FE_R(crate::FieldReader<bool, bool>);
impl OC5FE_R {
pub(crate) fn new(bits: bool) -> Self {
OC5FE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for OC5FE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `OC5FE` writer - Output compare 5 fast enable"]
pub struct OC5FE_W<'a> {
w: &'a mut W,
}
impl<'a> OC5FE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
self.w
}
}
#[doc = "Field `OC5PE` reader - Output compare 5 preload enable"]
pub struct OC5PE_R(crate::FieldReader<bool, bool>);
impl OC5PE_R {
pub(crate) fn new(bits: bool) -> Self {
OC5PE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for OC5PE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `OC5PE` writer - Output compare 5 preload enable"]
pub struct OC5PE_W<'a> {
w: &'a mut W,
}
impl<'a> OC5PE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
self.w
}
}
#[doc = "Output compare 5 mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum OC5M_A {
#[doc = "0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"]
FROZEN = 0,
#[doc = "1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1"]
ACTIVEONMATCH = 1,
#[doc = "2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved"]
INACTIVEONMATCH = 2,
#[doc = "3: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved"]
TOGGLE = 3,
#[doc = "4: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"]
FORCEINACTIVE = 4,
#[doc = "5: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"]
FORCEACTIVE = 5,
#[doc = "6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
PWMMODE1 = 6,
#[doc = "7: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1"]
PWMMODE2 = 7,
}
impl From<OC5M_A> for u8 {
#[inline(always)]
fn from(variant: OC5M_A) -> Self {
variant as _
}
}
#[doc = "Field `OC5M` reader - Output compare 5 mode"]
pub struct OC5M_R(crate::FieldReader<u8, OC5M_A>);
impl OC5M_R {
pub(crate) fn new(bits: u8) -> Self {
OC5M_R(crate::FieldReader::new(bits))
}
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> OC5M_A {
match self.bits {
0 => OC5M_A::FROZEN,
1 => OC5M_A::ACTIVEONMATCH,
2 => OC5M_A::INACTIVEONMATCH,
3 => OC5M_A::TOGGLE,
4 => OC5M_A::FORCEINACTIVE,
5 => OC5M_A::FORCEACTIVE,
6 => OC5M_A::PWMMODE1,
7 => OC5M_A::PWMMODE2,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `FROZEN`"]
#[inline(always)]
pub fn is_frozen(&self) -> bool {
**self == OC5M_A::FROZEN
}
#[doc = "Checks if the value of the field is `ACTIVEONMATCH`"]
#[inline(always)]
pub fn is_active_on_match(&self) -> bool {
**self == OC5M_A::ACTIVEONMATCH
}
#[doc = "Checks if the value of the field is `INACTIVEONMATCH`"]
#[inline(always)]
pub fn is_inactive_on_match(&self) -> bool {
**self == OC5M_A::INACTIVEONMATCH
}
#[doc = "Checks if the value of the field is `TOGGLE`"]
#[inline(always)]
pub fn is_toggle(&self) -> bool {
**self == OC5M_A::TOGGLE
}
#[doc = "Checks if the value of the field is `FORCEINACTIVE`"]
#[inline(always)]
pub fn is_force_inactive(&self) -> bool {
**self == OC5M_A::FORCEINACTIVE
}
#[doc = "Checks if the value of the field is `FORCEACTIVE`"]
#[inline(always)]
pub fn is_force_active(&self) -> bool {
**self == OC5M_A::FORCEACTIVE
}
#[doc = "Checks if the value of the field is `PWMMODE1`"]
#[inline(always)]
pub fn is_pwm_mode1(&self) -> bool {
**self == OC5M_A::PWMMODE1
}
#[doc = "Checks if the value of the field is `PWMMODE2`"]
#[inline(always)]
pub fn is_pwm_mode2(&self) -> bool {
**self == OC5M_A::PWMMODE2
}
}
impl core::ops::Deref for OC5M_R {
type Target = crate::FieldReader<u8, OC5M_A>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `OC5M` writer - Output compare 5 mode"]
pub struct OC5M_W<'a> {
w: &'a mut W,
}
impl<'a> OC5M_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OC5M_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"]
#[inline(always)]
pub fn frozen(self) -> &'a mut W {
self.variant(OC5M_A::FROZEN)
}
#[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1"]
#[inline(always)]
pub fn active_on_match(self) -> &'a mut W {
self.variant(OC5M_A::ACTIVEONMATCH)
}
#[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved"]
#[inline(always)]
pub fn inactive_on_match(self) -> &'a mut W {
self.variant(OC5M_A::INACTIVEONMATCH)
}
#[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved"]
#[inline(always)]
pub fn toggle(self) -> &'a mut W {
self.variant(OC5M_A::TOGGLE)
}
#[doc = "OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"]
#[inline(always)]
pub fn force_inactive(self) -> &'a mut W {
self.variant(OC5M_A::FORCEINACTIVE)
}
#[doc = "OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"]
#[inline(always)]
pub fn force_active(self) -> &'a mut W {
self.variant(OC5M_A::FORCEACTIVE)
}
#[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
#[inline(always)]
pub fn pwm_mode1(self) -> &'a mut W {
self.variant(OC5M_A::PWMMODE1)
}
#[doc = "Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1"]
#[inline(always)]
pub fn pwm_mode2(self) -> &'a mut W {
self.variant(OC5M_A::PWMMODE2)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4);
self.w
}
}
#[doc = "Field `OC5CE` reader - Output compare 5 clear enable"]
pub struct OC5CE_R(crate::FieldReader<bool, bool>);
impl OC5CE_R {
pub(crate) fn new(bits: bool) -> Self {
OC5CE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for OC5CE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `OC5CE` writer - Output compare 5 clear enable"]
pub struct OC5CE_W<'a> {
w: &'a mut W,
}
impl<'a> OC5CE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
self.w
}
}
#[doc = "Field `OC6FE` reader - Output compare 6 fast enable"]
pub struct OC6FE_R(crate::FieldReader<bool, bool>);
impl OC6FE_R {
pub(crate) fn new(bits: bool) -> Self {
OC6FE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for OC6FE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `OC6FE` writer - Output compare 6 fast enable"]
pub struct OC6FE_W<'a> {
w: &'a mut W,
}
impl<'a> OC6FE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
self.w
}
}
#[doc = "Field `OC6PE` reader - Output compare 6 preload enable"]
pub struct OC6PE_R(crate::FieldReader<bool, bool>);
impl OC6PE_R {
pub(crate) fn new(bits: bool) -> Self {
OC6PE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for OC6PE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `OC6PE` writer - Output compare 6 preload enable"]
pub struct OC6PE_W<'a> {
w: &'a mut W,
}
impl<'a> OC6PE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
self.w
}
}
#[doc = "Output compare 6 mode"]
pub type OC6M_A = OC5M_A;
#[doc = "Field `OC6M` reader - Output compare 6 mode"]
pub type OC6M_R = OC5M_R;
#[doc = "Field `OC6M` writer - Output compare 6 mode"]
pub struct OC6M_W<'a> {
w: &'a mut W,
}
impl<'a> OC6M_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OC6M_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"]
#[inline(always)]
pub fn frozen(self) -> &'a mut W {
self.variant(OC6M_A::FROZEN)
}
#[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1"]
#[inline(always)]
pub fn active_on_match(self) -> &'a mut W {
self.variant(OC6M_A::ACTIVEONMATCH)
}
#[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved"]
#[inline(always)]
pub fn inactive_on_match(self) -> &'a mut W {
self.variant(OC6M_A::INACTIVEONMATCH)
}
#[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved"]
#[inline(always)]
pub fn toggle(self) -> &'a mut W {
self.variant(OC6M_A::TOGGLE)
}
#[doc = "OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"]
#[inline(always)]
pub fn force_inactive(self) -> &'a mut W {
self.variant(OC6M_A::FORCEINACTIVE)
}
#[doc = "OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"]
#[inline(always)]
pub fn force_active(self) -> &'a mut W {
self.variant(OC6M_A::FORCEACTIVE)
}
#[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"]
#[inline(always)]
pub fn pwm_mode1(self) -> &'a mut W {
self.variant(OC6M_A::PWMMODE1)
}
#[doc = "Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1"]
#[inline(always)]
pub fn pwm_mode2(self) -> &'a mut W {
self.variant(OC6M_A::PWMMODE2)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12);
self.w
}
}
#[doc = "Field `OC6CE` reader - Output compare 6 clear enable"]
pub struct OC6CE_R(crate::FieldReader<bool, bool>);
impl OC6CE_R {
pub(crate) fn new(bits: bool) -> Self {
OC6CE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for OC6CE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `OC6CE` writer - Output compare 6 clear enable"]
pub struct OC6CE_W<'a> {
w: &'a mut W,
}
impl<'a> OC6CE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
self.w
}
}
#[doc = "Output Compare 5 mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OC5M_3_A {
#[doc = "0: Normal output compare mode (modes 0-7)"]
NORMAL = 0,
#[doc = "1: Extended output compare mode (modes 7-15)"]
EXTENDED = 1,
}
impl From<OC5M_3_A> for bool {
#[inline(always)]
fn from(variant: OC5M_3_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OC5M_3` reader - Output Compare 5 mode"]
pub struct OC5M_3_R(crate::FieldReader<bool, OC5M_3_A>);
impl OC5M_3_R {
pub(crate) fn new(bits: bool) -> Self {
OC5M_3_R(crate::FieldReader::new(bits))
}
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> OC5M_3_A {
match self.bits {
false => OC5M_3_A::NORMAL,
true => OC5M_3_A::EXTENDED,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline(always)]
pub fn is_normal(&self) -> bool {
**self == OC5M_3_A::NORMAL
}
#[doc = "Checks if the value of the field is `EXTENDED`"]
#[inline(always)]
pub fn is_extended(&self) -> bool {
**self == OC5M_3_A::EXTENDED
}
}
impl core::ops::Deref for OC5M_3_R {
type Target = crate::FieldReader<bool, OC5M_3_A>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `OC5M_3` writer - Output Compare 5 mode"]
pub struct OC5M_3_W<'a> {
w: &'a mut W,
}
impl<'a> OC5M_3_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OC5M_3_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "Normal output compare mode (modes 0-7)"]
#[inline(always)]
pub fn normal(self) -> &'a mut W {
self.variant(OC5M_3_A::NORMAL)
}
#[doc = "Extended output compare mode (modes 7-15)"]
#[inline(always)]
pub fn extended(self) -> &'a mut W {
self.variant(OC5M_3_A::EXTENDED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
self.w
}
}
#[doc = "Output Compare 6 mode"]
pub type OC6M_3_A = OC5M_3_A;
#[doc = "Field `OC6M_3` reader - Output Compare 6 mode"]
pub type OC6M_3_R = OC5M_3_R;
#[doc = "Field `OC6M_3` writer - Output Compare 6 mode"]
pub struct OC6M_3_W<'a> {
w: &'a mut W,
}
impl<'a> OC6M_3_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OC6M_3_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "Normal output compare mode (modes 0-7)"]
#[inline(always)]
pub fn normal(self) -> &'a mut W {
self.variant(OC6M_3_A::NORMAL)
}
#[doc = "Extended output compare mode (modes 7-15)"]
#[inline(always)]
pub fn extended(self) -> &'a mut W {
self.variant(OC6M_3_A::EXTENDED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
self.w
}
}
impl R {
#[doc = "Bit 2 - Output compare 5 fast enable"]
#[inline(always)]
pub fn oc5fe(&self) -> OC5FE_R {
OC5FE_R::new(((self.bits >> 2) & 0x01) != 0)
}
#[doc = "Bit 3 - Output compare 5 preload enable"]
#[inline(always)]
pub fn oc5pe(&self) -> OC5PE_R {
OC5PE_R::new(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bits 4:6 - Output compare 5 mode"]
#[inline(always)]
pub fn oc5m(&self) -> OC5M_R {
OC5M_R::new(((self.bits >> 4) & 0x07) as u8)
}
#[doc = "Bit 7 - Output compare 5 clear enable"]
#[inline(always)]
pub fn oc5ce(&self) -> OC5CE_R {
OC5CE_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bit 10 - Output compare 6 fast enable"]
#[inline(always)]
pub fn oc6fe(&self) -> OC6FE_R {
OC6FE_R::new(((self.bits >> 10) & 0x01) != 0)
}
#[doc = "Bit 11 - Output compare 6 preload enable"]
#[inline(always)]
pub fn oc6pe(&self) -> OC6PE_R {
OC6PE_R::new(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bits 12:14 - Output compare 6 mode"]
#[inline(always)]
pub fn oc6m(&self) -> OC6M_R {
OC6M_R::new(((self.bits >> 12) & 0x07) as u8)
}
#[doc = "Bit 15 - Output compare 6 clear enable"]
#[inline(always)]
pub fn oc6ce(&self) -> OC6CE_R {
OC6CE_R::new(((self.bits >> 15) & 0x01) != 0)
}
#[doc = "Bit 16 - Output Compare 5 mode"]
#[inline(always)]
pub fn oc5m_3(&self) -> OC5M_3_R {
OC5M_3_R::new(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bit 24 - Output Compare 6 mode"]
#[inline(always)]
pub fn oc6m_3(&self) -> OC6M_3_R {
OC6M_3_R::new(((self.bits >> 24) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 2 - Output compare 5 fast enable"]
#[inline(always)]
pub fn oc5fe(&mut self) -> OC5FE_W {
OC5FE_W { w: self }
}
#[doc = "Bit 3 - Output compare 5 preload enable"]
#[inline(always)]
pub fn oc5pe(&mut self) -> OC5PE_W {
OC5PE_W { w: self }
}
#[doc = "Bits 4:6 - Output compare 5 mode"]
#[inline(always)]
pub fn oc5m(&mut self) -> OC5M_W {
OC5M_W { w: self }
}
#[doc = "Bit 7 - Output compare 5 clear enable"]
#[inline(always)]
pub fn oc5ce(&mut self) -> OC5CE_W {
OC5CE_W { w: self }
}
#[doc = "Bit 10 - Output compare 6 fast enable"]
#[inline(always)]
pub fn oc6fe(&mut self) -> OC6FE_W {
OC6FE_W { w: self }
}
#[doc = "Bit 11 - Output compare 6 preload enable"]
#[inline(always)]
pub fn oc6pe(&mut self) -> OC6PE_W {
OC6PE_W { w: self }
}
#[doc = "Bits 12:14 - Output compare 6 mode"]
#[inline(always)]
pub fn oc6m(&mut self) -> OC6M_W {
OC6M_W { w: self }
}
#[doc = "Bit 15 - Output compare 6 clear enable"]
#[inline(always)]
pub fn oc6ce(&mut self) -> OC6CE_W {
OC6CE_W { w: self }
}
#[doc = "Bit 16 - Output Compare 5 mode"]
#[inline(always)]
pub fn oc5m_3(&mut self) -> OC5M_3_W {
OC5M_3_W { w: self }
}
#[doc = "Bit 24 - Output Compare 6 mode"]
#[inline(always)]
pub fn oc6m_3(&mut self) -> OC6M_3_W {
OC6M_3_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "capture/compare mode register 3 (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr3_output](index.html) module"]
pub struct CCMR3_OUTPUT_SPEC;
impl crate::RegisterSpec for CCMR3_OUTPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr3_output::R](R) reader structure"]
impl crate::Readable for CCMR3_OUTPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr3_output::W](W) writer structure"]
impl crate::Writable for CCMR3_OUTPUT_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CCMR3_Output to value 0"]
impl crate::Resettable for CCMR3_OUTPUT_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}