[−][src]Struct stm32f7::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Methods

`impl<U, T> R<U, T> where U: Copy,` [src]

`pub fn bits(&self) -> U`[src]

Read raw bits from register/field

`impl<FI> R<bool, FI>`[src]

`pub fn bit(&self) -> bool`[src]

Value of the field as raw bits

`pub fn bit_is_clear(&self) -> bool`[src]

Returns true if the bit is clear (0)

`pub fn bit_is_set(&self) -> bool`[src]

Returns true if the bit is set (1)

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn arpe(&self) -> ARPE_R`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&self) -> CMS_R`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&self) -> DIR_R`[src]

Bit 4 - Direction

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`pub fn uifremap(&self) -> UIFREMAP_R`[src]

Bit 11 - UIF status bit remapping

`impl R<bool, TI1S_A>`[src]

`pub fn variant(&self) -> TI1S_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_xor(&self) -> bool`[src]

Checks if the value of the field is XOR

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> MMS_A`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`pub fn is_update(&self) -> bool`[src]

Checks if the value of the field is UPDATE

`pub fn is_compare_pulse(&self) -> bool`[src]

Checks if the value of the field is COMPAREPULSE

`pub fn is_compare_oc1(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC1

`pub fn is_compare_oc2(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC2

`pub fn is_compare_oc3(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC3

`pub fn is_compare_oc4(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC4

`impl R<bool, CCDS_A>`[src]

`pub fn variant(&self) -> CCDS_A`[src]

Get enumerated values variant

`pub fn is_on_compare(&self) -> bool`[src]

Checks if the value of the field is ONCOMPARE

`pub fn is_on_update(&self) -> bool`[src]

Checks if the value of the field is ONUPDATE

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn ois4(&self) -> OIS4_R`[src]

Bit 14 - Output Idle state 4

`pub fn ois3n(&self) -> OIS3N_R`[src]

Bit 13 - Output Idle state 3

`pub fn ois3(&self) -> OIS3_R`[src]

Bit 12 - Output Idle state 3

`pub fn ois2n(&self) -> OIS2N_R`[src]

Bit 11 - Output Idle state 2

`pub fn ois2(&self) -> OIS2_R`[src]

Bit 10 - Output Idle state 2

`pub fn ois1n(&self) -> OIS1N_R`[src]

Bit 9 - Output Idle state 1

`pub fn ois1(&self) -> OIS1_R`[src]

Bit 8 - Output Idle state 1

`pub fn ti1s(&self) -> TI1S_R`[src]

Bit 7 - TI1 selection

`pub fn mms(&self) -> MMS_R`[src]

Bits 4:6 - Master mode selection

`pub fn ccds(&self) -> CCDS_R`[src]

Bit 3 - Capture/compare DMA selection

`pub fn ccus(&self) -> CCUS_R`[src]

Bit 2 - Capture/compare control update selection

`pub fn ccpc(&self) -> CCPC_R`[src]

Bit 0 - Capture/compare preloaded control

`pub fn mms2(&self) -> MMS2_R`[src]

Bits 20:23 - Master mode selection 2

`pub fn ois6(&self) -> OIS6_R`[src]

Bit 18 - Output Idle state 6 (OC6 output)

`pub fn ois5(&self) -> OIS5_R`[src]

Bit 16 - Output Idle state 5 (OC5 output)

`impl R<bool, ETP_A>`[src]

`pub fn variant(&self) -> ETP_A`[src]

Get enumerated values variant

`pub fn is_not_inverted(&self) -> bool`[src]

Checks if the value of the field is NOTINVERTED

`pub fn is_inverted(&self) -> bool`[src]

Checks if the value of the field is INVERTED

`impl R<bool, ECE_A>`[src]

`pub fn variant(&self) -> ECE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, ETPS_A>`[src]

`pub fn variant(&self) -> ETPS_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u8, ETF_A>`[src]

`pub fn variant(&self) -> ETF_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<bool, MSM_A>`[src]

`pub fn variant(&self) -> MSM_A`[src]

Get enumerated values variant

`pub fn is_no_sync(&self) -> bool`[src]

Checks if the value of the field is NOSYNC

`pub fn is_sync(&self) -> bool`[src]

Checks if the value of the field is SYNC

`impl R<u8, TS_A>`[src]

`pub fn variant(&self) -> Variant<u8, TS_A>`[src]

Get enumerated values variant

`pub fn is_itr0(&self) -> bool`[src]

Checks if the value of the field is ITR0

`pub fn is_itr1(&self) -> bool`[src]

Checks if the value of the field is ITR1

`pub fn is_itr2(&self) -> bool`[src]

Checks if the value of the field is ITR2

`pub fn is_ti1f_ed(&self) -> bool`[src]

Checks if the value of the field is TI1F_ED

`pub fn is_ti1fp1(&self) -> bool`[src]

Checks if the value of the field is TI1FP1

`pub fn is_ti2fp2(&self) -> bool`[src]

Checks if the value of the field is TI2FP2

`pub fn is_etrf(&self) -> bool`[src]

Checks if the value of the field is ETRF

`impl R<u8, SMS_A>`[src]

`pub fn variant(&self) -> SMS_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_encoder_mode_1(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_1

`pub fn is_encoder_mode_2(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_2

`pub fn is_encoder_mode_3(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_3

`pub fn is_reset_mode(&self) -> bool`[src]

Checks if the value of the field is RESET_MODE

`pub fn is_gated_mode(&self) -> bool`[src]

Checks if the value of the field is GATED_MODE

`pub fn is_trigger_mode(&self) -> bool`[src]

Checks if the value of the field is TRIGGER_MODE

`pub fn is_ext_clock_mode(&self) -> bool`[src]

Checks if the value of the field is EXT_CLOCK_MODE

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn sms_3(&self) -> SMS_3_R`[src]

Bit 16 - Slave model selection - bit[3]

`pub fn etp(&self) -> ETP_R`[src]

Bit 15 - External trigger polarity

`pub fn ece(&self) -> ECE_R`[src]

Bit 14 - External clock enable

`pub fn etps(&self) -> ETPS_R`[src]

Bits 12:13 - External trigger prescaler

`pub fn etf(&self) -> ETF_R`[src]

`pub fn cc3de(&self) -> CC3DE_R`[src]

Bit 11 - Capture/Compare 3 DMA request enable

`pub fn cc2de(&self) -> CC2DE_R`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&self) -> CC1DE_R`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&self) -> UDE_R`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&self) -> TIE_R`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&self) -> CC4IE_R`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&self) -> CC3IE_R`[src]

Bit 3 - Capture/Compare 3 interrupt enable

`pub fn cc2ie(&self) -> CC2IE_R`[src]

Bit 2 - Capture/Compare 2 interrupt enable

`pub fn cc1ie(&self) -> CC1IE_R`[src]

`pub fn cc2of(&self) -> CC2OF_R`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn bif(&self) -> BIF_R`[src]

Bit 7 - Break interrupt flag

`pub fn tif(&self) -> TIF_R`[src]

Bit 6 - Trigger interrupt flag

`pub fn comif(&self) -> COMIF_R`[src]

Bit 5 - COM interrupt flag

`pub fn cc4if(&self) -> CC4IF_R`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&self) -> CC3IF_R`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&self) -> CC2IF_R`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`pub fn b2if(&self) -> B2IF_R`[src]

Bit 8 - Break 2 interrupt flag

`impl R<u8, OC2M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC2M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC2PE_A>`[src]

`pub fn variant(&self) -> OC2PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&self) -> OC2CE_R`[src]

Bit 15 - Output Compare 2 clear enable

`pub fn oc2m(&self) -> OC2M_R`[src]

Bits 12:14 - Output Compare 2 mode

`pub fn oc2pe(&self) -> OC2PE_R`[src]

Bit 11 - Output Compare 2 preload enable

`pub fn oc2fe(&self) -> OC2FE_R`[src]

Bit 10 - Output Compare 2 fast enable

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn oc1ce(&self) -> OC1CE_R`[src]

Bit 7 - Output Compare 1 clear enable

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - Output Compare 1 mode

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - Output Compare 1 preload enable

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - Output Compare 1 fast enable

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`pub fn oc2m_3(&self) -> OC2M_3_R`[src]

Bit 24 - Output Compare 2 mode - bit 3

`pub fn oc1m_3(&self) -> OC1M_3_R`[src]

Bit 16 - Output Compare 1 mode - bit 3

`impl R<u8, CC2S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC2S_A>`[src]

Get enumerated values variant

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, IC1F_A>`[src]

`pub fn variant(&self) -> IC1F_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&self) -> IC2F_R`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&self) -> IC2PSC_R`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u8, OC4M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC4M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC4PE_A>`[src]

`pub fn variant(&self) -> OC4PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&self) -> OC4CE_R`[src]

Bit 15 - Output compare 4 clear enable

`pub fn oc4m(&self) -> OC4M_R`[src]

Bits 12:14 - Output compare 4 mode

`pub fn oc4pe(&self) -> OC4PE_R`[src]

Bit 11 - Output compare 4 preload enable

`pub fn oc4fe(&self) -> OC4FE_R`[src]

Bit 10 - Output compare 4 fast enable

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn oc3ce(&self) -> OC3CE_R`[src]

Bit 7 - Output compare 3 clear enable

`pub fn oc3m(&self) -> OC3M_R`[src]

Bits 4:6 - Output compare 3 mode

`pub fn oc3pe(&self) -> OC3PE_R`[src]

Bit 3 - Output compare 3 preload enable

`pub fn oc3fe(&self) -> OC3FE_R`[src]

Bit 2 - Output compare 3 fast enable

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - Capture/Compare 3 selection

`pub fn oc4m_3(&self) -> OC4M_3_R`[src]

Bit 24 - Output Compare 4 mode - bit 3

`pub fn oc3m_3(&self) -> OC3M_3_R`[src]

Bit 16 - Output Compare 3 mode - bit 3

`impl R<u8, CC4S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC4S_A>`[src]

Get enumerated values variant

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&self) -> IC4F_R`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&self) -> IC4PSC_R`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&self) -> IC3F_R`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&self) -> IC3PSC_R`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - Capture/compare 3 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4p(&self) -> CC4P_R`[src]

Bit 13 - Capture/Compare 3 output Polarity

`pub fn cc4e(&self) -> CC4E_R`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&self) -> CC3NP_R`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3ne(&self) -> CC3NE_R`[src]

Bit 10 - Capture/Compare 3 complementary output enable

`pub fn cc3p(&self) -> CC3P_R`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&self) -> CC3E_R`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&self) -> CC2NP_R`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2ne(&self) -> CC2NE_R`[src]

Bit 6 - Capture/Compare 2 complementary output enable

`pub fn cc2p(&self) -> CC2P_R`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&self) -> CC2E_R`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1ne(&self) -> CC1NE_R`[src]

Bit 2 - Capture/Compare 1 complementary output enable

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`pub fn cc6p(&self) -> CC6P_R`[src]

Bit 21 - Capture/Compare 6 output polarity

`pub fn cc6e(&self) -> CC6E_R`[src]

Bit 20 - Capture/Compare 6 output enable

`pub fn cc5p(&self) -> CC5P_R`[src]

Bit 17 - Capture/Compare 5 output polarity

`pub fn cc5e(&self) -> CC5E_R`[src]

Bit 16 - Capture/Compare 5 output enable

`pub fn cc4np(&self) -> CC4NP_R`[src]

Bit 15 - Capture/Compare 4 complementary output polarity

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - counter value

`pub fn uifcpy(&self) -> UIFCPY_R`[src]

Bit 31 - UIF copy

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 1 value

`impl R<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&self) -> DBL_R`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&self) -> DBA_R`[src]

Bits 0:4 - DMA base address

`impl R<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&self) -> DMAB_R`[src]

Bits 0:31 - DMA register for burst accesses

`impl R<u32, Reg<u32, _RCR>>`[src]

`pub fn rep(&self) -> REP_R`[src]

Bits 0:7 - Repetition counter value

`impl R<bool, MOE_A>`[src]

`pub fn variant(&self) -> MOE_A`[src]

Get enumerated values variant

`pub fn is_disabled_idle(&self) -> bool`[src]

Checks if the value of the field is DISABLEDIDLE

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, OSSR_A>`[src]

`pub fn variant(&self) -> OSSR_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_idle_level(&self) -> bool`[src]

Checks if the value of the field is IDLELEVEL

`impl R<bool, OSSI_A>`[src]

`pub fn variant(&self) -> OSSI_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_idle_level(&self) -> bool`[src]

Checks if the value of the field is IDLELEVEL

`impl R<u32, Reg<u32, _BDTR>>`[src]

`pub fn moe(&self) -> MOE_R`[src]

Bit 15 - Main output enable

`pub fn aoe(&self) -> AOE_R`[src]

Bit 14 - Automatic output enable

`pub fn bkp(&self) -> BKP_R`[src]

Bit 13 - Break polarity

`pub fn bke(&self) -> BKE_R`[src]

Bit 12 - Break enable

`pub fn ossr(&self) -> OSSR_R`[src]

Bit 11 - Off-state selection for Run mode

`pub fn ossi(&self) -> OSSI_R`[src]

Bit 10 - Off-state selection for Idle mode

`pub fn lock(&self) -> LOCK_R`[src]

Bits 8:9 - Lock configuration

`pub fn dtg(&self) -> DTG_R`[src]

Bits 0:7 - Dead-time generator setup

`pub fn bk2p(&self) -> BK2P_R`[src]

Bit 25 - Break 2 polarity

`pub fn bk2e(&self) -> BK2E_R`[src]

Bit 24 - Break 2 enable

`pub fn bk2f(&self) -> BK2F_R`[src]

Bits 20:23 - Break 2 filter

`pub fn bkf(&self) -> BKF_R`[src]

Bits 16:19 - Break filter

`impl R<u32, Reg<u32, _CCMR3_OUTPUT>>`[src]

`pub fn oc5fe(&self) -> OC5FE_R`[src]

Bit 2 - Output compare 5 fast enable

`pub fn oc5pe(&self) -> OC5PE_R`[src]

Bit 3 - Output compare 5 preload enable

`pub fn oc5m(&self) -> OC5M_R`[src]

Bits 4:6 - Output compare 5 mode

`pub fn oc5ce(&self) -> OC5CE_R`[src]

Bit 7 - Output compare 5 clear enable

`pub fn oc6fe(&self) -> OC6FE_R`[src]

Bit 10 - Output compare 6 fast enable

`pub fn oc6pe(&self) -> OC6PE_R`[src]

Bit 11 - Output compare 6 preload enable

`pub fn oc6m(&self) -> OC6M_R`[src]

Bits 12:14 - Output compare 6 mode

`pub fn oc6ce(&self) -> OC6CE_R`[src]

Bit 15 - Output compare 6 clear enable

`pub fn oc5m3(&self) -> OC5M3_R`[src]

Bit 16 - Output Compare 5 mode

`pub fn oc6m3(&self) -> OC6M3_R`[src]

Bit 24 - Output Compare 6 mode

`impl R<u32, Reg<u32, _CCR5>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 5 value

`pub fn gc5c1(&self) -> GC5C1_R`[src]

Bit 29 - Group Channel 5 and Channel 1

`pub fn gc5c2(&self) -> GC5C2_R`[src]

Bit 30 - Group Channel 5 and Channel 2

`pub fn gc5c3(&self) -> GC5C3_R`[src]

Bit 31 - Group Channel 5 and Channel 3

Checks if the value of the field is NOEVENT

`pub fn is_event(&self) -> bool`[src]

Checks if the value of the field is EVENT

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn ovr(&self) -> OVR_R`[src]

Bit 5 - Overrun

`pub fn strt(&self) -> STRT_R`[src]

Bit 4 - Regular channel start flag

`pub fn jstrt(&self) -> JSTRT_R`[src]

Bit 3 - Injected channel start flag

`pub fn jeoc(&self) -> JEOC_R`[src]

Bit 2 - Injected channel end of conversion

`pub fn eoc(&self) -> EOC_R`[src]

Bit 1 - Regular channel end of conversion

`pub fn awd(&self) -> AWD_R`[src]

Bit 0 - Analog watchdog flag

`impl R<bool, OVRIE_A>`[src]

`pub fn variant(&self) -> OVRIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, RES_A>`[src]

`pub fn variant(&self) -> RES_A`[src]

Get enumerated values variant

`pub fn is_twelve_bit(&self) -> bool`[src]

`pub fn jawden(&self) -> JAWDEN_R`[src]

Bit 22 - Analog watchdog enable on injected channels

`pub fn discnum(&self) -> DISCNUM_R`[src]

Bits 13:15 - Discontinuous mode channel count

`pub fn jdiscen(&self) -> JDISCEN_R`[src]

Bit 12 - Discontinuous mode on injected channels

`pub fn discen(&self) -> DISCEN_R`[src]

Bit 11 - Discontinuous mode on regular channels

`pub fn jauto(&self) -> JAUTO_R`[src]

Bit 10 - Automatic injected group conversion

`pub fn awdsgl(&self) -> AWDSGL_R`[src]

Bit 9 - Enable the watchdog on a single channel in scan mode

`pub fn scan(&self) -> SCAN_R`[src]

Bit 8 - Scan mode

`pub fn jeocie(&self) -> JEOCIE_R`[src]

Bit 7 - Interrupt enable for injected channels

`pub fn awdie(&self) -> AWDIE_R`[src]

Bit 6 - Analog watchdog interrupt enable

`pub fn eocie(&self) -> EOCIE_R`[src]

Bit 5 - Interrupt enable for EOC

`pub fn awdch(&self) -> AWDCH_R`[src]

Bits 0:4 - Analog watchdog channel select bits

`impl R<bool, SWSTART_A>`[src]

`pub fn variant(&self) -> Variant<bool, SWSTART_A>`[src]

Get enumerated values variant

`pub fn is_start(&self) -> bool`[src]

Checks if the value of the field is START

`impl R<u8, EXTEN_A>`[src]

`pub fn variant(&self) -> EXTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_rising_edge(&self) -> bool`[src]

Checks if the value of the field is RISINGEDGE

`pub fn is_falling_edge(&self) -> bool`[src]

Checks if the value of the field is FALLINGEDGE

`pub fn is_both_edges(&self) -> bool`[src]

Checks if the value of the field is BOTHEDGES

`impl R<u8, EXTSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, EXTSEL_A>`[src]

Get enumerated values variant

`pub fn is_tim1cc1(&self) -> bool`[src]

Checks if the value of the field is TIM1CC1

`pub fn is_tim1cc2(&self) -> bool`[src]

Checks if the value of the field is TIM1CC2

`pub fn is_tim1cc3(&self) -> bool`[src]

Checks if the value of the field is TIM1CC3

`pub fn is_tim2cc2(&self) -> bool`[src]

Checks if the value of the field is TIM2CC2

`pub fn is_tim2cc3(&self) -> bool`[src]

Checks if the value of the field is TIM2CC3

`pub fn is_tim2cc4(&self) -> bool`[src]

Checks if the value of the field is TIM2CC4

`pub fn is_tim2trgo(&self) -> bool`[src]

Checks if the value of the field is TIM2TRGO

`impl R<bool, JSWSTART_A>`[src]

`pub fn variant(&self) -> Variant<bool, JSWSTART_A>`[src]

Get enumerated values variant

`pub fn is_start(&self) -> bool`[src]

Checks if the value of the field is START

`impl R<u8, JEXTEN_A>`[src]

`pub fn variant(&self) -> JEXTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_rising_edge(&self) -> bool`[src]

Checks if the value of the field is RISINGEDGE

`pub fn is_falling_edge(&self) -> bool`[src]

Checks if the value of the field is FALLINGEDGE

`pub fn is_both_edges(&self) -> bool`[src]

Checks if the value of the field is BOTHEDGES

`impl R<u8, JEXTSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, JEXTSEL_A>`[src]

Get enumerated values variant

`pub fn is_tim1trgo(&self) -> bool`[src]

Checks if the value of the field is TIM1TRGO

`pub fn is_tim1cc4(&self) -> bool`[src]

Checks if the value of the field is TIM1CC4

`pub fn is_tim2trgo(&self) -> bool`[src]

Checks if the value of the field is TIM2TRGO

`pub fn is_tim2cc1(&self) -> bool`[src]

Checks if the value of the field is TIM2CC1

`pub fn is_tim3cc4(&self) -> bool`[src]

Checks if the value of the field is TIM3CC4

`pub fn is_tim4trgo(&self) -> bool`[src]

Checks if the value of the field is TIM4TRGO

`pub fn is_tim8cc4(&self) -> bool`[src]

Checks if the value of the field is TIM8CC4

`pub fn is_tim1trgo2(&self) -> bool`[src]

Checks if the value of the field is TIM1TRGO2

`pub fn is_tim8trgo(&self) -> bool`[src]

Checks if the value of the field is TIM8TRGO

`pub fn is_tim8trgo2(&self) -> bool`[src]

Checks if the value of the field is TIM8TRGO2

`pub fn is_tim3cc3(&self) -> bool`[src]

`pub fn jswstart(&self) -> JSWSTART_R`[src]

Bit 22 - Start conversion of injected channels

`pub fn jexten(&self) -> JEXTEN_R`[src]

Bits 20:21 - External trigger enable for injected channels

`pub fn jextsel(&self) -> JEXTSEL_R`[src]

Bits 16:19 - External event select for injected group

`pub fn align(&self) -> ALIGN_R`[src]

Bit 11 - Data alignment

`pub fn eocs(&self) -> EOCS_R`[src]

Bit 10 - End of conversion selection

`pub fn dds(&self) -> DDS_R`[src]

Bit 9 - DMA disable selection (for single ADC mode)

`pub fn dma(&self) -> DMA_R`[src]

Bit 8 - Direct memory access mode (for single ADC mode)

`pub fn cont(&self) -> CONT_R`[src]

Bit 1 - Continuous conversion

`pub fn adon(&self) -> ADON_R`[src]

Bit 0 - A/D Converter ON / OFF

`impl R<u8, SMP18_A>`[src]

`pub fn variant(&self) -> SMP18_A`[src]

Get enumerated values variant

`pub fn is_cycles3(&self) -> bool`[src]

Checks if the value of the field is CYCLES3

`pub fn is_cycles15(&self) -> bool`[src]

Checks if the value of the field is CYCLES15

`pub fn is_cycles28(&self) -> bool`[src]

Checks if the value of the field is CYCLES28

`pub fn is_cycles56(&self) -> bool`[src]

Checks if the value of the field is CYCLES56

`pub fn is_cycles84(&self) -> bool`[src]

Checks if the value of the field is CYCLES84

`pub fn is_cycles112(&self) -> bool`[src]

Checks if the value of the field is CYCLES112

`pub fn is_cycles144(&self) -> bool`[src]

Checks if the value of the field is CYCLES144

`pub fn is_cycles480(&self) -> bool`[src]

Checks if the value of the field is CYCLES480

`impl R<u32, Reg<u32, _SMPR1>>`[src]

`pub fn smp18(&self) -> SMP18_R`[src]

Bits 24:26 - Channel 18 sampling time selection

`pub fn smp17(&self) -> SMP17_R`[src]

Bits 21:23 - Channel 17 sampling time selection

`pub fn smp16(&self) -> SMP16_R`[src]

Bits 18:20 - Channel 16 sampling time selection

`pub fn smp15(&self) -> SMP15_R`[src]

Bits 15:17 - Channel 15 sampling time selection

`pub fn smp14(&self) -> SMP14_R`[src]

Bits 12:14 - Channel 14 sampling time selection

`pub fn smp13(&self) -> SMP13_R`[src]

Bits 9:11 - Channel 13 sampling time selection

`pub fn smp12(&self) -> SMP12_R`[src]

Bits 6:8 - Channel 12 sampling time selection

`pub fn smp11(&self) -> SMP11_R`[src]

Bits 3:5 - Channel 11 sampling time selection

`pub fn smp10(&self) -> SMP10_R`[src]

Bits 0:2 - Channel 10 sampling time selection

`impl R<u8, SMP9_A>`[src]

`pub fn variant(&self) -> SMP9_A`[src]

Get enumerated values variant

`pub fn is_cycles3(&self) -> bool`[src]

Checks if the value of the field is CYCLES3

`pub fn is_cycles15(&self) -> bool`[src]

Checks if the value of the field is CYCLES15

`pub fn is_cycles28(&self) -> bool`[src]

Checks if the value of the field is CYCLES28

`pub fn is_cycles56(&self) -> bool`[src]

Checks if the value of the field is CYCLES56

`pub fn is_cycles84(&self) -> bool`[src]

Checks if the value of the field is CYCLES84

`pub fn is_cycles112(&self) -> bool`[src]

Checks if the value of the field is CYCLES112

`pub fn is_cycles144(&self) -> bool`[src]

Checks if the value of the field is CYCLES144

`pub fn is_cycles480(&self) -> bool`[src]

Checks if the value of the field is CYCLES480

`impl R<u32, Reg<u32, _SMPR2>>`[src]

`pub fn smp9(&self) -> SMP9_R`[src]

Bits 27:29 - Channel 9 sampling time selection

`pub fn smp8(&self) -> SMP8_R`[src]

Bits 24:26 - Channel 8 sampling time selection

`pub fn smp7(&self) -> SMP7_R`[src]

Bits 21:23 - Channel 7 sampling time selection

`pub fn smp6(&self) -> SMP6_R`[src]

Bits 18:20 - Channel 6 sampling time selection

`pub fn smp5(&self) -> SMP5_R`[src]

Bits 15:17 - Channel 5 sampling time selection

`pub fn smp4(&self) -> SMP4_R`[src]

Bits 12:14 - Channel 4 sampling time selection

`pub fn smp3(&self) -> SMP3_R`[src]

Bits 9:11 - Channel 3 sampling time selection

`pub fn smp2(&self) -> SMP2_R`[src]

Bits 6:8 - Channel 2 sampling time selection

`pub fn smp1(&self) -> SMP1_R`[src]

Bits 3:5 - Channel 1 sampling time selection

`pub fn smp0(&self) -> SMP0_R`[src]

Bits 0:2 - Channel 0 sampling time selection

`impl R<u32, Reg<u32, _JOFR>>`[src]

`pub fn joffset(&self) -> JOFFSET_R`[src]

Bits 0:11 - Data offset for injected channel x

`impl R<u32, Reg<u32, _HTR>>`[src]

`pub fn ht(&self) -> HT_R`[src]

Bits 0:11 - Analog watchdog higher threshold

`impl R<u32, Reg<u32, _LTR>>`[src]

`pub fn lt(&self) -> LT_R`[src]

Bits 0:11 - Analog watchdog lower threshold

`impl R<u32, Reg<u32, _SQR1>>`[src]

`pub fn l(&self) -> L_R`[src]

Bits 20:23 - Regular channel sequence length

`pub fn sq16(&self) -> SQ16_R`[src]

Bits 15:19 - 16th conversion in regular sequence

`pub fn sq15(&self) -> SQ15_R`[src]

Bits 10:14 - 15th conversion in regular sequence

`pub fn sq14(&self) -> SQ14_R`[src]

Bits 5:9 - 14th conversion in regular sequence

`pub fn sq13(&self) -> SQ13_R`[src]

Bits 0:4 - 13th conversion in regular sequence

`impl R<u32, Reg<u32, _SQR2>>`[src]

`pub fn sq12(&self) -> SQ12_R`[src]

Bits 25:29 - 12th conversion in regular sequence

`pub fn sq11(&self) -> SQ11_R`[src]

Bits 20:24 - 11th conversion in regular sequence

`pub fn sq10(&self) -> SQ10_R`[src]

Bits 15:19 - 10th conversion in regular sequence

`pub fn sq9(&self) -> SQ9_R`[src]

Bits 10:14 - 9th conversion in regular sequence

`pub fn sq8(&self) -> SQ8_R`[src]

Bits 5:9 - 8th conversion in regular sequence

`pub fn sq7(&self) -> SQ7_R`[src]

Bits 0:4 - 7th conversion in regular sequence

`impl R<u32, Reg<u32, _SQR3>>`[src]

`pub fn sq6(&self) -> SQ6_R`[src]

Bits 25:29 - 6th conversion in regular sequence

`pub fn sq5(&self) -> SQ5_R`[src]

Bits 20:24 - 5th conversion in regular sequence

`pub fn sq4(&self) -> SQ4_R`[src]

Bits 15:19 - 4th conversion in regular sequence

`pub fn sq3(&self) -> SQ3_R`[src]

Bits 10:14 - 3rd conversion in regular sequence

`pub fn sq2(&self) -> SQ2_R`[src]

Bits 5:9 - 2nd conversion in regular sequence

`pub fn sq1(&self) -> SQ1_R`[src]

Bits 0:4 - 1st conversion in regular sequence

`impl R<u32, Reg<u32, _JSQR>>`[src]

`pub fn jl(&self) -> JL_R`[src]

Bits 20:21 - Injected sequence length

`pub fn jsq4(&self) -> JSQ4_R`[src]

Bits 15:19 - 4th conversion in injected sequence

`pub fn jsq3(&self) -> JSQ3_R`[src]

Bits 10:14 - 3rd conversion in injected sequence

`pub fn jsq2(&self) -> JSQ2_R`[src]

Bits 5:9 - 2nd conversion in injected sequence

`pub fn jsq1(&self) -> JSQ1_R`[src]

Bits 0:4 - 1st conversion in injected sequence

`impl R<u32, Reg<u32, _JDR>>`[src]

`pub fn jdata(&self) -> JDATA_R`[src]

Bits 0:15 - Injected data

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> Variant<u8, MMS_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`pub fn is_update(&self) -> bool`[src]

Checks if the value of the field is UPDATE

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn mms(&self) -> MMS_R`[src]

Bits 4:6 - Master mode selection

`impl R<bool, UDE_A>`[src]

`pub fn variant(&self) -> UDE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, UIE_A>`[src]

`pub fn variant(&self) -> UIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _DIER>>`[src]

`pub fn ude(&self) -> UDE_R`[src]

Bit 8 - Update DMA request enable

`pub fn uie(&self) -> UIE_R`[src]

Bit 0 - Update interrupt enable

`impl R<bool, UIF_A>`[src]

`pub fn variant(&self) -> UIF_A`[src]

Get enumerated values variant

`pub fn is_clear(&self) -> bool`[src]

Checks if the value of the field is CLEAR

`pub fn is_update_pending(&self) -> bool`[src]

Checks if the value of the field is UPDATEPENDING

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - Low counter value

`pub fn uifcpy(&self) -> UIFCPY_R`[src]

Bit 31 - UIF Copy

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

Checks if the value of the field is NOEVENT

`pub fn is_event(&self) -> bool`[src]

Checks if the value of the field is EVENT

`impl R<u32, Reg<u32, _CSR>>`[src]

`pub fn ovr3(&self) -> OVR3_R`[src]

Bit 21 - Overrun flag of ADC3

`pub fn strt3(&self) -> STRT3_R`[src]

Bit 20 - Regular channel Start flag of ADC 3

`pub fn jstrt3(&self) -> JSTRT3_R`[src]

Bit 19 - Injected channel Start flag of ADC 3

`pub fn jeoc3(&self) -> JEOC3_R`[src]

Bit 18 - Injected channel end of conversion of ADC 3

`pub fn eoc3(&self) -> EOC3_R`[src]

Bit 17 - End of conversion of ADC 3

`pub fn awd3(&self) -> AWD3_R`[src]

Bit 16 - Analog watchdog flag of ADC 3

`pub fn ovr2(&self) -> OVR2_R`[src]

Bit 13 - Overrun flag of ADC 2

`pub fn strt2(&self) -> STRT2_R`[src]

Bit 12 - Regular channel Start flag of ADC 2

`pub fn jstrt2(&self) -> JSTRT2_R`[src]

Bit 11 - Injected channel Start flag of ADC 2

`pub fn jeoc2(&self) -> JEOC2_R`[src]

Bit 10 - Injected channel end of conversion of ADC 2

`pub fn eoc2(&self) -> EOC2_R`[src]

Bit 9 - End of conversion of ADC 2

`pub fn awd2(&self) -> AWD2_R`[src]

Bit 8 - Analog watchdog flag of ADC 2

`pub fn ovr1(&self) -> OVR1_R`[src]

Bit 5 - Overrun flag of ADC 1

`pub fn strt1(&self) -> STRT1_R`[src]

Bit 4 - Regular channel Start flag of ADC 1

`pub fn jstrt1(&self) -> JSTRT1_R`[src]

Bit 3 - Injected channel Start flag of ADC 1

`pub fn jeoc1(&self) -> JEOC1_R`[src]

Bit 2 - Injected channel end of conversion of ADC 1

`pub fn eoc1(&self) -> EOC1_R`[src]

Bit 1 - End of conversion of ADC 1

`pub fn awd1(&self) -> AWD1_R`[src]

Bit 0 - Analog watchdog flag of ADC 1

`impl R<bool, TSVREFE_A>`[src]

`pub fn variant(&self) -> TSVREFE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

Checks if the value of the field is SINGLE

`pub fn is_continuous(&self) -> bool`[src]

Checks if the value of the field is CONTINUOUS

`impl R<u8, MULTI_A>`[src]

`pub fn variant(&self) -> Variant<u8, MULTI_A>`[src]

Get enumerated values variant

`pub fn is_independent(&self) -> bool`[src]

Checks if the value of the field is INDEPENDENT

`pub fn is_dual_rj(&self) -> bool`[src]

Checks if the value of the field is DUALRJ

`pub fn is_dual_ra(&self) -> bool`[src]

Checks if the value of the field is DUALRA

`pub fn is_dual_j(&self) -> bool`[src]

Checks if the value of the field is DUALJ

`pub fn is_dual_r(&self) -> bool`[src]

Checks if the value of the field is DUALR

`pub fn is_dual_i(&self) -> bool`[src]

Checks if the value of the field is DUALI

`pub fn is_dual_a(&self) -> bool`[src]

Checks if the value of the field is DUALA

`pub fn is_triple_rj(&self) -> bool`[src]

Checks if the value of the field is TRIPLERJ

`pub fn is_triple_ra(&self) -> bool`[src]

Checks if the value of the field is TRIPLERA

`pub fn is_triple_j(&self) -> bool`[src]

Checks if the value of the field is TRIPLEJ

`pub fn is_triple_r(&self) -> bool`[src]

Checks if the value of the field is TRIPLER

`pub fn is_triple_i(&self) -> bool`[src]

Checks if the value of the field is TRIPLEI

`pub fn is_triple_a(&self) -> bool`[src]

Checks if the value of the field is TRIPLEA

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn tsvrefe(&self) -> TSVREFE_R`[src]

Bit 23 - Temperature sensor and VREFINT enable

`pub fn vbate(&self) -> VBATE_R`[src]

Bit 22 - VBAT enable

`pub fn adcpre(&self) -> ADCPRE_R`[src]

Bits 16:17 - ADC prescaler

`pub fn dma(&self) -> DMA_R`[src]

Bits 14:15 - Direct memory access mode for multi ADC mode

`pub fn dds(&self) -> DDS_R`[src]

Bit 13 - DMA disable selection for multi-ADC mode

`pub fn delay(&self) -> DELAY_R`[src]

Bits 8:11 - Delay between 2 sampling phases

`pub fn multi(&self) -> MULTI_R`[src]

Bits 0:4 - Multi ADC mode selection

`impl R<u32, Reg<u32, _CDR>>`[src]

`pub fn data2(&self) -> DATA2_R`[src]

Bits 16:31 - 2nd data item of a pair of regular conversions

`pub fn data1(&self) -> DATA1_R`[src]

Bits 0:15 - 1st data item of a pair of regular conversions

`impl R<bool, IDE_A>`[src]

`pub fn variant(&self) -> IDE_A`[src]

Get enumerated values variant

`pub fn is_standard(&self) -> bool`[src]

Checks if the value of the field is STANDARD

`pub fn is_extended(&self) -> bool`[src]

Checks if the value of the field is EXTENDED

`impl R<bool, RTR_A>`[src]

`pub fn variant(&self) -> RTR_A`[src]

Get enumerated values variant

`pub fn is_data(&self) -> bool`[src]

Checks if the value of the field is DATA

`pub fn is_remote(&self) -> bool`[src]

Checks if the value of the field is REMOTE

`impl R<u32, Reg<u32, _TIR>>`[src]

`pub fn stid(&self) -> STID_R`[src]

Bits 21:31 - STID

`pub fn exid(&self) -> EXID_R`[src]

Bits 3:20 - EXID

`pub fn ide(&self) -> IDE_R`[src]

Bit 2 - IDE

`pub fn rtr(&self) -> RTR_R`[src]

Bit 1 - RTR

`pub fn txrq(&self) -> TXRQ_R`[src]

Bit 0 - TXRQ

`impl R<u32, Reg<u32, _TDTR>>`[src]

`pub fn time(&self) -> TIME_R`[src]

Bits 16:31 - TIME

`pub fn tgt(&self) -> TGT_R`[src]

Bit 8 - TGT

`pub fn dlc(&self) -> DLC_R`[src]

Bits 0:3 - DLC

`impl R<u32, Reg<u32, _TDLR>>`[src]

`pub fn data3(&self) -> DATA3_R`[src]

Bits 24:31 - DATA3

`pub fn data2(&self) -> DATA2_R`[src]

Bits 16:23 - DATA2

`pub fn data1(&self) -> DATA1_R`[src]

Bits 8:15 - DATA1

`pub fn data0(&self) -> DATA0_R`[src]

Bits 0:7 - DATA0

`impl R<u32, Reg<u32, _TDHR>>`[src]

`pub fn data7(&self) -> DATA7_R`[src]

Bits 24:31 - DATA7

`pub fn data6(&self) -> DATA6_R`[src]

Bits 16:23 - DATA6

`pub fn data5(&self) -> DATA5_R`[src]

Bits 8:15 - DATA5

`pub fn data4(&self) -> DATA4_R`[src]

Bits 0:7 - DATA4

`impl R<bool, IDE_A>`[src]

`pub fn variant(&self) -> IDE_A`[src]

Get enumerated values variant

`pub fn is_standard(&self) -> bool`[src]

Checks if the value of the field is STANDARD

`pub fn is_extended(&self) -> bool`[src]

Checks if the value of the field is EXTENDED

`impl R<bool, RTR_A>`[src]

`pub fn variant(&self) -> RTR_A`[src]

Get enumerated values variant

`pub fn is_data(&self) -> bool`[src]

Checks if the value of the field is DATA

`pub fn is_remote(&self) -> bool`[src]

Checks if the value of the field is REMOTE

`impl R<u32, Reg<u32, _RIR>>`[src]

`pub fn stid(&self) -> STID_R`[src]

Bits 21:31 - STID

`pub fn exid(&self) -> EXID_R`[src]

Bits 3:20 - EXID

`pub fn ide(&self) -> IDE_R`[src]

Bit 2 - IDE

`pub fn rtr(&self) -> RTR_R`[src]

Bit 1 - RTR

`impl R<u32, Reg<u32, _RDTR>>`[src]

`pub fn time(&self) -> TIME_R`[src]

Bits 16:31 - TIME

`pub fn fmi(&self) -> FMI_R`[src]

Bits 8:15 - FMI

`pub fn dlc(&self) -> DLC_R`[src]

Bits 0:3 - DLC

`impl R<u32, Reg<u32, _RDLR>>`[src]

`pub fn data3(&self) -> DATA3_R`[src]

Bits 24:31 - DATA3

`pub fn data2(&self) -> DATA2_R`[src]

Bits 16:23 - DATA2

`pub fn data1(&self) -> DATA1_R`[src]

Bits 8:15 - DATA1

`pub fn data0(&self) -> DATA0_R`[src]

Bits 0:7 - DATA0

`impl R<u32, Reg<u32, _RDHR>>`[src]

`pub fn data7(&self) -> DATA7_R`[src]

Bits 24:31 - DATA7

`pub fn data6(&self) -> DATA6_R`[src]

Bits 16:23 - DATA6

`pub fn data5(&self) -> DATA5_R`[src]

Bits 8:15 - DATA5

`pub fn data4(&self) -> DATA4_R`[src]

Bits 0:7 - DATA4

`impl R<u32, Reg<u32, _FR1>>`[src]

`pub fn fb0(&self) -> FB0_R`[src]

Bit 0 - Filter bits

`pub fn fb1(&self) -> FB1_R`[src]

Bit 1 - Filter bits

`pub fn fb2(&self) -> FB2_R`[src]

Bit 2 - Filter bits

`pub fn fb3(&self) -> FB3_R`[src]

Bit 3 - Filter bits

`pub fn fb4(&self) -> FB4_R`[src]

Bit 4 - Filter bits

`pub fn fb5(&self) -> FB5_R`[src]

Bit 5 - Filter bits

`pub fn fb6(&self) -> FB6_R`[src]

Bit 6 - Filter bits

`pub fn fb7(&self) -> FB7_R`[src]

Bit 7 - Filter bits

`pub fn fb8(&self) -> FB8_R`[src]

Bit 8 - Filter bits

`pub fn fb9(&self) -> FB9_R`[src]

Bit 9 - Filter bits

`pub fn fb10(&self) -> FB10_R`[src]

Bit 10 - Filter bits

`pub fn fb11(&self) -> FB11_R`[src]

Bit 11 - Filter bits

`pub fn fb12(&self) -> FB12_R`[src]

Bit 12 - Filter bits

`pub fn fb13(&self) -> FB13_R`[src]

Bit 13 - Filter bits

`pub fn fb14(&self) -> FB14_R`[src]

Bit 14 - Filter bits

`pub fn fb15(&self) -> FB15_R`[src]

Bit 15 - Filter bits

`pub fn fb16(&self) -> FB16_R`[src]

Bit 16 - Filter bits

`pub fn fb17(&self) -> FB17_R`[src]

Bit 17 - Filter bits

`pub fn fb18(&self) -> FB18_R`[src]

Bit 18 - Filter bits

`pub fn fb19(&self) -> FB19_R`[src]

Bit 19 - Filter bits

`pub fn fb20(&self) -> FB20_R`[src]

Bit 20 - Filter bits

`pub fn fb21(&self) -> FB21_R`[src]

Bit 21 - Filter bits

`pub fn fb22(&self) -> FB22_R`[src]

Bit 22 - Filter bits

`pub fn fb23(&self) -> FB23_R`[src]

Bit 23 - Filter bits

`pub fn fb24(&self) -> FB24_R`[src]

Bit 24 - Filter bits

`pub fn fb25(&self) -> FB25_R`[src]

Bit 25 - Filter bits

`pub fn fb26(&self) -> FB26_R`[src]

Bit 26 - Filter bits

`pub fn fb27(&self) -> FB27_R`[src]

Bit 27 - Filter bits

`pub fn fb28(&self) -> FB28_R`[src]

Bit 28 - Filter bits

`pub fn fb29(&self) -> FB29_R`[src]

Bit 29 - Filter bits

`pub fn fb30(&self) -> FB30_R`[src]

Bit 30 - Filter bits

`pub fn fb31(&self) -> FB31_R`[src]

Bit 31 - Filter bits

`impl R<u32, Reg<u32, _FR2>>`[src]

`pub fn fb0(&self) -> FB0_R`[src]

Bit 0 - Filter bits

`pub fn fb1(&self) -> FB1_R`[src]

Bit 1 - Filter bits

`pub fn fb2(&self) -> FB2_R`[src]

Bit 2 - Filter bits

`pub fn fb3(&self) -> FB3_R`[src]

Bit 3 - Filter bits

`pub fn fb4(&self) -> FB4_R`[src]

Bit 4 - Filter bits

`pub fn fb5(&self) -> FB5_R`[src]

Bit 5 - Filter bits

`pub fn fb6(&self) -> FB6_R`[src]

Bit 6 - Filter bits

`pub fn fb7(&self) -> FB7_R`[src]

Bit 7 - Filter bits

`pub fn fb8(&self) -> FB8_R`[src]

Bit 8 - Filter bits

`pub fn fb9(&self) -> FB9_R`[src]

Bit 9 - Filter bits

`pub fn fb10(&self) -> FB10_R`[src]

Bit 10 - Filter bits

`pub fn fb11(&self) -> FB11_R`[src]

Bit 11 - Filter bits

`pub fn fb12(&self) -> FB12_R`[src]

Bit 12 - Filter bits

`pub fn fb13(&self) -> FB13_R`[src]

Bit 13 - Filter bits

`pub fn fb14(&self) -> FB14_R`[src]

Bit 14 - Filter bits

`pub fn fb15(&self) -> FB15_R`[src]

Bit 15 - Filter bits

`pub fn fb16(&self) -> FB16_R`[src]

Bit 16 - Filter bits

`pub fn fb17(&self) -> FB17_R`[src]

Bit 17 - Filter bits

`pub fn fb18(&self) -> FB18_R`[src]

Bit 18 - Filter bits

`pub fn fb19(&self) -> FB19_R`[src]

Bit 19 - Filter bits

`pub fn fb20(&self) -> FB20_R`[src]

Bit 20 - Filter bits

`pub fn fb21(&self) -> FB21_R`[src]

Bit 21 - Filter bits

`pub fn fb22(&self) -> FB22_R`[src]

Bit 22 - Filter bits

`pub fn fb23(&self) -> FB23_R`[src]

Bit 23 - Filter bits

`pub fn fb24(&self) -> FB24_R`[src]

Bit 24 - Filter bits

`pub fn fb25(&self) -> FB25_R`[src]

Bit 25 - Filter bits

`pub fn fb26(&self) -> FB26_R`[src]

Bit 26 - Filter bits

`pub fn fb27(&self) -> FB27_R`[src]

Bit 27 - Filter bits

`pub fn fb28(&self) -> FB28_R`[src]

Bit 28 - Filter bits

`pub fn fb29(&self) -> FB29_R`[src]

Bit 29 - Filter bits

`pub fn fb30(&self) -> FB30_R`[src]

Bit 30 - Filter bits

`pub fn fb31(&self) -> FB31_R`[src]

Bit 31 - Filter bits

`impl R<u32, Reg<u32, _MCR>>`[src]

`pub fn dbf(&self) -> DBF_R`[src]

Bit 16 - DBF

`pub fn reset(&self) -> RESET_R`[src]

Bit 15 - RESET

`pub fn ttcm(&self) -> TTCM_R`[src]

Bit 7 - TTCM

`pub fn abom(&self) -> ABOM_R`[src]

Bit 6 - ABOM

`pub fn awum(&self) -> AWUM_R`[src]

Bit 5 - AWUM

`pub fn nart(&self) -> NART_R`[src]

Bit 4 - NART

`pub fn rflm(&self) -> RFLM_R`[src]

Bit 3 - RFLM

`pub fn txfp(&self) -> TXFP_R`[src]

Bit 2 - TXFP

`pub fn sleep(&self) -> SLEEP_R`[src]

Bit 1 - SLEEP

`pub fn inrq(&self) -> INRQ_R`[src]

Bit 0 - INRQ

`impl R<u32, Reg<u32, _MSR>>`[src]

`pub fn rx(&self) -> RX_R`[src]

Bit 11 - RX

`pub fn samp(&self) -> SAMP_R`[src]

Bit 10 - SAMP

`pub fn rxm(&self) -> RXM_R`[src]

Bit 9 - RXM

`pub fn txm(&self) -> TXM_R`[src]

Bit 8 - TXM

`pub fn slaki(&self) -> SLAKI_R`[src]

Bit 4 - SLAKI

`pub fn wkui(&self) -> WKUI_R`[src]

Bit 3 - WKUI

`pub fn erri(&self) -> ERRI_R`[src]

Bit 2 - ERRI

`pub fn slak(&self) -> SLAK_R`[src]

Bit 1 - SLAK

`pub fn inak(&self) -> INAK_R`[src]

Bit 0 - INAK

`impl R<u32, Reg<u32, _TSR>>`[src]

`pub fn low2(&self) -> LOW2_R`[src]

Bit 31 - Lowest priority flag for mailbox 2

`pub fn low1(&self) -> LOW1_R`[src]

Bit 30 - Lowest priority flag for mailbox 1

`pub fn low0(&self) -> LOW0_R`[src]

Bit 29 - Lowest priority flag for mailbox 0

`pub fn tme2(&self) -> TME2_R`[src]

Bit 28 - Lowest priority flag for mailbox 2

`pub fn tme1(&self) -> TME1_R`[src]

Bit 27 - Lowest priority flag for mailbox 1

`pub fn tme0(&self) -> TME0_R`[src]

Bit 26 - Lowest priority flag for mailbox 0

`pub fn code(&self) -> CODE_R`[src]

Bits 24:25 - CODE

`pub fn abrq2(&self) -> ABRQ2_R`[src]

Bit 23 - ABRQ2

`pub fn terr2(&self) -> TERR2_R`[src]

Bit 19 - TERR2

`pub fn alst2(&self) -> ALST2_R`[src]

Bit 18 - ALST2

`pub fn txok2(&self) -> TXOK2_R`[src]

Bit 17 - TXOK2

`pub fn rqcp2(&self) -> RQCP2_R`[src]

Bit 16 - RQCP2

`pub fn abrq1(&self) -> ABRQ1_R`[src]

Bit 15 - ABRQ1

`pub fn terr1(&self) -> TERR1_R`[src]

Bit 11 - TERR1

`pub fn alst1(&self) -> ALST1_R`[src]

Bit 10 - ALST1

`pub fn txok1(&self) -> TXOK1_R`[src]

Bit 9 - TXOK1

`pub fn rqcp1(&self) -> RQCP1_R`[src]

Bit 8 - RQCP1

`pub fn abrq0(&self) -> ABRQ0_R`[src]

Bit 7 - ABRQ0

`pub fn terr0(&self) -> TERR0_R`[src]

Bit 3 - TERR0

`pub fn alst0(&self) -> ALST0_R`[src]

Bit 2 - ALST0

`pub fn txok0(&self) -> TXOK0_R`[src]

Bit 1 - TXOK0

`pub fn rqcp0(&self) -> RQCP0_R`[src]

Bit 0 - RQCP0

`pub fn lecie(&self) -> LECIE_R`[src]

Bit 11 - LECIE

`pub fn bofie(&self) -> BOFIE_R`[src]

Bit 10 - BOFIE

`pub fn epvie(&self) -> EPVIE_R`[src]

Bit 9 - EPVIE

`pub fn ewgie(&self) -> EWGIE_R`[src]

Bit 8 - EWGIE

`pub fn fovie1(&self) -> FOVIE1_R`[src]

Bit 6 - FOVIE1

`pub fn ffie1(&self) -> FFIE1_R`[src]

Bit 5 - FFIE1

`pub fn fmpie1(&self) -> FMPIE1_R`[src]

Bit 4 - FMPIE1

`pub fn fovie0(&self) -> FOVIE0_R`[src]

Bit 3 - FOVIE0

`pub fn ffie0(&self) -> FFIE0_R`[src]

Bit 2 - FFIE0

`pub fn fmpie0(&self) -> FMPIE0_R`[src]

Bit 1 - FMPIE0

`pub fn tmeie(&self) -> TMEIE_R`[src]

Bit 0 - TMEIE

`impl R<u8, LEC_A>`[src]

`pub fn variant(&self) -> LEC_A`[src]

Get enumerated values variant

`pub fn is_no_error(&self) -> bool`[src]

Checks if the value of the field is NOERROR

`pub fn is_stuff(&self) -> bool`[src]

Checks if the value of the field is STUFF

`pub fn is_form(&self) -> bool`[src]

Checks if the value of the field is FORM

`pub fn is_ack(&self) -> bool`[src]

Checks if the value of the field is ACK

`pub fn is_bit_recessive(&self) -> bool`[src]

Checks if the value of the field is BITRECESSIVE

`pub fn is_bit_dominant(&self) -> bool`[src]

Checks if the value of the field is BITDOMINANT

`pub fn is_crc(&self) -> bool`[src]

Checks if the value of the field is CRC

`pub fn is_custom(&self) -> bool`[src]

Checks if the value of the field is CUSTOM

`impl R<u32, Reg<u32, _ESR>>`[src]

`pub fn rec(&self) -> REC_R`[src]

Bits 24:31 - REC

`pub fn tec(&self) -> TEC_R`[src]

Bits 16:23 - TEC

`pub fn lec(&self) -> LEC_R`[src]

Bits 4:6 - LEC

`pub fn boff(&self) -> BOFF_R`[src]

Bit 2 - BOFF

`pub fn epvf(&self) -> EPVF_R`[src]

Bit 1 - EPVF

`pub fn ewgf(&self) -> EWGF_R`[src]

Bit 0 - EWGF

`impl R<bool, SILM_A>`[src]

`pub fn variant(&self) -> SILM_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_silent(&self) -> bool`[src]

Checks if the value of the field is SILENT

`impl R<bool, LBKM_A>`[src]

`pub fn variant(&self) -> LBKM_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _BTR>>`[src]

`pub fn silm(&self) -> SILM_R`[src]

Bit 31 - SILM

`pub fn lbkm(&self) -> LBKM_R`[src]

Bit 30 - LBKM

`pub fn sjw(&self) -> SJW_R`[src]

Bits 24:25 - SJW

`pub fn ts2(&self) -> TS2_R`[src]

Bits 20:22 - TS2

`pub fn ts1(&self) -> TS1_R`[src]

Bits 16:19 - TS1

`pub fn brp(&self) -> BRP_R`[src]

Bits 0:9 - BRP

`impl R<u32, Reg<u32, _FMR>>`[src]

`pub fn finit(&self) -> FINIT_R`[src]

Bit 0 - FINIT

`impl R<u32, Reg<u32, _FM1R>>`[src]

`pub fn fbm0(&self) -> FBM0_R`[src]

Bit 0 - Filter mode

`pub fn fbm1(&self) -> FBM1_R`[src]

Bit 1 - Filter mode

`pub fn fbm2(&self) -> FBM2_R`[src]

Bit 2 - Filter mode

`pub fn fbm3(&self) -> FBM3_R`[src]

Bit 3 - Filter mode

`pub fn fbm4(&self) -> FBM4_R`[src]

Bit 4 - Filter mode

`pub fn fbm5(&self) -> FBM5_R`[src]

Bit 5 - Filter mode

`pub fn fbm6(&self) -> FBM6_R`[src]

Bit 6 - Filter mode

`pub fn fbm7(&self) -> FBM7_R`[src]

Bit 7 - Filter mode

`pub fn fbm8(&self) -> FBM8_R`[src]

Bit 8 - Filter mode

`pub fn fbm9(&self) -> FBM9_R`[src]

Bit 9 - Filter mode

`pub fn fbm10(&self) -> FBM10_R`[src]

Bit 10 - Filter mode

`pub fn fbm11(&self) -> FBM11_R`[src]

Bit 11 - Filter mode

`pub fn fbm12(&self) -> FBM12_R`[src]

Bit 12 - Filter mode

`pub fn fbm13(&self) -> FBM13_R`[src]

Bit 13 - Filter mode

`impl R<u32, Reg<u32, _FS1R>>`[src]

`pub fn fsc0(&self) -> FSC0_R`[src]

Bit 0 - Filter scale configuration

`pub fn fsc1(&self) -> FSC1_R`[src]

Bit 1 - Filter scale configuration

`pub fn fsc2(&self) -> FSC2_R`[src]

Bit 2 - Filter scale configuration

`pub fn fsc3(&self) -> FSC3_R`[src]

Bit 3 - Filter scale configuration

`pub fn fsc4(&self) -> FSC4_R`[src]

Bit 4 - Filter scale configuration

`pub fn fsc5(&self) -> FSC5_R`[src]

Bit 5 - Filter scale configuration

`pub fn fsc6(&self) -> FSC6_R`[src]

Bit 6 - Filter scale configuration

`pub fn fsc7(&self) -> FSC7_R`[src]

Bit 7 - Filter scale configuration

`pub fn fsc8(&self) -> FSC8_R`[src]

Bit 8 - Filter scale configuration

`pub fn fsc9(&self) -> FSC9_R`[src]

Bit 9 - Filter scale configuration

`pub fn fsc10(&self) -> FSC10_R`[src]

Bit 10 - Filter scale configuration

`pub fn fsc11(&self) -> FSC11_R`[src]

Bit 11 - Filter scale configuration

`pub fn fsc12(&self) -> FSC12_R`[src]

Bit 12 - Filter scale configuration

`pub fn fsc13(&self) -> FSC13_R`[src]

Bit 13 - Filter scale configuration

`impl R<u32, Reg<u32, _FFA1R>>`[src]

`pub fn ffa0(&self) -> FFA0_R`[src]

Bit 0 - Filter FIFO assignment for filter 0

`pub fn ffa1(&self) -> FFA1_R`[src]

Bit 1 - Filter FIFO assignment for filter 1

`pub fn ffa2(&self) -> FFA2_R`[src]

Bit 2 - Filter FIFO assignment for filter 2

`pub fn ffa3(&self) -> FFA3_R`[src]

Bit 3 - Filter FIFO assignment for filter 3

`pub fn ffa4(&self) -> FFA4_R`[src]

Bit 4 - Filter FIFO assignment for filter 4

`pub fn ffa5(&self) -> FFA5_R`[src]

Bit 5 - Filter FIFO assignment for filter 5

`pub fn ffa6(&self) -> FFA6_R`[src]

Bit 6 - Filter FIFO assignment for filter 6

`pub fn ffa7(&self) -> FFA7_R`[src]

Bit 7 - Filter FIFO assignment for filter 7

`pub fn ffa8(&self) -> FFA8_R`[src]

Bit 8 - Filter FIFO assignment for filter 8

`pub fn ffa9(&self) -> FFA9_R`[src]

Bit 9 - Filter FIFO assignment for filter 9

`pub fn ffa10(&self) -> FFA10_R`[src]

Bit 10 - Filter FIFO assignment for filter 10

`pub fn ffa11(&self) -> FFA11_R`[src]

Bit 11 - Filter FIFO assignment for filter 11

`pub fn ffa12(&self) -> FFA12_R`[src]

Bit 12 - Filter FIFO assignment for filter 12

`pub fn ffa13(&self) -> FFA13_R`[src]

Bit 13 - Filter FIFO assignment for filter 13

`impl R<u32, Reg<u32, _FA1R>>`[src]

`pub fn fact0(&self) -> FACT0_R`[src]

Bit 0 - Filter active

`pub fn fact1(&self) -> FACT1_R`[src]

Bit 1 - Filter active

`pub fn fact2(&self) -> FACT2_R`[src]

Bit 2 - Filter active

`pub fn fact3(&self) -> FACT3_R`[src]

Bit 3 - Filter active

`pub fn fact4(&self) -> FACT4_R`[src]

Bit 4 - Filter active

`pub fn fact5(&self) -> FACT5_R`[src]

Bit 5 - Filter active

`pub fn fact6(&self) -> FACT6_R`[src]

Bit 6 - Filter active

`pub fn fact7(&self) -> FACT7_R`[src]

Bit 7 - Filter active

`pub fn fact8(&self) -> FACT8_R`[src]

Bit 8 - Filter active

`pub fn fact9(&self) -> FACT9_R`[src]

Bit 9 - Filter active

`pub fn fact10(&self) -> FACT10_R`[src]

Bit 10 - Filter active

`pub fn fact11(&self) -> FACT11_R`[src]

Bit 11 - Filter active

`pub fn fact12(&self) -> FACT12_R`[src]

Bit 12 - Filter active

`pub fn fact13(&self) -> FACT13_R`[src]

Bit 13 - Filter active

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&self) -> DR_R`[src]

Bits 0:31 - Data Register

`impl R<u32, Reg<u32, _IDR>>`[src]

`pub fn idr(&self) -> IDR_R`[src]

Bits 0:7 - Independent Data register

`impl R<u32, Reg<u32, _INIT>>`[src]

`pub fn crc_init(&self) -> CRC_INIT_R`[src]

Bits 0:31 - Programmable initial CRC value

`impl R<u32, Reg<u32, _POL>>`[src]

`pub fn pol(&self) -> POL_R`[src]

Bits 0:31 - Programmable polynomial

`impl R<u32, Reg<u32, _IDCODE>>`[src]

`pub fn dev_id(&self) -> DEV_ID_R`[src]

Bits 0:11 - DEV_ID

`pub fn rev_id(&self) -> REV_ID_R`[src]

Bits 16:31 - REV_ID

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn dbg_sleep(&self) -> DBG_SLEEP_R`[src]

Bit 0 - DBG_SLEEP

`pub fn dbg_stop(&self) -> DBG_STOP_R`[src]

Bit 1 - DBG_STOP

`pub fn dbg_standby(&self) -> DBG_STANDBY_R`[src]

Bit 2 - DBG_STANDBY

`pub fn trace_ioen(&self) -> TRACE_IOEN_R`[src]

Bit 5 - TRACE_IOEN

`pub fn trace_mode(&self) -> TRACE_MODE_R`[src]

Bits 6:7 - TRACE_MODE

`impl R<u32, Reg<u32, _APB1_FZ>>`[src]

`pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R`[src]

Bit 0 - DBG_TIM2_STOP

`pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R`[src]

Bit 1 - DBG_TIM3 _STOP

`pub fn dbg_tim4_stop(&self) -> DBG_TIM4_STOP_R`[src]

Bit 2 - DBG_TIM4_STOP

`pub fn dbg_tim5_stop(&self) -> DBG_TIM5_STOP_R`[src]

Bit 3 - DBG_TIM5_STOP

`pub fn dbg_tim6_stop(&self) -> DBG_TIM6_STOP_R`[src]

Bit 4 - DBG_TIM6_STOP

`pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R`[src]

Bit 5 - DBG_TIM7_STOP

`pub fn dbg_tim12_stop(&self) -> DBG_TIM12_STOP_R`[src]

Bit 6 - DBG_TIM12_STOP

`pub fn dbg_tim13_stop(&self) -> DBG_TIM13_STOP_R`[src]

Bit 7 - DBG_TIM13_STOP

`pub fn dbg_tim14_stop(&self) -> DBG_TIM14_STOP_R`[src]

Bit 8 - DBG_TIM14_STOP

`pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R`[src]

Bit 11 - DBG_WWDG_STOP

`pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R`[src]

Bit 12 - DBG_IWDEG_STOP

`pub fn dbg_j2c1_smbus_timeout(&self) -> DBG_J2C1_SMBUS_TIMEOUT_R`[src]

Bit 21 - DBG_J2C1_SMBUS_TIMEOUT

`pub fn dbg_j2c2_smbus_timeout(&self) -> DBG_J2C2_SMBUS_TIMEOUT_R`[src]

Bit 22 - DBG_J2C2_SMBUS_TIMEOUT

`pub fn dbg_j2c3smbus_timeout(&self) -> DBG_J2C3SMBUS_TIMEOUT_R`[src]

Bit 23 - DBG_J2C3SMBUS_TIMEOUT

`pub fn dbg_can1_stop(&self) -> DBG_CAN1_STOP_R`[src]

Bit 25 - DBG_CAN1_STOP

`pub fn dbg_can2_stop(&self) -> DBG_CAN2_STOP_R`[src]

Bit 26 - DBG_CAN2_STOP

`impl R<u32, Reg<u32, _APB2_FZ>>`[src]

`pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R`[src]

Bit 0 - TIM1 counter stopped when core is halted

`pub fn dbg_tim8_stop(&self) -> DBG_TIM8_STOP_R`[src]

Bit 1 - TIM8 counter stopped when core is halted

`pub fn dbg_tim9_stop(&self) -> DBG_TIM9_STOP_R`[src]

Bit 16 - TIM9 counter stopped when core is halted

`pub fn dbg_tim10_stop(&self) -> DBG_TIM10_STOP_R`[src]

Bit 17 - TIM10 counter stopped when core is halted

`pub fn dbg_tim11_stop(&self) -> DBG_TIM11_STOP_R`[src]

Bit 18 - TIM11 counter stopped when core is halted

`impl R<bool, DMAUDRIE2_A>`[src]

`pub fn variant(&self) -> DMAUDRIE2_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, DMAEN2_A>`[src]

`pub fn variant(&self) -> DMAEN2_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, WAVE2_A>`[src]

`pub fn variant(&self) -> Variant<u8, WAVE2_A>`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_noise(&self) -> bool`[src]

Checks if the value of the field is NOISE

`pub fn is_triangle(&self) -> bool`[src]

Checks if the value of the field is TRIANGLE

`impl R<u8, TSEL2_A>`[src]

`pub fn variant(&self) -> TSEL2_A`[src]

Get enumerated values variant

`pub fn is_tim6_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM6_TRGO

`pub fn is_tim8_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM8_TRGO

`pub fn is_tim7_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM7_TRGO

`pub fn is_tim5_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM5_TRGO

`pub fn is_tim2_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM2_TRGO

`pub fn is_tim4_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM4_TRGO

`pub fn is_exti9(&self) -> bool`[src]

Checks if the value of the field is EXTI9

`pub fn is_software(&self) -> bool`[src]

Checks if the value of the field is SOFTWARE

`impl R<bool, TEN2_A>`[src]

`pub fn variant(&self) -> TEN2_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, BOFF2_A>`[src]

`pub fn variant(&self) -> BOFF2_A`[src]

Get enumerated values variant

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`impl R<bool, EN2_A>`[src]

`pub fn variant(&self) -> EN2_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, WAVE1_A>`[src]

`pub fn variant(&self) -> Variant<u8, WAVE1_A>`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_noise(&self) -> bool`[src]

Checks if the value of the field is NOISE

`pub fn is_triangle(&self) -> bool`[src]

Checks if the value of the field is TRIANGLE

`impl R<u8, TSEL1_A>`[src]

`pub fn variant(&self) -> Variant<u8, TSEL1_A>`[src]

Get enumerated values variant

`pub fn is_tim6_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM6_TRGO

`pub fn is_tim3_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM3_TRGO

`pub fn is_tim7_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM7_TRGO

`pub fn is_tim15_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM15_TRGO

`pub fn is_tim2_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM2_TRGO

`pub fn is_exti9(&self) -> bool`[src]

Checks if the value of the field is EXTI9

`pub fn is_software(&self) -> bool`[src]

Checks if the value of the field is SOFTWARE

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn dmaudrie2(&self) -> DMAUDRIE2_R`[src]

Bit 29 - DAC channel2 DMA underrun interrupt enable

`pub fn dmaen2(&self) -> DMAEN2_R`[src]

Bit 28 - DAC channel2 DMA enable

`pub fn mamp2(&self) -> MAMP2_R`[src]

Bits 24:27 - DAC channel2 mask/amplitude selector

`pub fn wave2(&self) -> WAVE2_R`[src]

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

`pub fn tsel2(&self) -> TSEL2_R`[src]

Bits 19:21 - DAC channel2 trigger selection

`pub fn ten2(&self) -> TEN2_R`[src]

Bit 18 - DAC channel2 trigger enable

`pub fn boff2(&self) -> BOFF2_R`[src]

Bit 17 - DAC channel2 output buffer disable

`pub fn en2(&self) -> EN2_R`[src]

Bit 16 - DAC channel2 enable

`pub fn dmaudrie1(&self) -> DMAUDRIE1_R`[src]

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

`pub fn dmaen1(&self) -> DMAEN1_R`[src]

Bit 12 - DAC channel1 DMA enable

`pub fn mamp1(&self) -> MAMP1_R`[src]

Bits 8:11 - DAC channel1 mask/amplitude selector

`pub fn wave1(&self) -> WAVE1_R`[src]

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

`pub fn tsel1(&self) -> TSEL1_R`[src]

Bits 3:5 - DAC channel1 trigger selection

`pub fn ten1(&self) -> TEN1_R`[src]

Bit 2 - DAC channel1 trigger enable

`pub fn boff1(&self) -> BOFF1_R`[src]

Bit 1 - DAC channel1 output buffer disable

`pub fn en1(&self) -> EN1_R`[src]

Bit 0 - DAC channel1 enable

`impl R<u32, Reg<u32, _DHR12R1>>`[src]

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

`impl R<u32, Reg<u32, _DHR12L1>>`[src]

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

`impl R<u32, Reg<u32, _DHR8R1>>`[src]

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

`impl R<u32, Reg<u32, _DHR12R2>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 0:11 - DAC channel2 12-bit right-aligned data

`impl R<u32, Reg<u32, _DHR12L2>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 4:15 - DAC channel2 12-bit left-aligned data

`impl R<u32, Reg<u32, _DHR8R2>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 0:7 - DAC channel2 8-bit right-aligned data

`impl R<u32, Reg<u32, _DHR12RD>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 16:27 - DAC channel2 12-bit right-aligned data

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

`impl R<u32, Reg<u32, _DHR12LD>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 20:31 - DAC channel2 12-bit left-aligned data

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

`impl R<u32, Reg<u32, _DHR8RD>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 8:15 - DAC channel2 8-bit right-aligned data

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

`impl R<u32, Reg<u32, _DOR1>>`[src]

`pub fn dacc1dor(&self) -> DACC1DOR_R`[src]

Bits 0:11 - DAC channel1 data output

`impl R<u32, Reg<u32, _DOR2>>`[src]

`pub fn dacc2dor(&self) -> DACC2DOR_R`[src]

Bits 0:11 - DAC channel2 data output

`impl R<bool, DMAUDR2_A>`[src]

`pub fn variant(&self) -> DMAUDR2_A`[src]

Get enumerated values variant

`pub fn is_no_underrun(&self) -> bool`[src]

Checks if the value of the field is NOUNDERRUN

`pub fn is_underrun(&self) -> bool`[src]

Checks if the value of the field is UNDERRUN

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn dmaudr2(&self) -> DMAUDR2_R`[src]

Bit 29 - DAC channel2 DMA underrun flag

`pub fn dmaudr1(&self) -> DMAUDR1_R`[src]

Bit 13 - DAC channel1 DMA underrun flag

`impl R<u8, MBURST_A>`[src]

`pub fn variant(&self) -> MBURST_A`[src]

Get enumerated values variant

`pub fn is_single(&self) -> bool`[src]

Checks if the value of the field is SINGLE

`pub fn is_incr4(&self) -> bool`[src]

Checks if the value of the field is INCR4

`pub fn is_incr8(&self) -> bool`[src]

Checks if the value of the field is INCR8

`pub fn is_medium(&self) -> bool`[src]

Checks if the value of the field is MEDIUM

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_very_high(&self) -> bool`[src]

Checks if the value of the field is VERYHIGH

`impl R<bool, PINCOS_A>`[src]

`pub fn variant(&self) -> PINCOS_A`[src]

Get enumerated values variant

`pub fn is_psize(&self) -> bool`[src]

Checks if the value of the field is PSIZE

`pub fn is_fixed4(&self) -> bool`[src]

Checks if the value of the field is FIXED4

`impl R<u8, MSIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, MSIZE_A>`[src]

Get enumerated values variant

`pub fn is_bits8(&self) -> bool`[src]

Checks if the value of the field is BITS8

`pub fn is_bits16(&self) -> bool`[src]

Checks if the value of the field is BITS16

`pub fn is_bits32(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn chsel(&self) -> CHSEL_R`[src]

Bits 25:28 - Channel selection

`pub fn mburst(&self) -> MBURST_R`[src]

Bits 23:24 - Memory burst transfer configuration

`pub fn pburst(&self) -> PBURST_R`[src]

Bits 21:22 - Peripheral burst transfer configuration

`pub fn ct(&self) -> CT_R`[src]

Bit 19 - Current target (only in double buffer mode)

`pub fn dbm(&self) -> DBM_R`[src]

Bit 18 - Double buffer mode

`pub fn pl(&self) -> PL_R`[src]

Bits 16:17 - Priority level

`pub fn pincos(&self) -> PINCOS_R`[src]

Bit 15 - Peripheral increment offset size

`pub fn msize(&self) -> MSIZE_R`[src]

Bits 13:14 - Memory data size

`pub fn psize(&self) -> PSIZE_R`[src]

Bits 11:12 - Peripheral data size

`pub fn minc(&self) -> MINC_R`[src]

Bit 10 - Memory increment mode

`pub fn pinc(&self) -> PINC_R`[src]

Bit 9 - Peripheral increment mode

`pub fn circ(&self) -> CIRC_R`[src]

Bit 8 - Circular mode

`pub fn dir(&self) -> DIR_R`[src]

Bits 6:7 - Data transfer direction

`pub fn pfctrl(&self) -> PFCTRL_R`[src]

Bit 5 - Peripheral flow controller

`pub fn tcie(&self) -> TCIE_R`[src]

Bit 4 - Transfer complete interrupt enable

`pub fn htie(&self) -> HTIE_R`[src]

Bit 3 - Half transfer interrupt enable

`pub fn teie(&self) -> TEIE_R`[src]

Bit 2 - Transfer error interrupt enable

`pub fn dmeie(&self) -> DMEIE_R`[src]

Bit 1 - Direct mode error interrupt enable

`pub fn en(&self) -> EN_R`[src]

Bit 0 - Stream enable / flag stream ready when read low

`impl R<u32, Reg<u32, _NDTR>>`[src]

`pub fn ndt(&self) -> NDT_R`[src]

Bits 0:15 - Number of data items to transfer

`impl R<u32, Reg<u32, _PAR>>`[src]

`pub fn pa(&self) -> PA_R`[src]

Bits 0:31 - Peripheral address

`impl R<u32, Reg<u32, _M0AR>>`[src]

`pub fn m0a(&self) -> M0A_R`[src]

Bits 0:31 - Memory 0 address

`impl R<u32, Reg<u32, _M1AR>>`[src]

`pub fn m1a(&self) -> M1A_R`[src]

Bits 0:31 - Memory 1 address (used in case of Double buffer mode)

`impl R<bool, FEIE_A>`[src]

`pub fn variant(&self) -> FEIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, FS_A>`[src]

`pub fn variant(&self) -> Variant<u8, FS_A>`[src]

Get enumerated values variant

`pub fn is_quarter1(&self) -> bool`[src]

Checks if the value of the field is QUARTER1

`pub fn is_quarter2(&self) -> bool`[src]

Checks if the value of the field is QUARTER2

`pub fn is_quarter3(&self) -> bool`[src]

Checks if the value of the field is QUARTER3

`pub fn is_quarter4(&self) -> bool`[src]

Checks if the value of the field is QUARTER4

`pub fn is_empty(&self) -> bool`[src]

Checks if the value of the field is EMPTY

`pub fn is_full(&self) -> bool`[src]

Checks if the value of the field is FULL

`impl R<bool, DMDIS_A>`[src]

`pub fn variant(&self) -> DMDIS_A`[src]

Get enumerated values variant

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`impl R<u8, FTH_A>`[src]

`pub fn variant(&self) -> FTH_A`[src]

Get enumerated values variant

`pub fn is_quarter(&self) -> bool`[src]

Checks if the value of the field is QUARTER

`pub fn is_half(&self) -> bool`[src]

Checks if the value of the field is HALF

`pub fn is_three_quarters(&self) -> bool`[src]

Checks if the value of the field is THREEQUARTERS

`pub fn is_full(&self) -> bool`[src]

Checks if the value of the field is FULL

`impl R<u32, Reg<u32, _FCR>>`[src]

`pub fn feie(&self) -> FEIE_R`[src]

`impl R<u32, Reg<u32, _LISR>>`[src]

`pub fn tcif3(&self) -> TCIF3_R`[src]

Bit 27 - Stream x transfer complete interrupt flag (x = 3..0)

`pub fn htif3(&self) -> HTIF3_R`[src]

Bit 26 - Stream x half transfer interrupt flag (x=3..0)

`pub fn teif3(&self) -> TEIF3_R`[src]

Bit 25 - Stream x transfer error interrupt flag (x=3..0)

`pub fn dmeif3(&self) -> DMEIF3_R`[src]

Bit 24 - Stream x direct mode error interrupt flag (x=3..0)

`pub fn feif3(&self) -> FEIF3_R`[src]

Bit 22 - Stream x FIFO error interrupt flag (x=3..0)

`pub fn tcif2(&self) -> TCIF2_R`[src]

Bit 21 - Stream x transfer complete interrupt flag (x = 3..0)

`pub fn htif2(&self) -> HTIF2_R`[src]

Bit 20 - Stream x half transfer interrupt flag (x=3..0)

`pub fn teif2(&self) -> TEIF2_R`[src]

Bit 19 - Stream x transfer error interrupt flag (x=3..0)

`pub fn dmeif2(&self) -> DMEIF2_R`[src]

Bit 18 - Stream x direct mode error interrupt flag (x=3..0)

`pub fn feif2(&self) -> FEIF2_R`[src]

Bit 16 - Stream x FIFO error interrupt flag (x=3..0)

`pub fn tcif1(&self) -> TCIF1_R`[src]

Bit 11 - Stream x transfer complete interrupt flag (x = 3..0)

`pub fn htif1(&self) -> HTIF1_R`[src]

Bit 10 - Stream x half transfer interrupt flag (x=3..0)

`pub fn teif1(&self) -> TEIF1_R`[src]

Bit 9 - Stream x transfer error interrupt flag (x=3..0)

`pub fn dmeif1(&self) -> DMEIF1_R`[src]

Bit 8 - Stream x direct mode error interrupt flag (x=3..0)

`pub fn feif1(&self) -> FEIF1_R`[src]

Bit 6 - Stream x FIFO error interrupt flag (x=3..0)

`pub fn tcif0(&self) -> TCIF0_R`[src]

Bit 5 - Stream x transfer complete interrupt flag (x = 3..0)

`pub fn htif0(&self) -> HTIF0_R`[src]

Bit 4 - Stream x half transfer interrupt flag (x=3..0)

`pub fn teif0(&self) -> TEIF0_R`[src]

Bit 3 - Stream x transfer error interrupt flag (x=3..0)

`pub fn dmeif0(&self) -> DMEIF0_R`[src]

Bit 2 - Stream x direct mode error interrupt flag (x=3..0)

`pub fn feif0(&self) -> FEIF0_R`[src]

Bit 0 - Stream x FIFO error interrupt flag (x=3..0)

`impl R<bool, TCIF7_A>`[src]

Bit 24 - Stream x direct mode error interrupt flag (x=7..4)

`pub fn feif7(&self) -> FEIF7_R`[src]

Bit 22 - Stream x FIFO error interrupt flag (x=7..4)

`pub fn tcif6(&self) -> TCIF6_R`[src]

Bit 21 - Stream x transfer complete interrupt flag (x=7..4)

`pub fn htif6(&self) -> HTIF6_R`[src]

Bit 20 - Stream x half transfer interrupt flag (x=7..4)

`pub fn teif6(&self) -> TEIF6_R`[src]

Bit 19 - Stream x transfer error interrupt flag (x=7..4)

`pub fn dmeif6(&self) -> DMEIF6_R`[src]

Bit 18 - Stream x direct mode error interrupt flag (x=7..4)

`pub fn feif6(&self) -> FEIF6_R`[src]

Bit 16 - Stream x FIFO error interrupt flag (x=7..4)

`pub fn tcif5(&self) -> TCIF5_R`[src]

Bit 11 - Stream x transfer complete interrupt flag (x=7..4)

`pub fn htif5(&self) -> HTIF5_R`[src]

Bit 10 - Stream x half transfer interrupt flag (x=7..4)

`pub fn teif5(&self) -> TEIF5_R`[src]

Bit 9 - Stream x transfer error interrupt flag (x=7..4)

`pub fn dmeif5(&self) -> DMEIF5_R`[src]

Bit 8 - Stream x direct mode error interrupt flag (x=7..4)

`pub fn feif5(&self) -> FEIF5_R`[src]

Bit 6 - Stream x FIFO error interrupt flag (x=7..4)

`pub fn tcif4(&self) -> TCIF4_R`[src]

Bit 5 - Stream x transfer complete interrupt flag (x=7..4)

`pub fn htif4(&self) -> HTIF4_R`[src]

Bit 4 - Stream x half transfer interrupt flag (x=7..4)

`pub fn teif4(&self) -> TEIF4_R`[src]

Bit 3 - Stream x transfer error interrupt flag (x=7..4)

`pub fn dmeif4(&self) -> DMEIF4_R`[src]

Bit 2 - Stream x direct mode error interrupt flag (x=7..4)

`pub fn feif4(&self) -> FEIF4_R`[src]

Bit 0 - Stream x FIFO error interrupt flag (x=7..4)

`impl R<bool, IM0_A>`[src]

`pub fn variant(&self) -> IM0_A`[src]

Get enumerated values variant

`pub fn is_masked(&self) -> bool`[src]

Checks if the value of the field is MASKED

`pub fn is_unmasked(&self) -> bool`[src]

Checks if the value of the field is UNMASKED

`impl R<u32, Reg<u32, _IMR>>`[src]

`pub fn im0(&self) -> IM0_R`[src]

Bit 0 - Interrupt Mask on line 0

`pub fn im1(&self) -> IM1_R`[src]

Bit 1 - Interrupt Mask on line 1

`pub fn im2(&self) -> IM2_R`[src]

Bit 2 - Interrupt Mask on line 2

`pub fn im3(&self) -> IM3_R`[src]

Bit 3 - Interrupt Mask on line 3

`pub fn im4(&self) -> IM4_R`[src]

Bit 4 - Interrupt Mask on line 4

`pub fn im5(&self) -> IM5_R`[src]

Bit 5 - Interrupt Mask on line 5

`pub fn im6(&self) -> IM6_R`[src]

Bit 6 - Interrupt Mask on line 6

`pub fn im7(&self) -> IM7_R`[src]

Bit 7 - Interrupt Mask on line 7

`pub fn im8(&self) -> IM8_R`[src]

Bit 8 - Interrupt Mask on line 8

`pub fn mi9(&self) -> MI9_R`[src]

Bit 9 - Interrupt Mask on line 9

`pub fn im10(&self) -> IM10_R`[src]

Bit 10 - Interrupt Mask on line 10

`pub fn im11(&self) -> IM11_R`[src]

Bit 11 - Interrupt Mask on line 11

`pub fn im12(&self) -> IM12_R`[src]

Bit 12 - Interrupt Mask on line 12

`pub fn im13(&self) -> IM13_R`[src]

Bit 13 - Interrupt Mask on line 13

`pub fn im14(&self) -> IM14_R`[src]

Bit 14 - Interrupt Mask on line 14

`pub fn im15(&self) -> IM15_R`[src]

Bit 15 - Interrupt Mask on line 15

`pub fn im16(&self) -> IM16_R`[src]

Bit 16 - Interrupt Mask on line 16

`pub fn im17(&self) -> IM17_R`[src]

Bit 17 - Interrupt Mask on line 17

`pub fn im18(&self) -> IM18_R`[src]

Bit 18 - Interrupt Mask on line 18

`pub fn im19(&self) -> IM19_R`[src]

Bit 19 - Interrupt Mask on line 19

`pub fn im20(&self) -> IM20_R`[src]

Bit 20 - Interrupt Mask on line 20

`pub fn im21(&self) -> IM21_R`[src]

Bit 21 - Interrupt Mask on line 21

`pub fn im22(&self) -> IM22_R`[src]

Bit 22 - Interrupt Mask on line 22

`pub fn im23(&self) -> IM23_R`[src]

Bit 23 - Interrupt Mask on line 23

`impl R<bool, EM0_A>`[src]

`pub fn variant(&self) -> EM0_A`[src]

Get enumerated values variant

`pub fn is_masked(&self) -> bool`[src]

Checks if the value of the field is MASKED

`pub fn is_unmasked(&self) -> bool`[src]

Checks if the value of the field is UNMASKED

`impl R<u32, Reg<u32, _EMR>>`[src]

`pub fn em0(&self) -> EM0_R`[src]

Bit 0 - Event Mask on line 0

`pub fn em1(&self) -> EM1_R`[src]

Bit 1 - Event Mask on line 1

`pub fn em2(&self) -> EM2_R`[src]

Bit 2 - Event Mask on line 2

`pub fn em3(&self) -> EM3_R`[src]

Bit 3 - Event Mask on line 3

`pub fn em4(&self) -> EM4_R`[src]

Bit 4 - Event Mask on line 4

`pub fn em5(&self) -> EM5_R`[src]

Bit 5 - Event Mask on line 5

`pub fn em6(&self) -> EM6_R`[src]

Bit 6 - Event Mask on line 6

`pub fn em7(&self) -> EM7_R`[src]

Bit 7 - Event Mask on line 7

`pub fn em8(&self) -> EM8_R`[src]

Bit 8 - Event Mask on line 8

`pub fn em9(&self) -> EM9_R`[src]

Bit 9 - Event Mask on line 9

`pub fn em10(&self) -> EM10_R`[src]

Bit 10 - Event Mask on line 10

`pub fn em11(&self) -> EM11_R`[src]

Bit 11 - Event Mask on line 11

`pub fn em12(&self) -> EM12_R`[src]

Bit 12 - Event Mask on line 12

`pub fn em13(&self) -> EM13_R`[src]

Bit 13 - Event Mask on line 13

`pub fn em14(&self) -> EM14_R`[src]

Bit 14 - Event Mask on line 14

`pub fn em15(&self) -> EM15_R`[src]

Bit 15 - Event Mask on line 15

`pub fn em16(&self) -> EM16_R`[src]

Bit 16 - Event Mask on line 16

`pub fn em17(&self) -> EM17_R`[src]

Bit 17 - Event Mask on line 17

`pub fn em18(&self) -> EM18_R`[src]

Bit 18 - Event Mask on line 18

`pub fn em19(&self) -> EM19_R`[src]

Bit 19 - Event Mask on line 19

`pub fn em20(&self) -> EM20_R`[src]

Bit 20 - Event Mask on line 20

`pub fn em21(&self) -> EM21_R`[src]

Bit 21 - Event Mask on line 21

`pub fn em22(&self) -> EM22_R`[src]

Bit 22 - Event Mask on line 22

`pub fn em23(&self) -> EM23_R`[src]

Bit 23 - Event Mask on line 23

`impl R<bool, TR0_A>`[src]

`pub fn variant(&self) -> TR0_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _RTSR>>`[src]

`pub fn tr0(&self) -> TR0_R`[src]

Bit 0 - Rising trigger event configuration of line 0

`pub fn tr1(&self) -> TR1_R`[src]

Bit 1 - Rising trigger event configuration of line 1

`pub fn tr2(&self) -> TR2_R`[src]

Bit 2 - Rising trigger event configuration of line 2

`pub fn tr3(&self) -> TR3_R`[src]

Bit 3 - Rising trigger event configuration of line 3

`pub fn tr4(&self) -> TR4_R`[src]

Bit 4 - Rising trigger event configuration of line 4

`pub fn tr5(&self) -> TR5_R`[src]

Bit 5 - Rising trigger event configuration of line 5

`pub fn tr6(&self) -> TR6_R`[src]

Bit 6 - Rising trigger event configuration of line 6

`pub fn tr7(&self) -> TR7_R`[src]

Bit 7 - Rising trigger event configuration of line 7

`pub fn tr8(&self) -> TR8_R`[src]

Bit 8 - Rising trigger event configuration of line 8

`pub fn tr9(&self) -> TR9_R`[src]

Bit 9 - Rising trigger event configuration of line 9

`pub fn tr10(&self) -> TR10_R`[src]

Bit 10 - Rising trigger event configuration of line 10

`pub fn tr11(&self) -> TR11_R`[src]

Bit 11 - Rising trigger event configuration of line 11

`pub fn tr12(&self) -> TR12_R`[src]

Bit 12 - Rising trigger event configuration of line 12

`pub fn tr13(&self) -> TR13_R`[src]

Bit 13 - Rising trigger event configuration of line 13

`pub fn tr14(&self) -> TR14_R`[src]

Bit 14 - Rising trigger event configuration of line 14

`pub fn tr15(&self) -> TR15_R`[src]

Bit 15 - Rising trigger event configuration of line 15

`pub fn tr16(&self) -> TR16_R`[src]

Bit 16 - Rising trigger event configuration of line 16

`pub fn tr17(&self) -> TR17_R`[src]

Bit 17 - Rising trigger event configuration of line 17

`pub fn tr18(&self) -> TR18_R`[src]

Bit 18 - Rising trigger event configuration of line 18

`pub fn tr19(&self) -> TR19_R`[src]

Bit 19 - Rising trigger event configuration of line 19

`pub fn tr20(&self) -> TR20_R`[src]

Bit 20 - Rising trigger event configuration of line 20

`pub fn tr21(&self) -> TR21_R`[src]

Bit 21 - Rising trigger event configuration of line 21

`pub fn tr22(&self) -> TR22_R`[src]

Bit 22 - Rising trigger event configuration of line 22

`pub fn tr23(&self) -> TR23_R`[src]

Bit 23 - Rising trigger event configuration of line 23

`impl R<bool, TR0_A>`[src]

`pub fn variant(&self) -> TR0_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _FTSR>>`[src]

`pub fn tr0(&self) -> TR0_R`[src]

Bit 0 - Falling trigger event configuration of line 0

`pub fn tr1(&self) -> TR1_R`[src]

Bit 1 - Falling trigger event configuration of line 1

`pub fn tr2(&self) -> TR2_R`[src]

Bit 2 - Falling trigger event configuration of line 2

`pub fn tr3(&self) -> TR3_R`[src]

Bit 3 - Falling trigger event configuration of line 3

`pub fn tr4(&self) -> TR4_R`[src]

Bit 4 - Falling trigger event configuration of line 4

`pub fn tr5(&self) -> TR5_R`[src]

Bit 5 - Falling trigger event configuration of line 5

`pub fn tr6(&self) -> TR6_R`[src]

Bit 6 - Falling trigger event configuration of line 6

`pub fn tr7(&self) -> TR7_R`[src]

Bit 7 - Falling trigger event configuration of line 7

`pub fn tr8(&self) -> TR8_R`[src]

Bit 8 - Falling trigger event configuration of line 8

`pub fn tr9(&self) -> TR9_R`[src]

Bit 9 - Falling trigger event configuration of line 9

`pub fn tr10(&self) -> TR10_R`[src]

Bit 10 - Falling trigger event configuration of line 10

`pub fn tr11(&self) -> TR11_R`[src]

Bit 11 - Falling trigger event configuration of line 11

`pub fn tr12(&self) -> TR12_R`[src]

Bit 12 - Falling trigger event configuration of line 12

`pub fn tr13(&self) -> TR13_R`[src]

Bit 13 - Falling trigger event configuration of line 13

`pub fn tr14(&self) -> TR14_R`[src]

Bit 14 - Falling trigger event configuration of line 14

`pub fn tr15(&self) -> TR15_R`[src]

Bit 15 - Falling trigger event configuration of line 15

`pub fn tr16(&self) -> TR16_R`[src]

Bit 16 - Falling trigger event configuration of line 16

`pub fn tr17(&self) -> TR17_R`[src]

Bit 17 - Falling trigger event configuration of line 17

`pub fn tr18(&self) -> TR18_R`[src]

Bit 18 - Falling trigger event configuration of line 18

`pub fn tr19(&self) -> TR19_R`[src]

Bit 19 - Falling trigger event configuration of line 19

`pub fn tr20(&self) -> TR20_R`[src]

Bit 20 - Falling trigger event configuration of line 20

`pub fn tr21(&self) -> TR21_R`[src]

Bit 21 - Falling trigger event configuration of line 21

`pub fn tr22(&self) -> TR22_R`[src]

Bit 22 - Falling trigger event configuration of line 22

`pub fn tr23(&self) -> TR23_R`[src]

Bit 23 - Falling trigger event configuration of line 23

`impl R<bool, SWIER0_A>`[src]

`pub fn variant(&self) -> Variant<bool, SWIER0_A>`[src]

Get enumerated values variant

`pub fn is_pend(&self) -> bool`[src]

Checks if the value of the field is PEND

`impl R<u32, Reg<u32, _SWIER>>`[src]

`pub fn swier0(&self) -> SWIER0_R`[src]

Bit 0 - Software Interrupt on line 0

`pub fn swier1(&self) -> SWIER1_R`[src]

Bit 1 - Software Interrupt on line 1

`pub fn swier2(&self) -> SWIER2_R`[src]

Bit 2 - Software Interrupt on line 2

`pub fn swier3(&self) -> SWIER3_R`[src]

Bit 3 - Software Interrupt on line 3

`pub fn swier4(&self) -> SWIER4_R`[src]

Bit 4 - Software Interrupt on line 4

`pub fn swier5(&self) -> SWIER5_R`[src]

Bit 5 - Software Interrupt on line 5

`pub fn swier6(&self) -> SWIER6_R`[src]

Bit 6 - Software Interrupt on line 6

`pub fn swier7(&self) -> SWIER7_R`[src]

Bit 7 - Software Interrupt on line 7

`pub fn swier8(&self) -> SWIER8_R`[src]

Bit 8 - Software Interrupt on line 8

`pub fn swier9(&self) -> SWIER9_R`[src]

Bit 9 - Software Interrupt on line 9

`pub fn swier10(&self) -> SWIER10_R`[src]

Bit 10 - Software Interrupt on line 10

`pub fn swier11(&self) -> SWIER11_R`[src]

Bit 11 - Software Interrupt on line 11

`pub fn swier12(&self) -> SWIER12_R`[src]

Bit 12 - Software Interrupt on line 12

`pub fn swier13(&self) -> SWIER13_R`[src]

Bit 13 - Software Interrupt on line 13

`pub fn swier14(&self) -> SWIER14_R`[src]

Bit 14 - Software Interrupt on line 14

`pub fn swier15(&self) -> SWIER15_R`[src]

Bit 15 - Software Interrupt on line 15

`pub fn swier16(&self) -> SWIER16_R`[src]

Bit 16 - Software Interrupt on line 16

`pub fn swier17(&self) -> SWIER17_R`[src]

Bit 17 - Software Interrupt on line 17

`pub fn swier18(&self) -> SWIER18_R`[src]

Bit 18 - Software Interrupt on line 18

`pub fn swier19(&self) -> SWIER19_R`[src]

Bit 19 - Software Interrupt on line 19

`pub fn swier20(&self) -> SWIER20_R`[src]

Bit 20 - Software Interrupt on line 20

`pub fn swier21(&self) -> SWIER21_R`[src]

Bit 21 - Software Interrupt on line 21

`pub fn swier22(&self) -> SWIER22_R`[src]

Bit 22 - Software Interrupt on line 22

`pub fn swier23(&self) -> SWIER23_R`[src]

Bit 23 - Software Interrupt on line 22

`impl R<bool, PR0_A>`[src]

`pub fn variant(&self) -> PR0_A`[src]

Get enumerated values variant

`pub fn is_not_pending(&self) -> bool`[src]

Checks if the value of the field is NOTPENDING

`pub fn is_pending(&self) -> bool`[src]

Checks if the value of the field is PENDING

`impl R<u32, Reg<u32, _PR>>`[src]

`pub fn pr0(&self) -> PR0_R`[src]

Bit 0 - Pending bit 0

`pub fn pr1(&self) -> PR1_R`[src]

Bit 1 - Pending bit 1

`pub fn pr2(&self) -> PR2_R`[src]

Bit 2 - Pending bit 2

`pub fn pr3(&self) -> PR3_R`[src]

Bit 3 - Pending bit 3

`pub fn pr4(&self) -> PR4_R`[src]

Bit 4 - Pending bit 4

`pub fn pr5(&self) -> PR5_R`[src]

Bit 5 - Pending bit 5

`pub fn pr6(&self) -> PR6_R`[src]

Bit 6 - Pending bit 6

`pub fn pr7(&self) -> PR7_R`[src]

Bit 7 - Pending bit 7

`pub fn pr8(&self) -> PR8_R`[src]

Bit 8 - Pending bit 8

`pub fn pr9(&self) -> PR9_R`[src]

Bit 9 - Pending bit 9

`pub fn pr10(&self) -> PR10_R`[src]

Bit 10 - Pending bit 10

`pub fn pr11(&self) -> PR11_R`[src]

Bit 11 - Pending bit 11

`pub fn pr12(&self) -> PR12_R`[src]

Bit 12 - Pending bit 12

`pub fn pr13(&self) -> PR13_R`[src]

Bit 13 - Pending bit 13

`pub fn pr14(&self) -> PR14_R`[src]

Bit 14 - Pending bit 14

`pub fn pr15(&self) -> PR15_R`[src]

Bit 15 - Pending bit 15

`pub fn pr16(&self) -> PR16_R`[src]

Bit 16 - Pending bit 16

`pub fn pr17(&self) -> PR17_R`[src]

Bit 17 - Pending bit 17

`pub fn pr18(&self) -> PR18_R`[src]

Bit 18 - Pending bit 18

`pub fn pr19(&self) -> PR19_R`[src]

Bit 19 - Pending bit 19

`pub fn pr20(&self) -> PR20_R`[src]

Bit 20 - Pending bit 20

`pub fn pr21(&self) -> PR21_R`[src]

Bit 21 - Pending bit 21

`pub fn pr22(&self) -> PR22_R`[src]

Bit 22 - Pending bit 22

`pub fn pr23(&self) -> PR23_R`[src]

Bit 23 - Pending bit 23

`impl R<u8, LATENCY_A>`[src]

`pub fn variant(&self) -> LATENCY_A`[src]

Get enumerated values variant

`pub fn is_ws0(&self) -> bool`[src]

Checks if the value of the field is WS0

`pub fn is_ws1(&self) -> bool`[src]

Checks if the value of the field is WS1

`pub fn is_ws2(&self) -> bool`[src]

Checks if the value of the field is WS2

`pub fn is_ws3(&self) -> bool`[src]

Checks if the value of the field is WS3

`pub fn is_ws4(&self) -> bool`[src]

Checks if the value of the field is WS4

`pub fn is_ws5(&self) -> bool`[src]

Checks if the value of the field is WS5

`pub fn is_ws6(&self) -> bool`[src]

Checks if the value of the field is WS6

`pub fn is_ws7(&self) -> bool`[src]

Checks if the value of the field is WS7

`pub fn is_ws8(&self) -> bool`[src]

Checks if the value of the field is WS8

`pub fn is_ws9(&self) -> bool`[src]

Checks if the value of the field is WS9

`pub fn is_ws10(&self) -> bool`[src]

Checks if the value of the field is WS10

`pub fn is_ws11(&self) -> bool`[src]

Checks if the value of the field is WS11

`pub fn is_ws12(&self) -> bool`[src]

Checks if the value of the field is WS12

`pub fn is_ws13(&self) -> bool`[src]

Checks if the value of the field is WS13

`pub fn is_ws14(&self) -> bool`[src]

Checks if the value of the field is WS14

`pub fn is_ws15(&self) -> bool`[src]

Checks if the value of the field is WS15

`impl R<bool, PRFTEN_A>`[src]

`pub fn variant(&self) -> PRFTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, ARTEN_A>`[src]

`pub fn variant(&self) -> ARTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, ARTRST_A>`[src]

`pub fn variant(&self) -> ARTRST_A`[src]

Get enumerated values variant

`pub fn is_not_reset(&self) -> bool`[src]

Checks if the value of the field is NOTRESET

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _ACR>>`[src]

`pub fn latency(&self) -> LATENCY_R`[src]

Bits 0:3 - Latency

`pub fn prften(&self) -> PRFTEN_R`[src]

Bit 8 - Prefetch enable

`pub fn arten(&self) -> ARTEN_R`[src]

Bit 9 - ART Accelerator Enable

`pub fn artrst(&self) -> ARTRST_R`[src]

Bit 11 - ART Accelerator reset

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn eop(&self) -> EOP_R`[src]

Bit 0 - End of operation

`pub fn operr(&self) -> OPERR_R`[src]

Bit 1 - Operation error

`pub fn wrperr(&self) -> WRPERR_R`[src]

Bit 4 - Write protection error

`pub fn pgaerr(&self) -> PGAERR_R`[src]

Bit 5 - Programming alignment error

`pub fn pgperr(&self) -> PGPERR_R`[src]

Bit 6 - Programming parallelism error

`pub fn erserr(&self) -> ERSERR_R`[src]

Bit 7 - Erase Sequence Error

`pub fn bsy(&self) -> BSY_R`[src]

Bit 16 - Busy

`pub fn rderr(&self) -> RDERR_R`[src]

Bit 8 - RDERR

`impl R<bool, PG_A>`[src]

`pub fn variant(&self) -> Variant<bool, PG_A>`[src]

Get enumerated values variant

`pub fn is_program(&self) -> bool`[src]

Checks if the value of the field is PROGRAM

`impl R<bool, SER_A>`[src]

`pub fn variant(&self) -> Variant<bool, SER_A>`[src]

Get enumerated values variant

`pub fn is_sector_erase(&self) -> bool`[src]

Checks if the value of the field is SECTORERASE

`impl R<bool, MER_A>`[src]

`pub fn variant(&self) -> Variant<bool, MER_A>`[src]

Get enumerated values variant

`pub fn is_mass_erase(&self) -> bool`[src]

Checks if the value of the field is MASSERASE

`impl R<u8, PSIZE_A>`[src]

`pub fn variant(&self) -> PSIZE_A`[src]

Get enumerated values variant

`pub fn is_psize8(&self) -> bool`[src]

Checks if the value of the field is PSIZE8

`pub fn is_psize16(&self) -> bool`[src]

Checks if the value of the field is PSIZE16

`pub fn is_psize32(&self) -> bool`[src]

Checks if the value of the field is PSIZE32

`pub fn is_psize64(&self) -> bool`[src]

Checks if the value of the field is PSIZE64

Bit 0 - Programming

`pub fn ser(&self) -> SER_R`[src]

Bit 1 - Sector Erase

`pub fn mer(&self) -> MER_R`[src]

Bit 2 - Mass Erase of sectors 0 to 11

`pub fn snb(&self) -> SNB_R`[src]

Bits 3:6 - Sector number

`pub fn psize(&self) -> PSIZE_R`[src]

Bits 8:9 - Program size

`pub fn strt(&self) -> STRT_R`[src]

Bit 16 - Start

`pub fn eopie(&self) -> EOPIE_R`[src]

Bit 24 - End of operation interrupt enable

`pub fn errie(&self) -> ERRIE_R`[src]

Bit 25 - Error interrupt enable

`pub fn lock(&self) -> LOCK_R`[src]

Bit 31 - Lock

`pub fn rderrie(&self) -> RDERRIE_R`[src]

Bit 26 - PCROP error interrupt enable

`impl R<u32, Reg<u32, _OPTCR>>`[src]

`pub fn optlock(&self) -> OPTLOCK_R`[src]

Bit 0 - Option lock

`pub fn optstrt(&self) -> OPTSTRT_R`[src]

Bit 1 - Option start

`pub fn bor_lev(&self) -> BOR_LEV_R`[src]

Bits 2:3 - BOR reset Level

`pub fn iwdg_sw(&self) -> IWDG_SW_R`[src]

Bit 5 - WDG_SW User option bytes

`pub fn n_rst_stop(&self) -> NRST_STOP_R`[src]

Bit 6 - nRST_STOP User option bytes

`pub fn n_rst_stdby(&self) -> NRST_STDBY_R`[src]

Bit 7 - nRST_STDBY User option bytes

`pub fn rdp(&self) -> RDP_R`[src]

Bits 8:15 - Read protect

`pub fn n_wrp(&self) -> NWRP_R`[src]

Bits 16:23 - Not write protect

`pub fn wwdg_sw(&self) -> WWDG_SW_R`[src]

Bit 4 - User option bytes

`pub fn iwdg_stop(&self) -> IWDG_STOP_R`[src]

Bit 31 - Independent watchdog counter freeze in Stop mode

`pub fn iwdg_stdby(&self) -> IWDG_STDBY_R`[src]

Bit 30 - Independent watchdog counter freeze in standby mode

`impl R<u32, Reg<u32, _OPTCR1>>`[src]

`pub fn boot_add1(&self) -> BOOT_ADD1_R`[src]

Bits 16:31 - Boot base address when Boot pin =1

`pub fn boot_add0(&self) -> BOOT_ADD0_R`[src]

Bits 0:15 - Boot base address when Boot pin =0

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, MWID_A>`[src]

`pub fn variant(&self) -> Variant<u8, MWID_A>`[src]

Get enumerated values variant

`pub fn is_bits8(&self) -> bool`[src]

Checks if the value of the field is BITS8

`pub fn is_bits16(&self) -> bool`[src]

Checks if the value of the field is BITS16

`pub fn is_bits32(&self) -> bool`[src]

Checks if the value of the field is BITS32

`impl R<u8, MTYP_A>`[src]

`pub fn variant(&self) -> Variant<u8, MTYP_A>`[src]

`pub fn is_bytes256(&self) -> bool`[src]

Checks if the value of the field is BYTES256

`pub fn is_bytes512(&self) -> bool`[src]

Checks if the value of the field is BYTES512

`pub fn is_bytes1024(&self) -> bool`[src]

Checks if the value of the field is BYTES1024

`impl R<u32, Reg<u32, _BCR1>>`[src]

`pub fn cclken(&self) -> CCLKEN_R`[src]

Bit 20 - CCLKEN

`pub fn cburstrw(&self) -> CBURSTRW_R`[src]

Bit 19 - CBURSTRW

`pub fn asyncwait(&self) -> ASYNCWAIT_R`[src]

Bit 15 - ASYNCWAIT

`pub fn extmod(&self) -> EXTMOD_R`[src]

Bit 14 - EXTMOD

`pub fn waiten(&self) -> WAITEN_R`[src]

Bit 13 - WAITEN

`pub fn wren(&self) -> WREN_R`[src]

Bit 12 - WREN

`pub fn waitcfg(&self) -> WAITCFG_R`[src]

Bit 11 - WAITCFG

`pub fn waitpol(&self) -> WAITPOL_R`[src]

Bit 9 - WAITPOL

`pub fn bursten(&self) -> BURSTEN_R`[src]

Bit 8 - BURSTEN

`pub fn faccen(&self) -> FACCEN_R`[src]

Bit 6 - FACCEN

`pub fn mwid(&self) -> MWID_R`[src]

Bits 4:5 - MWID

`pub fn mtyp(&self) -> MTYP_R`[src]

Bits 2:3 - MTYP

`pub fn muxen(&self) -> MUXEN_R`[src]

Bit 1 - MUXEN

`pub fn mbken(&self) -> MBKEN_R`[src]

Bit 0 - MBKEN

`pub fn wfdis(&self) -> WFDIS_R`[src]

Bit 21 - Write FIFO Disable

`pub fn cpsize(&self) -> CPSIZE_R`[src]

Bits 16:18 - CRAM page size

`impl R<u8, ACCMOD_A>`[src]

`pub fn variant(&self) -> ACCMOD_A`[src]

Get enumerated values variant

`pub fn is_a(&self) -> bool`[src]

Checks if the value of the field is A

`pub fn is_b(&self) -> bool`[src]

Checks if the value of the field is B

`pub fn is_c(&self) -> bool`[src]

Checks if the value of the field is C

`pub fn is_d(&self) -> bool`[src]

Checks if the value of the field is D

`impl R<u32, Reg<u32, _BTR>>`[src]

`pub fn accmod(&self) -> ACCMOD_R`[src]

Bits 28:29 - ACCMOD

`pub fn datlat(&self) -> DATLAT_R`[src]

Bits 24:27 - DATLAT

`pub fn clkdiv(&self) -> CLKDIV_R`[src]

Bits 20:23 - CLKDIV

`pub fn busturn(&self) -> BUSTURN_R`[src]

`impl R<u8, MWID_A>`[src]

`pub fn variant(&self) -> Variant<u8, MWID_A>`[src]

Get enumerated values variant

`pub fn is_bits8(&self) -> bool`[src]

Checks if the value of the field is BITS8

`pub fn is_bits16(&self) -> bool`[src]

Checks if the value of the field is BITS16

`pub fn is_bits32(&self) -> bool`[src]

Checks if the value of the field is BITS32

`impl R<u8, MTYP_A>`[src]

`pub fn variant(&self) -> Variant<u8, MTYP_A>`[src]

`pub fn is_bytes256(&self) -> bool`[src]

Checks if the value of the field is BYTES256

`pub fn is_bytes512(&self) -> bool`[src]

Checks if the value of the field is BYTES512

`pub fn is_bytes1024(&self) -> bool`[src]

Checks if the value of the field is BYTES1024

`impl R<u32, Reg<u32, _BCR>>`[src]

`pub fn cburstrw(&self) -> CBURSTRW_R`[src]

Bit 19 - CBURSTRW

`pub fn asyncwait(&self) -> ASYNCWAIT_R`[src]

Bit 15 - ASYNCWAIT

`pub fn extmod(&self) -> EXTMOD_R`[src]

Bit 14 - EXTMOD

`pub fn waiten(&self) -> WAITEN_R`[src]

Bit 13 - WAITEN

`pub fn wren(&self) -> WREN_R`[src]

Bit 12 - WREN

`pub fn waitcfg(&self) -> WAITCFG_R`[src]

Bit 11 - WAITCFG

`pub fn waitpol(&self) -> WAITPOL_R`[src]

Bit 9 - WAITPOL

`pub fn bursten(&self) -> BURSTEN_R`[src]

Bit 8 - BURSTEN

`pub fn faccen(&self) -> FACCEN_R`[src]

Bit 6 - FACCEN

`pub fn mwid(&self) -> MWID_R`[src]

Bits 4:5 - MWID

`pub fn mtyp(&self) -> MTYP_R`[src]

Bits 2:3 - MTYP

`pub fn muxen(&self) -> MUXEN_R`[src]

Bit 1 - MUXEN

`pub fn mbken(&self) -> MBKEN_R`[src]

Bit 0 - MBKEN

`pub fn cpsize(&self) -> CPSIZE_R`[src]

Bits 16:18 - CRAM page size

`impl R<u8, ECCPS_A>`[src]

`pub fn variant(&self) -> Variant<u8, ECCPS_A>`[src]

Get enumerated values variant

`pub fn is_bytes256(&self) -> bool`[src]

Checks if the value of the field is BYTES256

`pub fn is_bytes512(&self) -> bool`[src]

Checks if the value of the field is BYTES512

`pub fn is_bytes1024(&self) -> bool`[src]

Checks if the value of the field is BYTES1024

`pub fn is_bytes2048(&self) -> bool`[src]

Checks if the value of the field is BYTES2048

`pub fn is_bytes4096(&self) -> bool`[src]

Checks if the value of the field is BYTES4096

`pub fn is_bytes8192(&self) -> bool`[src]

Checks if the value of the field is BYTES8192

`impl R<bool, ECCEN_A>`[src]

`pub fn variant(&self) -> ECCEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, PWID_A>`[src]

`pub fn variant(&self) -> Variant<u8, PWID_A>`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, PWAITEN_A>`[src]

`pub fn variant(&self) -> PWAITEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _PCR>>`[src]

`pub fn eccps(&self) -> ECCPS_R`[src]

Bits 17:19 - ECCPS

`pub fn tar(&self) -> TAR_R`[src]

Bits 13:16 - TAR

`pub fn tclr(&self) -> TCLR_R`[src]

Bits 9:12 - TCLR

`pub fn eccen(&self) -> ECCEN_R`[src]

Bit 6 - ECCEN

`pub fn pwid(&self) -> PWID_R`[src]

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn fempt(&self) -> FEMPT_R`[src]

Bit 6 - FEMPT

`pub fn ifen(&self) -> IFEN_R`[src]

Bit 5 - IFEN

`pub fn ilen(&self) -> ILEN_R`[src]

Bit 4 - ILEN

`pub fn iren(&self) -> IREN_R`[src]

Bit 3 - IREN

`pub fn ifs(&self) -> IFS_R`[src]

Bit 2 - IFS

`pub fn ils(&self) -> ILS_R`[src]

Bit 1 - ILS

`pub fn irs(&self) -> IRS_R`[src]

Bit 0 - IRS

`impl R<u32, Reg<u32, _PMEM>>`[src]

`pub fn memhiz(&self) -> MEMHIZ_R`[src]

Bits 24:31 - MEMHIZx

`pub fn memhold(&self) -> MEMHOLD_R`[src]

Bits 16:23 - MEMHOLDx

`pub fn memwait(&self) -> MEMWAIT_R`[src]

Bits 8:15 - MEMWAITx

`pub fn memset(&self) -> MEMSET_R`[src]

Bits 0:7 - MEMSETx

`impl R<u32, Reg<u32, _PATT>>`[src]

`pub fn atthiz(&self) -> ATTHIZ_R`[src]

Bits 24:31 - ATTHIZx

`pub fn atthold(&self) -> ATTHOLD_R`[src]

Bits 16:23 - ATTHOLDx

`pub fn attwait(&self) -> ATTWAIT_R`[src]

Bits 8:15 - ATTWAITx

`pub fn attset(&self) -> ATTSET_R`[src]

Bits 0:7 - ATTSETx

`impl R<u32, Reg<u32, _ECCR>>`[src]

`pub fn ecc(&self) -> ECC_R`[src]

Bits 0:31 - ECCx

`impl R<u8, ACCMOD_A>`[src]

`pub fn variant(&self) -> ACCMOD_A`[src]

Get enumerated values variant

`pub fn is_a(&self) -> bool`[src]

Checks if the value of the field is A

`pub fn is_b(&self) -> bool`[src]

Checks if the value of the field is B

`pub fn is_c(&self) -> bool`[src]

Checks if the value of the field is C

`pub fn is_d(&self) -> bool`[src]

Checks if the value of the field is D

`impl R<u32, Reg<u32, _BWTR>>`[src]

`pub fn accmod(&self) -> ACCMOD_R`[src]

Bits 28:29 - ACCMOD

`pub fn datast(&self) -> DATAST_R`[src]

Bits 8:15 - DATAST

`pub fn addhld(&self) -> ADDHLD_R`[src]

Bits 4:7 - ADDHLD

`pub fn addset(&self) -> ADDSET_R`[src]

Bits 0:3 - ADDSET

`pub fn busturn(&self) -> BUSTURN_R`[src]

Bits 16:19 - Bus turnaround phase duration

`impl R<u8, NC_A>`[src]

`pub fn variant(&self) -> NC_A`[src]

`pub fn is_clocks3(&self) -> bool`[src]

Checks if the value of the field is CLOCKS3

`impl R<bool, WP_A>`[src]

`pub fn variant(&self) -> WP_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, SDCLK_A>`[src]

`pub fn variant(&self) -> Variant<u8, SDCLK_A>`[src]

`pub fn is_clocks2(&self) -> bool`[src]

Checks if the value of the field is CLOCKS2

`impl R<u32, Reg<u32, _SDCR>>`[src]

`pub fn nc(&self) -> NC_R`[src]

Bits 0:1 - Number of column address bits

`pub fn nr(&self) -> NR_R`[src]

Bits 2:3 - Number of row address bits

`pub fn mwid(&self) -> MWID_R`[src]

Bits 4:5 - Memory data bus width

`pub fn nb(&self) -> NB_R`[src]

Bit 6 - Number of internal banks

`pub fn cas(&self) -> CAS_R`[src]

Bits 7:8 - CAS latency

`pub fn wp(&self) -> WP_R`[src]

Bit 9 - Write protection

`pub fn sdclk(&self) -> SDCLK_R`[src]

Bits 10:11 - SDRAM clock configuration

`pub fn rburst(&self) -> RBURST_R`[src]

Bit 12 - Burst read

`pub fn rpipe(&self) -> RPIPE_R`[src]

Bits 13:14 - Read pipe

`impl R<u32, Reg<u32, _SDTR>>`[src]

`pub fn tmrd(&self) -> TMRD_R`[src]

Bits 0:3 - Load Mode Register to Active

`pub fn txsr(&self) -> TXSR_R`[src]

Bits 4:7 - Exit self-refresh delay

`pub fn tras(&self) -> TRAS_R`[src]

Bits 8:11 - Self refresh time

`pub fn trc(&self) -> TRC_R`[src]

Bits 12:15 - Row cycle delay

`pub fn twr(&self) -> TWR_R`[src]

Bits 16:19 - Recovery delay

`pub fn trp(&self) -> TRP_R`[src]

Bits 20:23 - Row precharge delay

`pub fn trcd(&self) -> TRCD_R`[src]

Bits 24:27 - Row to column delay

`impl R<u32, Reg<u32, _SDCMR>>`[src]

`pub fn nrfs(&self) -> NRFS_R`[src]

Bits 5:8 - Number of Auto-refresh

`pub fn mrd(&self) -> MRD_R`[src]

Bits 9:21 - Mode Register definition

`impl R<bool, REIE_A>`[src]

`pub fn variant(&self) -> REIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _SDRTR>>`[src]

`pub fn count(&self) -> COUNT_R`[src]

Bits 1:13 - Refresh Timer Count

`pub fn reie(&self) -> REIE_R`[src]

Bit 14 - RES Interrupt Enable

`impl R<u8, MODES1_A>`[src]

`pub fn variant(&self) -> Variant<u8, MODES1_A>`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_self_refresh(&self) -> bool`[src]

Checks if the value of the field is SELFREFRESH

`pub fn is_power_down(&self) -> bool`[src]

Checks if the value of the field is POWERDOWN

`impl R<bool, BUSY_A>`[src]

`pub fn variant(&self) -> BUSY_A`[src]

Get enumerated values variant

`pub fn is_not_busy(&self) -> bool`[src]

Checks if the value of the field is NOTBUSY

`pub fn is_busy(&self) -> bool`[src]

Checks if the value of the field is BUSY

`impl R<bool, RE_A>`[src]

`pub fn variant(&self) -> RE_A`[src]

Get enumerated values variant

`pub fn is_no_error(&self) -> bool`[src]

Checks if the value of the field is NOERROR

`pub fn is_error(&self) -> bool`[src]

Checks if the value of the field is ERROR

`impl R<u32, Reg<u32, _SDSR>>`[src]

`pub fn modes1(&self) -> MODES1_R`[src]

Bits 1:2 - Status Mode for Bank 1

`pub fn modes2(&self) -> MODES2_R`[src]

Bits 3:4 - Status Mode for Bank 2

`pub fn busy(&self) -> BUSY_R`[src]

Bit 5 - Busy status

`pub fn re(&self) -> RE_R`[src]

Bit 0 - Refresh error flag

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&self) -> CKD_R`[src]

Bits 8:9 - Clock division

`pub fn arpe(&self) -> ARPE_R`[src]

Bit 7 - Auto-reload preload enable

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn msm(&self) -> MSM_R`[src]

Bit 7 - Master/Slave mode

`pub fn ts(&self) -> TS_R`[src]

Bits 4:6 - Trigger selection

`pub fn sms(&self) -> SMS_R`[src]

Bits 0:2 - Slave mode selection

`impl R<bool, UIE_A>`[src]

`pub fn variant(&self) -> UIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _DIER>>`[src]

`pub fn tie(&self) -> TIE_R`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc2ie(&self) -> CC2IE_R`[src]

Bit 2 - Capture/Compare 2 interrupt enable

`pub fn cc1ie(&self) -> CC1IE_R`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&self) -> UIE_R`[src]

Bit 0 - Update interrupt enable

`impl R<bool, UIF_A>`[src]

`pub fn variant(&self) -> UIF_A`[src]

Get enumerated values variant

`pub fn is_clear(&self) -> bool`[src]

Checks if the value of the field is CLEAR

`pub fn is_update_pending(&self) -> bool`[src]

Checks if the value of the field is UPDATEPENDING

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn cc2of(&self) -> CC2OF_R`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn tif(&self) -> TIF_R`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc2if(&self) -> CC2IF_R`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2m(&self) -> OC2M_R`[src]

Bits 12:14 - Output Compare 2 mode

`pub fn oc2pe(&self) -> OC2PE_R`[src]

Bit 11 - Output Compare 2 preload enable

`pub fn oc2fe(&self) -> OC2FE_R`[src]

Bit 10 - Output Compare 2 fast enable

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - Output Compare 1 mode

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - Output Compare 1 preload enable

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - Output Compare 1 fast enable

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`pub fn oc2m_3(&self) -> OC2M_3_R`[src]

Bit 24 - Output Compare 2 mode - bit 3

`pub fn oc1m_3(&self) -> OC1M_3_R`[src]

Bit 16 - Output Compare 1 mode - bit 3

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&self) -> IC2F_R`[src]

Bits 12:14 - Input capture 2 filter

`pub fn ic2psc(&self) -> IC2PSC_R`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:6 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc2np(&self) -> CC2NP_R`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&self) -> CC2P_R`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&self) -> CC2E_R`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 1 value

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn arpe(&self) -> ARPE_R`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&self) -> CMS_R`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&self) -> DIR_R`[src]

Bit 4 - Direction

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`pub fn uifremap(&self) -> UIFREMAP_R`[src]

Bit 11 - UIF status bit remapping

`impl R<bool, TI1S_A>`[src]

`pub fn variant(&self) -> TI1S_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_xor(&self) -> bool`[src]

Checks if the value of the field is XOR

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> MMS_A`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`pub fn is_update(&self) -> bool`[src]

Checks if the value of the field is UPDATE

`pub fn is_compare_pulse(&self) -> bool`[src]

Checks if the value of the field is COMPAREPULSE

`pub fn is_compare_oc1(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC1

`pub fn is_compare_oc2(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC2

`pub fn is_compare_oc3(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC3

`pub fn is_compare_oc4(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC4

`impl R<bool, CCDS_A>`[src]

`pub fn variant(&self) -> CCDS_A`[src]

Get enumerated values variant

`pub fn is_on_compare(&self) -> bool`[src]

Checks if the value of the field is ONCOMPARE

`pub fn is_on_update(&self) -> bool`[src]

Checks if the value of the field is ONUPDATE

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn ti1s(&self) -> TI1S_R`[src]

Bit 7 - TI1 selection

`pub fn mms(&self) -> MMS_R`[src]

Bits 4:6 - Master mode selection

`pub fn ccds(&self) -> CCDS_R`[src]

Bit 3 - Capture/compare DMA selection

`impl R<u8, SMS_A>`[src]

`pub fn variant(&self) -> SMS_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_encoder_mode_1(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_1

`pub fn is_encoder_mode_2(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_2

`pub fn is_encoder_mode_3(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_3

`pub fn is_reset_mode(&self) -> bool`[src]

Checks if the value of the field is RESET_MODE

`pub fn is_gated_mode(&self) -> bool`[src]

Checks if the value of the field is GATED_MODE

`pub fn is_trigger_mode(&self) -> bool`[src]

Checks if the value of the field is TRIGGER_MODE

`pub fn is_ext_clock_mode(&self) -> bool`[src]

Checks if the value of the field is EXT_CLOCK_MODE

`impl R<u8, TS_A>`[src]

`pub fn variant(&self) -> Variant<u8, TS_A>`[src]

Get enumerated values variant

`pub fn is_itr0(&self) -> bool`[src]

Checks if the value of the field is ITR0

`pub fn is_itr1(&self) -> bool`[src]

Checks if the value of the field is ITR1

`pub fn is_itr2(&self) -> bool`[src]

Checks if the value of the field is ITR2

`pub fn is_ti1f_ed(&self) -> bool`[src]

Checks if the value of the field is TI1F_ED

`pub fn is_ti1fp1(&self) -> bool`[src]

Checks if the value of the field is TI1FP1

`pub fn is_ti2fp2(&self) -> bool`[src]

Checks if the value of the field is TI2FP2

`pub fn is_etrf(&self) -> bool`[src]

Checks if the value of the field is ETRF

`impl R<bool, MSM_A>`[src]

`pub fn variant(&self) -> MSM_A`[src]

Get enumerated values variant

`pub fn is_no_sync(&self) -> bool`[src]

Checks if the value of the field is NOSYNC

`pub fn is_sync(&self) -> bool`[src]

Checks if the value of the field is SYNC

`impl R<u8, ETF_A>`[src]

`pub fn variant(&self) -> ETF_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, ETPS_A>`[src]

`pub fn variant(&self) -> ETPS_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<bool, ECE_A>`[src]

`pub fn variant(&self) -> ECE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, ETP_A>`[src]

`pub fn variant(&self) -> ETP_A`[src]

Get enumerated values variant

`pub fn is_not_inverted(&self) -> bool`[src]

Checks if the value of the field is NOTINVERTED

`pub fn is_inverted(&self) -> bool`[src]

Checks if the value of the field is INVERTED

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn sms(&self) -> SMS_R`[src]

Bits 0:2 - Slave mode selection

`pub fn ts(&self) -> TS_R`[src]

Bits 4:6 - Trigger selection

`pub fn msm(&self) -> MSM_R`[src]

Bit 7 - Master/Slave mode

`pub fn etf(&self) -> ETF_R`[src]

Bits 8:11 - External trigger filter

`pub fn etps(&self) -> ETPS_R`[src]

`pub fn cc2de(&self) -> CC2DE_R`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&self) -> CC1DE_R`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&self) -> UDE_R`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&self) -> TIE_R`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&self) -> CC4IE_R`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&self) -> CC3IE_R`[src]

`pub fn cc2of(&self) -> CC2OF_R`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn tif(&self) -> TIF_R`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc4if(&self) -> CC4IF_R`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&self) -> CC3IF_R`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&self) -> CC2IF_R`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u8, OC2M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC2M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC2PE_A>`[src]

`pub fn variant(&self) -> OC2PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&self) -> OC2CE_R`[src]

Bit 15 - OC2CE

`pub fn oc2m(&self) -> OC2M_R`[src]

Bits 12:14 - OC2M

`pub fn oc2pe(&self) -> OC2PE_R`[src]

Bit 11 - OC2PE

`pub fn oc2fe(&self) -> OC2FE_R`[src]

Bit 10 - OC2FE

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - CC2S

`pub fn oc1ce(&self) -> OC1CE_R`[src]

Bit 7 - OC1CE

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - OC1M

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - OC1PE

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - OC1FE

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - CC1S

`pub fn oc2m_3(&self) -> OC2M_3_R`[src]

Bit 24 - Output Compare 2 mode - bit 3

`pub fn oc1m_3(&self) -> OC1M_3_R`[src]

Bit 16 - Output Compare 1 mode - bit 3

`impl R<u8, CC2S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC2S_A>`[src]

Get enumerated values variant

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, IC1F_A>`[src]

`pub fn variant(&self) -> IC1F_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&self) -> IC2F_R`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&self) -> IC2PSC_R`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u8, OC4M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC4M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC4PE_A>`[src]

`pub fn variant(&self) -> OC4PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&self) -> OC4CE_R`[src]

Bit 15 - O24CE

`pub fn oc4m(&self) -> OC4M_R`[src]

Bits 12:14 - OC4M

`pub fn oc4pe(&self) -> OC4PE_R`[src]

Bit 11 - OC4PE

`pub fn oc4fe(&self) -> OC4FE_R`[src]

Bit 10 - OC4FE

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - CC4S

`pub fn oc3ce(&self) -> OC3CE_R`[src]

Bit 7 - OC3CE

`pub fn oc3m(&self) -> OC3M_R`[src]

Bits 4:6 - OC3M

`pub fn oc3pe(&self) -> OC3PE_R`[src]

Bit 3 - OC3PE

`pub fn oc3fe(&self) -> OC3FE_R`[src]

Bit 2 - OC3FE

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - CC3S

`pub fn oc4m_3(&self) -> OC4M_3_R`[src]

Bit 24 - Output Compare 2 mode - bit 3

`pub fn oc3m_3(&self) -> OC3M_3_R`[src]

Bit 16 - Output Compare 1 mode - bit 3

`impl R<u8, CC4S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC4S_A>`[src]

Get enumerated values variant

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&self) -> IC4F_R`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&self) -> IC4PSC_R`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&self) -> IC3F_R`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&self) -> IC3PSC_R`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - Capture/compare 3 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4np(&self) -> CC4NP_R`[src]

Bit 15 - Capture/Compare 4 output Polarity

`pub fn cc4p(&self) -> CC4P_R`[src]

Bit 13 - Capture/Compare 3 output Polarity

`pub fn cc4e(&self) -> CC4E_R`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&self) -> CC3NP_R`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3p(&self) -> CC3P_R`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&self) -> CC3E_R`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&self) -> CC2NP_R`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&self) -> CC2P_R`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&self) -> CC2E_R`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:31 - Counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:31 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:31 - Capture/Compare 1 value

`impl R<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&self) -> DBL_R`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&self) -> DBA_R`[src]

Bits 0:4 - DMA base address

`impl R<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&self) -> DMAB_R`[src]

Bits 0:15 - DMA register for burst accesses

`impl R<u32, Reg<u32, _OR>>`[src]

`pub fn itr1_rmp(&self) -> ITR1_RMP_R`[src]

Bits 10:11 - Internal trigger 1 remap

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn arpe(&self) -> ARPE_R`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&self) -> CMS_R`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&self) -> DIR_R`[src]

Bit 4 - Direction

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`pub fn uifremap(&self) -> UIFREMAP_R`[src]

Bit 11 - UIF status bit remapping

`impl R<bool, TI1S_A>`[src]

`pub fn variant(&self) -> TI1S_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_xor(&self) -> bool`[src]

Checks if the value of the field is XOR

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> MMS_A`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`pub fn is_update(&self) -> bool`[src]

Checks if the value of the field is UPDATE

`pub fn is_compare_pulse(&self) -> bool`[src]

Checks if the value of the field is COMPAREPULSE

`pub fn is_compare_oc1(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC1

`pub fn is_compare_oc2(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC2

`pub fn is_compare_oc3(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC3

`pub fn is_compare_oc4(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC4

`impl R<bool, CCDS_A>`[src]

`pub fn variant(&self) -> CCDS_A`[src]

Get enumerated values variant

`pub fn is_on_compare(&self) -> bool`[src]

Checks if the value of the field is ONCOMPARE

`pub fn is_on_update(&self) -> bool`[src]

Checks if the value of the field is ONUPDATE

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn ti1s(&self) -> TI1S_R`[src]

Bit 7 - TI1 selection

`pub fn mms(&self) -> MMS_R`[src]

Bits 4:6 - Master mode selection

`pub fn ccds(&self) -> CCDS_R`[src]

Bit 3 - Capture/compare DMA selection

`impl R<u8, SMS_A>`[src]

`pub fn variant(&self) -> SMS_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_encoder_mode_1(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_1

`pub fn is_encoder_mode_2(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_2

`pub fn is_encoder_mode_3(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_3

`pub fn is_reset_mode(&self) -> bool`[src]

Checks if the value of the field is RESET_MODE

`pub fn is_gated_mode(&self) -> bool`[src]

Checks if the value of the field is GATED_MODE

`pub fn is_trigger_mode(&self) -> bool`[src]

Checks if the value of the field is TRIGGER_MODE

`pub fn is_ext_clock_mode(&self) -> bool`[src]

Checks if the value of the field is EXT_CLOCK_MODE

`impl R<u8, TS_A>`[src]

`pub fn variant(&self) -> Variant<u8, TS_A>`[src]

Get enumerated values variant

`pub fn is_itr0(&self) -> bool`[src]

Checks if the value of the field is ITR0

`pub fn is_itr1(&self) -> bool`[src]

Checks if the value of the field is ITR1

`pub fn is_itr2(&self) -> bool`[src]

Checks if the value of the field is ITR2

`pub fn is_ti1f_ed(&self) -> bool`[src]

Checks if the value of the field is TI1F_ED

`pub fn is_ti1fp1(&self) -> bool`[src]

Checks if the value of the field is TI1FP1

`pub fn is_ti2fp2(&self) -> bool`[src]

Checks if the value of the field is TI2FP2

`pub fn is_etrf(&self) -> bool`[src]

Checks if the value of the field is ETRF

`impl R<bool, MSM_A>`[src]

`pub fn variant(&self) -> MSM_A`[src]

Get enumerated values variant

`pub fn is_no_sync(&self) -> bool`[src]

Checks if the value of the field is NOSYNC

`pub fn is_sync(&self) -> bool`[src]

Checks if the value of the field is SYNC

`impl R<u8, ETF_A>`[src]

`pub fn variant(&self) -> ETF_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, ETPS_A>`[src]

`pub fn variant(&self) -> ETPS_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<bool, ECE_A>`[src]

`pub fn variant(&self) -> ECE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, ETP_A>`[src]

`pub fn variant(&self) -> ETP_A`[src]

Get enumerated values variant

`pub fn is_not_inverted(&self) -> bool`[src]

Checks if the value of the field is NOTINVERTED

`pub fn is_inverted(&self) -> bool`[src]

Checks if the value of the field is INVERTED

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn sms(&self) -> SMS_R`[src]

Bits 0:2 - Slave mode selection

`pub fn ts(&self) -> TS_R`[src]

Bits 4:6 - Trigger selection

`pub fn msm(&self) -> MSM_R`[src]

Bit 7 - Master/Slave mode

`pub fn etf(&self) -> ETF_R`[src]

Bits 8:11 - External trigger filter

`pub fn etps(&self) -> ETPS_R`[src]

`pub fn cc2de(&self) -> CC2DE_R`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&self) -> CC1DE_R`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&self) -> UDE_R`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&self) -> TIE_R`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&self) -> CC4IE_R`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&self) -> CC3IE_R`[src]

`pub fn cc2of(&self) -> CC2OF_R`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn tif(&self) -> TIF_R`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc4if(&self) -> CC4IF_R`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&self) -> CC3IF_R`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&self) -> CC2IF_R`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u8, OC2M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC2M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC2PE_A>`[src]

`pub fn variant(&self) -> OC2PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&self) -> OC2CE_R`[src]

Bit 15 - OC2CE

`pub fn oc2m(&self) -> OC2M_R`[src]

Bits 12:14 - OC2M

`pub fn oc2pe(&self) -> OC2PE_R`[src]

Bit 11 - OC2PE

`pub fn oc2fe(&self) -> OC2FE_R`[src]

Bit 10 - OC2FE

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - CC2S

`pub fn oc1ce(&self) -> OC1CE_R`[src]

Bit 7 - OC1CE

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - OC1M

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - OC1PE

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - OC1FE

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - CC1S

`pub fn oc2m_3(&self) -> OC2M_3_R`[src]

Bit 24 - Output Compare 2 mode - bit 3

`pub fn oc1m_3(&self) -> OC1M_3_R`[src]

Bit 16 - Output Compare 1 mode - bit 3

`impl R<u8, CC2S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC2S_A>`[src]

Get enumerated values variant

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, IC1F_A>`[src]

`pub fn variant(&self) -> IC1F_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&self) -> IC2F_R`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&self) -> IC2PSC_R`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u8, OC4M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC4M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC4PE_A>`[src]

`pub fn variant(&self) -> OC4PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&self) -> OC4CE_R`[src]

Bit 15 - O24CE

`pub fn oc4m(&self) -> OC4M_R`[src]

Bits 12:14 - OC4M

`pub fn oc4pe(&self) -> OC4PE_R`[src]

Bit 11 - OC4PE

`pub fn oc4fe(&self) -> OC4FE_R`[src]

Bit 10 - OC4FE

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - CC4S

`pub fn oc3ce(&self) -> OC3CE_R`[src]

Bit 7 - OC3CE

`pub fn oc3m(&self) -> OC3M_R`[src]

Bits 4:6 - OC3M

`pub fn oc3pe(&self) -> OC3PE_R`[src]

Bit 3 - OC3PE

`pub fn oc3fe(&self) -> OC3FE_R`[src]

Bit 2 - OC3FE

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - CC3S

`pub fn oc4m_3(&self) -> OC4M_3_R`[src]

Bit 24 - Output Compare 2 mode - bit 3

`pub fn oc3m_3(&self) -> OC3M_3_R`[src]

Bit 16 - Output Compare 1 mode - bit 3

`impl R<u8, CC4S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC4S_A>`[src]

Get enumerated values variant

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&self) -> IC4F_R`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&self) -> IC4PSC_R`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&self) -> IC3F_R`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&self) -> IC3PSC_R`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - Capture/compare 3 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4np(&self) -> CC4NP_R`[src]

Bit 15 - Capture/Compare 4 output Polarity

`pub fn cc4p(&self) -> CC4P_R`[src]

Bit 13 - Capture/Compare 3 output Polarity

`pub fn cc4e(&self) -> CC4E_R`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&self) -> CC3NP_R`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3p(&self) -> CC3P_R`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&self) -> CC3E_R`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&self) -> CC2NP_R`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&self) -> CC2P_R`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&self) -> CC2E_R`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt_h(&self) -> CNT_H_R`[src]

Bits 16:31 - High counter value

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - Counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr_h(&self) -> ARR_H_R`[src]

Bits 16:31 - High Auto-reload value

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr1_h(&self) -> CCR1_H_R`[src]

Bits 16:31 - High Capture/Compare 1 value

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 1 value

`impl R<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&self) -> DBL_R`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&self) -> DBA_R`[src]

Bits 0:4 - DMA base address

`impl R<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&self) -> DMAB_R`[src]

Bits 0:15 - DMA register for burst accesses

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn arpe(&self) -> ARPE_R`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&self) -> CMS_R`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&self) -> DIR_R`[src]

Bit 4 - Direction

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`pub fn uifremap(&self) -> UIFREMAP_R`[src]

Bit 11 - UIF status bit remapping

`impl R<bool, TI1S_A>`[src]

`pub fn variant(&self) -> TI1S_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_xor(&self) -> bool`[src]

Checks if the value of the field is XOR

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> MMS_A`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`pub fn is_update(&self) -> bool`[src]

Checks if the value of the field is UPDATE

`pub fn is_compare_pulse(&self) -> bool`[src]

Checks if the value of the field is COMPAREPULSE

`pub fn is_compare_oc1(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC1

`pub fn is_compare_oc2(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC2

`pub fn is_compare_oc3(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC3

`pub fn is_compare_oc4(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC4

`impl R<bool, CCDS_A>`[src]

`pub fn variant(&self) -> CCDS_A`[src]

Get enumerated values variant

`pub fn is_on_compare(&self) -> bool`[src]

Checks if the value of the field is ONCOMPARE

`pub fn is_on_update(&self) -> bool`[src]

Checks if the value of the field is ONUPDATE

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn ti1s(&self) -> TI1S_R`[src]

Bit 7 - TI1 selection

`pub fn mms(&self) -> MMS_R`[src]

Bits 4:6 - Master mode selection

`pub fn ccds(&self) -> CCDS_R`[src]

Bit 3 - Capture/compare DMA selection

`impl R<u8, SMS_A>`[src]

`pub fn variant(&self) -> SMS_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_encoder_mode_1(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_1

`pub fn is_encoder_mode_2(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_2

`pub fn is_encoder_mode_3(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_3

`pub fn is_reset_mode(&self) -> bool`[src]

Checks if the value of the field is RESET_MODE

`pub fn is_gated_mode(&self) -> bool`[src]

Checks if the value of the field is GATED_MODE

`pub fn is_trigger_mode(&self) -> bool`[src]

Checks if the value of the field is TRIGGER_MODE

`pub fn is_ext_clock_mode(&self) -> bool`[src]

Checks if the value of the field is EXT_CLOCK_MODE

`impl R<u8, TS_A>`[src]

`pub fn variant(&self) -> Variant<u8, TS_A>`[src]

Get enumerated values variant

`pub fn is_itr0(&self) -> bool`[src]

Checks if the value of the field is ITR0

`pub fn is_itr1(&self) -> bool`[src]

Checks if the value of the field is ITR1

`pub fn is_itr2(&self) -> bool`[src]

Checks if the value of the field is ITR2

`pub fn is_ti1f_ed(&self) -> bool`[src]

Checks if the value of the field is TI1F_ED

`pub fn is_ti1fp1(&self) -> bool`[src]

Checks if the value of the field is TI1FP1

`pub fn is_ti2fp2(&self) -> bool`[src]

Checks if the value of the field is TI2FP2

`pub fn is_etrf(&self) -> bool`[src]

Checks if the value of the field is ETRF

`impl R<bool, MSM_A>`[src]

`pub fn variant(&self) -> MSM_A`[src]

Get enumerated values variant

`pub fn is_no_sync(&self) -> bool`[src]

Checks if the value of the field is NOSYNC

`pub fn is_sync(&self) -> bool`[src]

Checks if the value of the field is SYNC

`impl R<u8, ETF_A>`[src]

`pub fn variant(&self) -> ETF_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, ETPS_A>`[src]

`pub fn variant(&self) -> ETPS_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<bool, ECE_A>`[src]

`pub fn variant(&self) -> ECE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, ETP_A>`[src]

`pub fn variant(&self) -> ETP_A`[src]

Get enumerated values variant

`pub fn is_not_inverted(&self) -> bool`[src]

Checks if the value of the field is NOTINVERTED

`pub fn is_inverted(&self) -> bool`[src]

Checks if the value of the field is INVERTED

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn sms(&self) -> SMS_R`[src]

Bits 0:2 - Slave mode selection

`pub fn ts(&self) -> TS_R`[src]

Bits 4:6 - Trigger selection

`pub fn msm(&self) -> MSM_R`[src]

Bit 7 - Master/Slave mode

`pub fn etf(&self) -> ETF_R`[src]

Bits 8:11 - External trigger filter

`pub fn etps(&self) -> ETPS_R`[src]

`pub fn cc2de(&self) -> CC2DE_R`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&self) -> CC1DE_R`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&self) -> UDE_R`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&self) -> TIE_R`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&self) -> CC4IE_R`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&self) -> CC3IE_R`[src]

`pub fn cc2of(&self) -> CC2OF_R`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn tif(&self) -> TIF_R`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc4if(&self) -> CC4IF_R`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&self) -> CC3IF_R`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&self) -> CC2IF_R`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u8, OC2M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC2M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC2PE_A>`[src]

`pub fn variant(&self) -> OC2PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&self) -> OC2CE_R`[src]

Bit 15 - OC2CE

`pub fn oc2m(&self) -> OC2M_R`[src]

Bits 12:14 - OC2M

`pub fn oc2pe(&self) -> OC2PE_R`[src]

Bit 11 - OC2PE

`pub fn oc2fe(&self) -> OC2FE_R`[src]

Bit 10 - OC2FE

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - CC2S

`pub fn oc1ce(&self) -> OC1CE_R`[src]

Bit 7 - OC1CE

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - OC1M

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - OC1PE

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - OC1FE

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - CC1S

`pub fn oc2m_3(&self) -> OC2M_3_R`[src]

Bit 24 - Output Compare 2 mode - bit 3

`pub fn oc1m_3(&self) -> OC1M_3_R`[src]

Bit 16 - Output Compare 1 mode - bit 3

`impl R<u8, CC2S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC2S_A>`[src]

Get enumerated values variant

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, IC1F_A>`[src]

`pub fn variant(&self) -> IC1F_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&self) -> IC2F_R`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&self) -> IC2PSC_R`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u8, OC4M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC4M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC4PE_A>`[src]

`pub fn variant(&self) -> OC4PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&self) -> OC4CE_R`[src]

Bit 15 - O24CE

`pub fn oc4m(&self) -> OC4M_R`[src]

Bits 12:14 - OC4M

`pub fn oc4pe(&self) -> OC4PE_R`[src]

Bit 11 - OC4PE

`pub fn oc4fe(&self) -> OC4FE_R`[src]

Bit 10 - OC4FE

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - CC4S

`pub fn oc3ce(&self) -> OC3CE_R`[src]

Bit 7 - OC3CE

`pub fn oc3m(&self) -> OC3M_R`[src]

Bits 4:6 - OC3M

`pub fn oc3pe(&self) -> OC3PE_R`[src]

Bit 3 - OC3PE

`pub fn oc3fe(&self) -> OC3FE_R`[src]

Bit 2 - OC3FE

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - CC3S

`pub fn oc4m_3(&self) -> OC4M_3_R`[src]

Bit 24 - Output Compare 2 mode - bit 3

`pub fn oc3m_3(&self) -> OC3M_3_R`[src]

Bit 16 - Output Compare 1 mode - bit 3

`impl R<u8, CC4S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC4S_A>`[src]

Get enumerated values variant

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&self) -> IC4F_R`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&self) -> IC4PSC_R`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&self) -> IC3F_R`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&self) -> IC3PSC_R`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - Capture/compare 3 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4np(&self) -> CC4NP_R`[src]

Bit 15 - Capture/Compare 4 output Polarity

`pub fn cc4p(&self) -> CC4P_R`[src]

Bit 13 - Capture/Compare 3 output Polarity

`pub fn cc4e(&self) -> CC4E_R`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&self) -> CC3NP_R`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3p(&self) -> CC3P_R`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&self) -> CC3E_R`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&self) -> CC2NP_R`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&self) -> CC2P_R`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&self) -> CC2E_R`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:31 - Counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:31 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:31 - Capture/Compare 1 value

`impl R<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&self) -> DBL_R`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&self) -> DBA_R`[src]

Bits 0:4 - DMA base address

`impl R<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&self) -> DMAB_R`[src]

Bits 0:15 - DMA register for burst accesses

`impl R<u32, Reg<u32, _OR>>`[src]

`pub fn ti4_rmp(&self) -> TI4_RMP_R`[src]

Bits 6:7 - Timer Input 4 remap

`impl R<u8, MODER15_A>`[src]

`pub fn variant(&self) -> MODER15_A`[src]

Get enumerated values variant

`pub fn is_input(&self) -> bool`[src]

Checks if the value of the field is INPUT

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`pub fn is_alternate(&self) -> bool`[src]

Checks if the value of the field is ALTERNATE

`pub fn is_analog(&self) -> bool`[src]

Checks if the value of the field is ANALOG

`impl R<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&self) -> MODER15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&self) -> MODER14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&self) -> MODER13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&self) -> MODER12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&self) -> MODER11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&self) -> MODER10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&self) -> MODER9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&self) -> MODER8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&self) -> MODER7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&self) -> MODER6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&self) -> MODER5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&self) -> MODER4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&self) -> MODER3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&self) -> MODER2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&self) -> MODER1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&self) -> MODER0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, OT15_A>`[src]

`pub fn variant(&self) -> OT15_A`[src]

Get enumerated values variant

`pub fn is_push_pull(&self) -> bool`[src]

Checks if the value of the field is PUSHPULL

`pub fn is_open_drain(&self) -> bool`[src]

Checks if the value of the field is OPENDRAIN

`impl R<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&self) -> OT15_R`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&self) -> OT14_R`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&self) -> OT13_R`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&self) -> OT12_R`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&self) -> OT11_R`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&self) -> OT10_R`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&self) -> OT9_R`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&self) -> OT8_R`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&self) -> OT7_R`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&self) -> OT6_R`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&self) -> OT5_R`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&self) -> OT4_R`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&self) -> OT3_R`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&self) -> OT2_R`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&self) -> OT1_R`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&self) -> OT0_R`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl R<u8, OSPEEDR15_A>`[src]

`pub fn variant(&self) -> OSPEEDR15_A`[src]

Get enumerated values variant

`pub fn is_low_speed(&self) -> bool`[src]

Checks if the value of the field is LOWSPEED

`pub fn is_medium_speed(&self) -> bool`[src]

Checks if the value of the field is MEDIUMSPEED

`pub fn is_high_speed(&self) -> bool`[src]

Checks if the value of the field is HIGHSPEED

`pub fn is_very_high_speed(&self) -> bool`[src]

Checks if the value of the field is VERYHIGHSPEED

`impl R<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&self) -> OSPEEDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn ospeedr14(&self) -> OSPEEDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn ospeedr13(&self) -> OSPEEDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn ospeedr12(&self) -> OSPEEDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn ospeedr11(&self) -> OSPEEDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn ospeedr10(&self) -> OSPEEDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn ospeedr9(&self) -> OSPEEDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn ospeedr8(&self) -> OSPEEDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn ospeedr7(&self) -> OSPEEDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn ospeedr6(&self) -> OSPEEDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn ospeedr5(&self) -> OSPEEDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn ospeedr4(&self) -> OSPEEDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn ospeedr3(&self) -> OSPEEDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn ospeedr2(&self) -> OSPEEDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn ospeedr1(&self) -> OSPEEDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn ospeedr0(&self) -> OSPEEDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<u8, PUPDR15_A>`[src]

`pub fn variant(&self) -> Variant<u8, PUPDR15_A>`[src]

Get enumerated values variant

`pub fn is_floating(&self) -> bool`[src]

Checks if the value of the field is FLOATING

`pub fn is_pull_up(&self) -> bool`[src]

Checks if the value of the field is PULLUP

`pub fn is_pull_down(&self) -> bool`[src]

Checks if the value of the field is PULLDOWN

`impl R<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&self) -> PUPDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&self) -> PUPDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&self) -> PUPDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&self) -> PUPDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&self) -> PUPDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&self) -> PUPDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&self) -> PUPDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&self) -> PUPDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&self) -> PUPDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&self) -> PUPDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&self) -> PUPDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&self) -> PUPDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&self) -> PUPDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&self) -> PUPDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&self) -> PUPDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&self) -> PUPDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, IDR15_A>`[src]

`pub fn variant(&self) -> IDR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _IDR>>`[src]

`pub fn idr15(&self) -> IDR15_R`[src]

Bit 15 - Port input data (y = 0..15)

`pub fn idr14(&self) -> IDR14_R`[src]

Bit 14 - Port input data (y = 0..15)

`pub fn idr13(&self) -> IDR13_R`[src]

Bit 13 - Port input data (y = 0..15)

`pub fn idr12(&self) -> IDR12_R`[src]

Bit 12 - Port input data (y = 0..15)

`pub fn idr11(&self) -> IDR11_R`[src]

Bit 11 - Port input data (y = 0..15)

`pub fn idr10(&self) -> IDR10_R`[src]

Bit 10 - Port input data (y = 0..15)

`pub fn idr9(&self) -> IDR9_R`[src]

Bit 9 - Port input data (y = 0..15)

`pub fn idr8(&self) -> IDR8_R`[src]

Bit 8 - Port input data (y = 0..15)

`pub fn idr7(&self) -> IDR7_R`[src]

Bit 7 - Port input data (y = 0..15)

`pub fn idr6(&self) -> IDR6_R`[src]

Bit 6 - Port input data (y = 0..15)

`pub fn idr5(&self) -> IDR5_R`[src]

Bit 5 - Port input data (y = 0..15)

`pub fn idr4(&self) -> IDR4_R`[src]

Bit 4 - Port input data (y = 0..15)

`pub fn idr3(&self) -> IDR3_R`[src]

Bit 3 - Port input data (y = 0..15)

`pub fn idr2(&self) -> IDR2_R`[src]

Bit 2 - Port input data (y = 0..15)

`pub fn idr1(&self) -> IDR1_R`[src]

Bit 1 - Port input data (y = 0..15)

`pub fn idr0(&self) -> IDR0_R`[src]

Bit 0 - Port input data (y = 0..15)

`impl R<bool, ODR15_A>`[src]

`pub fn variant(&self) -> ODR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&self) -> ODR15_R`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&self) -> ODR14_R`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&self) -> ODR13_R`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&self) -> ODR12_R`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&self) -> ODR11_R`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&self) -> ODR10_R`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&self) -> ODR9_R`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&self) -> ODR8_R`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&self) -> ODR7_R`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&self) -> ODR6_R`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&self) -> ODR5_R`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&self) -> ODR4_R`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&self) -> ODR3_R`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&self) -> ODR2_R`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&self) -> ODR1_R`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&self) -> ODR0_R`[src]

Bit 0 - Port output data (y = 0..15)

`impl R<bool, LCKK_A>`[src]

`pub fn variant(&self) -> LCKK_A`[src]

Get enumerated values variant

`pub fn is_not_active(&self) -> bool`[src]

Checks if the value of the field is NOTACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<bool, LCK15_A>`[src]

`pub fn variant(&self) -> LCK15_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<bool, LCK9_A>`[src]

`pub fn variant(&self) -> LCK9_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&self) -> LCKK_R`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&self) -> LCK15_R`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&self) -> LCK14_R`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&self) -> LCK13_R`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&self) -> LCK12_R`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&self) -> LCK11_R`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&self) -> LCK10_R`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&self) -> LCK9_R`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&self) -> LCK8_R`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&self) -> LCK7_R`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&self) -> LCK6_R`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&self) -> LCK5_R`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&self) -> LCK4_R`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&self) -> LCK3_R`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&self) -> LCK2_R`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&self) -> LCK1_R`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&self) -> LCK0_R`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl R<u8, AFRL7_A>`[src]

`pub fn variant(&self) -> AFRL7_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&self) -> AFRL7_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&self) -> AFRL6_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&self) -> AFRL5_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&self) -> AFRL4_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&self) -> AFRL3_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&self) -> AFRL2_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&self) -> AFRL1_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&self) -> AFRL0_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl R<u8, AFRH15_A>`[src]

`pub fn variant(&self) -> AFRH15_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&self) -> AFRH15_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&self) -> AFRH14_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&self) -> AFRH13_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&self) -> AFRH12_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&self) -> AFRH11_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&self) -> AFRH10_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&self) -> AFRH9_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&self) -> AFRH8_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl R<u8, MODER15_A>`[src]

`pub fn variant(&self) -> MODER15_A`[src]

Get enumerated values variant

`pub fn is_input(&self) -> bool`[src]

Checks if the value of the field is INPUT

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`pub fn is_alternate(&self) -> bool`[src]

Checks if the value of the field is ALTERNATE

`pub fn is_analog(&self) -> bool`[src]

Checks if the value of the field is ANALOG

`impl R<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&self) -> MODER15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&self) -> MODER14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&self) -> MODER13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&self) -> MODER12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&self) -> MODER11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&self) -> MODER10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&self) -> MODER9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&self) -> MODER8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&self) -> MODER7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&self) -> MODER6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&self) -> MODER5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&self) -> MODER4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&self) -> MODER3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&self) -> MODER2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&self) -> MODER1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&self) -> MODER0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, OT15_A>`[src]

`pub fn variant(&self) -> OT15_A`[src]

Get enumerated values variant

`pub fn is_push_pull(&self) -> bool`[src]

Checks if the value of the field is PUSHPULL

`pub fn is_open_drain(&self) -> bool`[src]

Checks if the value of the field is OPENDRAIN

`impl R<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&self) -> OT15_R`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&self) -> OT14_R`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&self) -> OT13_R`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&self) -> OT12_R`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&self) -> OT11_R`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&self) -> OT10_R`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&self) -> OT9_R`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&self) -> OT8_R`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&self) -> OT7_R`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&self) -> OT6_R`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&self) -> OT5_R`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&self) -> OT4_R`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&self) -> OT3_R`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&self) -> OT2_R`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&self) -> OT1_R`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&self) -> OT0_R`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl R<u8, OSPEEDR15_A>`[src]

`pub fn variant(&self) -> OSPEEDR15_A`[src]

Get enumerated values variant

`pub fn is_low_speed(&self) -> bool`[src]

Checks if the value of the field is LOWSPEED

`pub fn is_medium_speed(&self) -> bool`[src]

Checks if the value of the field is MEDIUMSPEED

`pub fn is_high_speed(&self) -> bool`[src]

Checks if the value of the field is HIGHSPEED

`pub fn is_very_high_speed(&self) -> bool`[src]

Checks if the value of the field is VERYHIGHSPEED

`impl R<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&self) -> OSPEEDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn ospeedr14(&self) -> OSPEEDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn ospeedr13(&self) -> OSPEEDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn ospeedr12(&self) -> OSPEEDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn ospeedr11(&self) -> OSPEEDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn ospeedr10(&self) -> OSPEEDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn ospeedr9(&self) -> OSPEEDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn ospeedr8(&self) -> OSPEEDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn ospeedr7(&self) -> OSPEEDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn ospeedr6(&self) -> OSPEEDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn ospeedr5(&self) -> OSPEEDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn ospeedr4(&self) -> OSPEEDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn ospeedr3(&self) -> OSPEEDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn ospeedr2(&self) -> OSPEEDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn ospeedr1(&self) -> OSPEEDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn ospeedr0(&self) -> OSPEEDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<u8, PUPDR15_A>`[src]

`pub fn variant(&self) -> Variant<u8, PUPDR15_A>`[src]

Get enumerated values variant

`pub fn is_floating(&self) -> bool`[src]

Checks if the value of the field is FLOATING

`pub fn is_pull_up(&self) -> bool`[src]

Checks if the value of the field is PULLUP

`pub fn is_pull_down(&self) -> bool`[src]

Checks if the value of the field is PULLDOWN

`impl R<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&self) -> PUPDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&self) -> PUPDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&self) -> PUPDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&self) -> PUPDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&self) -> PUPDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&self) -> PUPDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&self) -> PUPDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&self) -> PUPDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&self) -> PUPDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&self) -> PUPDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&self) -> PUPDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&self) -> PUPDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&self) -> PUPDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&self) -> PUPDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&self) -> PUPDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&self) -> PUPDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, IDR15_A>`[src]

`pub fn variant(&self) -> IDR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _IDR>>`[src]

`pub fn idr15(&self) -> IDR15_R`[src]

Bit 15 - Port input data (y = 0..15)

`pub fn idr14(&self) -> IDR14_R`[src]

Bit 14 - Port input data (y = 0..15)

`pub fn idr13(&self) -> IDR13_R`[src]

Bit 13 - Port input data (y = 0..15)

`pub fn idr12(&self) -> IDR12_R`[src]

Bit 12 - Port input data (y = 0..15)

`pub fn idr11(&self) -> IDR11_R`[src]

Bit 11 - Port input data (y = 0..15)

`pub fn idr10(&self) -> IDR10_R`[src]

Bit 10 - Port input data (y = 0..15)

`pub fn idr9(&self) -> IDR9_R`[src]

Bit 9 - Port input data (y = 0..15)

`pub fn idr8(&self) -> IDR8_R`[src]

Bit 8 - Port input data (y = 0..15)

`pub fn idr7(&self) -> IDR7_R`[src]

Bit 7 - Port input data (y = 0..15)

`pub fn idr6(&self) -> IDR6_R`[src]

Bit 6 - Port input data (y = 0..15)

`pub fn idr5(&self) -> IDR5_R`[src]

Bit 5 - Port input data (y = 0..15)

`pub fn idr4(&self) -> IDR4_R`[src]

Bit 4 - Port input data (y = 0..15)

`pub fn idr3(&self) -> IDR3_R`[src]

Bit 3 - Port input data (y = 0..15)

`pub fn idr2(&self) -> IDR2_R`[src]

Bit 2 - Port input data (y = 0..15)

`pub fn idr1(&self) -> IDR1_R`[src]

Bit 1 - Port input data (y = 0..15)

`pub fn idr0(&self) -> IDR0_R`[src]

Bit 0 - Port input data (y = 0..15)

`impl R<bool, ODR15_A>`[src]

`pub fn variant(&self) -> ODR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&self) -> ODR15_R`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&self) -> ODR14_R`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&self) -> ODR13_R`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&self) -> ODR12_R`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&self) -> ODR11_R`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&self) -> ODR10_R`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&self) -> ODR9_R`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&self) -> ODR8_R`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&self) -> ODR7_R`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&self) -> ODR6_R`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&self) -> ODR5_R`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&self) -> ODR4_R`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&self) -> ODR3_R`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&self) -> ODR2_R`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&self) -> ODR1_R`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&self) -> ODR0_R`[src]

Bit 0 - Port output data (y = 0..15)

`impl R<bool, LCKK_A>`[src]

`pub fn variant(&self) -> LCKK_A`[src]

Get enumerated values variant

`pub fn is_not_active(&self) -> bool`[src]

Checks if the value of the field is NOTACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<bool, LCK15_A>`[src]

`pub fn variant(&self) -> LCK15_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<bool, LCK9_A>`[src]

`pub fn variant(&self) -> LCK9_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&self) -> LCKK_R`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&self) -> LCK15_R`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&self) -> LCK14_R`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&self) -> LCK13_R`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&self) -> LCK12_R`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&self) -> LCK11_R`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&self) -> LCK10_R`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&self) -> LCK9_R`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&self) -> LCK8_R`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&self) -> LCK7_R`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&self) -> LCK6_R`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&self) -> LCK5_R`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&self) -> LCK4_R`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&self) -> LCK3_R`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&self) -> LCK2_R`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&self) -> LCK1_R`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&self) -> LCK0_R`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl R<u8, AFRL7_A>`[src]

`pub fn variant(&self) -> AFRL7_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&self) -> AFRL7_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&self) -> AFRL6_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&self) -> AFRL5_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&self) -> AFRL4_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&self) -> AFRL3_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&self) -> AFRL2_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&self) -> AFRL1_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&self) -> AFRL0_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl R<u8, AFRH15_A>`[src]

`pub fn variant(&self) -> AFRH15_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&self) -> AFRH15_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&self) -> AFRH14_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&self) -> AFRH13_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&self) -> AFRH12_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&self) -> AFRH11_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&self) -> AFRH10_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&self) -> AFRH9_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&self) -> AFRH8_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl R<u8, MODER15_A>`[src]

`pub fn variant(&self) -> MODER15_A`[src]

Get enumerated values variant

`pub fn is_input(&self) -> bool`[src]

Checks if the value of the field is INPUT

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`pub fn is_alternate(&self) -> bool`[src]

Checks if the value of the field is ALTERNATE

`pub fn is_analog(&self) -> bool`[src]

Checks if the value of the field is ANALOG

`impl R<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&self) -> MODER15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&self) -> MODER14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&self) -> MODER13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&self) -> MODER12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&self) -> MODER11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&self) -> MODER10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&self) -> MODER9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&self) -> MODER8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&self) -> MODER7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&self) -> MODER6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&self) -> MODER5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&self) -> MODER4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&self) -> MODER3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&self) -> MODER2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&self) -> MODER1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&self) -> MODER0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, OT15_A>`[src]

`pub fn variant(&self) -> OT15_A`[src]

Get enumerated values variant

`pub fn is_push_pull(&self) -> bool`[src]

Checks if the value of the field is PUSHPULL

`pub fn is_open_drain(&self) -> bool`[src]

Checks if the value of the field is OPENDRAIN

`impl R<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&self) -> OT15_R`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&self) -> OT14_R`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&self) -> OT13_R`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&self) -> OT12_R`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&self) -> OT11_R`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&self) -> OT10_R`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&self) -> OT9_R`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&self) -> OT8_R`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&self) -> OT7_R`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&self) -> OT6_R`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&self) -> OT5_R`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&self) -> OT4_R`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&self) -> OT3_R`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&self) -> OT2_R`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&self) -> OT1_R`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&self) -> OT0_R`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl R<u8, OSPEEDR15_A>`[src]

`pub fn variant(&self) -> OSPEEDR15_A`[src]

Get enumerated values variant

`pub fn is_low_speed(&self) -> bool`[src]

Checks if the value of the field is LOWSPEED

`pub fn is_medium_speed(&self) -> bool`[src]

Checks if the value of the field is MEDIUMSPEED

`pub fn is_high_speed(&self) -> bool`[src]

Checks if the value of the field is HIGHSPEED

`pub fn is_very_high_speed(&self) -> bool`[src]

Checks if the value of the field is VERYHIGHSPEED

`impl R<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&self) -> OSPEEDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn ospeedr14(&self) -> OSPEEDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn ospeedr13(&self) -> OSPEEDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn ospeedr12(&self) -> OSPEEDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn ospeedr11(&self) -> OSPEEDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn ospeedr10(&self) -> OSPEEDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn ospeedr9(&self) -> OSPEEDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn ospeedr8(&self) -> OSPEEDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn ospeedr7(&self) -> OSPEEDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn ospeedr6(&self) -> OSPEEDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn ospeedr5(&self) -> OSPEEDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn ospeedr4(&self) -> OSPEEDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn ospeedr3(&self) -> OSPEEDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn ospeedr2(&self) -> OSPEEDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn ospeedr1(&self) -> OSPEEDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn ospeedr0(&self) -> OSPEEDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<u8, PUPDR15_A>`[src]

`pub fn variant(&self) -> Variant<u8, PUPDR15_A>`[src]

Get enumerated values variant

`pub fn is_floating(&self) -> bool`[src]

Checks if the value of the field is FLOATING

`pub fn is_pull_up(&self) -> bool`[src]

Checks if the value of the field is PULLUP

`pub fn is_pull_down(&self) -> bool`[src]

Checks if the value of the field is PULLDOWN

`impl R<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&self) -> PUPDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&self) -> PUPDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&self) -> PUPDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&self) -> PUPDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&self) -> PUPDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&self) -> PUPDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&self) -> PUPDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&self) -> PUPDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&self) -> PUPDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&self) -> PUPDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&self) -> PUPDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&self) -> PUPDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&self) -> PUPDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&self) -> PUPDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&self) -> PUPDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&self) -> PUPDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, IDR15_A>`[src]

`pub fn variant(&self) -> IDR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _IDR>>`[src]

`pub fn idr15(&self) -> IDR15_R`[src]

Bit 15 - Port input data (y = 0..15)

`pub fn idr14(&self) -> IDR14_R`[src]

Bit 14 - Port input data (y = 0..15)

`pub fn idr13(&self) -> IDR13_R`[src]

Bit 13 - Port input data (y = 0..15)

`pub fn idr12(&self) -> IDR12_R`[src]

Bit 12 - Port input data (y = 0..15)

`pub fn idr11(&self) -> IDR11_R`[src]

Bit 11 - Port input data (y = 0..15)

`pub fn idr10(&self) -> IDR10_R`[src]

Bit 10 - Port input data (y = 0..15)

`pub fn idr9(&self) -> IDR9_R`[src]

Bit 9 - Port input data (y = 0..15)

`pub fn idr8(&self) -> IDR8_R`[src]

Bit 8 - Port input data (y = 0..15)

`pub fn idr7(&self) -> IDR7_R`[src]

Bit 7 - Port input data (y = 0..15)

`pub fn idr6(&self) -> IDR6_R`[src]

Bit 6 - Port input data (y = 0..15)

`pub fn idr5(&self) -> IDR5_R`[src]

Bit 5 - Port input data (y = 0..15)

`pub fn idr4(&self) -> IDR4_R`[src]

Bit 4 - Port input data (y = 0..15)

`pub fn idr3(&self) -> IDR3_R`[src]

Bit 3 - Port input data (y = 0..15)

`pub fn idr2(&self) -> IDR2_R`[src]

Bit 2 - Port input data (y = 0..15)

`pub fn idr1(&self) -> IDR1_R`[src]

Bit 1 - Port input data (y = 0..15)

`pub fn idr0(&self) -> IDR0_R`[src]

Bit 0 - Port input data (y = 0..15)

`impl R<bool, ODR15_A>`[src]

`pub fn variant(&self) -> ODR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&self) -> ODR15_R`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&self) -> ODR14_R`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&self) -> ODR13_R`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&self) -> ODR12_R`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&self) -> ODR11_R`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&self) -> ODR10_R`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&self) -> ODR9_R`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&self) -> ODR8_R`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&self) -> ODR7_R`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&self) -> ODR6_R`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&self) -> ODR5_R`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&self) -> ODR4_R`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&self) -> ODR3_R`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&self) -> ODR2_R`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&self) -> ODR1_R`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&self) -> ODR0_R`[src]

Bit 0 - Port output data (y = 0..15)

`impl R<bool, LCKK_A>`[src]

`pub fn variant(&self) -> LCKK_A`[src]

Get enumerated values variant

`pub fn is_not_active(&self) -> bool`[src]

Checks if the value of the field is NOTACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<bool, LCK15_A>`[src]

`pub fn variant(&self) -> LCK15_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<bool, LCK9_A>`[src]

`pub fn variant(&self) -> LCK9_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&self) -> LCKK_R`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&self) -> LCK15_R`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&self) -> LCK14_R`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&self) -> LCK13_R`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&self) -> LCK12_R`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&self) -> LCK11_R`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&self) -> LCK10_R`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&self) -> LCK9_R`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&self) -> LCK8_R`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&self) -> LCK7_R`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&self) -> LCK6_R`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&self) -> LCK5_R`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&self) -> LCK4_R`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&self) -> LCK3_R`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&self) -> LCK2_R`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&self) -> LCK1_R`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&self) -> LCK0_R`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl R<u8, AFRL7_A>`[src]

`pub fn variant(&self) -> AFRL7_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&self) -> AFRL7_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&self) -> AFRL6_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&self) -> AFRL5_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&self) -> AFRL4_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&self) -> AFRL3_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&self) -> AFRL2_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&self) -> AFRL1_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&self) -> AFRL0_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl R<u8, AFRH15_A>`[src]

`pub fn variant(&self) -> AFRH15_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&self) -> AFRH15_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&self) -> AFRH14_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&self) -> AFRH13_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&self) -> AFRH12_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&self) -> AFRH11_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&self) -> AFRH10_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&self) -> AFRH9_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&self) -> AFRH8_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`impl R<bool, UIE_A>`[src]

`pub fn variant(&self) -> UIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _DIER>>`[src]

`pub fn cc1ie(&self) -> CC1IE_R`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&self) -> UIE_R`[src]

Bit 0 - Update interrupt enable

`impl R<bool, UIF_A>`[src]

`pub fn variant(&self) -> UIF_A`[src]

Get enumerated values variant

`pub fn is_clear(&self) -> bool`[src]

Checks if the value of the field is CLEAR

`pub fn is_update_pending(&self) -> bool`[src]

Checks if the value of the field is UPDATEPENDING

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - Output Compare 1 mode

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - Output Compare 1 preload enable

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - Output Compare 1 fast enable

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`pub fn oc1m_3(&self) -> OC1M_3_R`[src]

Bit 16 - Output Compare 1 mode - bit 3

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 1 value

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn res(&self) -> RES_R`[src]

Bits 0:31 - Res.

`impl R<u32, Reg<u32, _OR>>`[src]

`pub fn ti1_rmp(&self) -> TI1_RMP_R`[src]

Bits 0:1 - TIM11 Input 1 remapping capability

`impl R<u8, PR_A>`[src]

`pub fn variant(&self) -> PR_A`[src]

Get enumerated values variant

`pub fn is_divide_by4(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY4

`pub fn is_divide_by8(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY8

`pub fn is_divide_by16(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY16

`pub fn is_divide_by32(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY32

`pub fn is_divide_by64(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY64

`pub fn is_divide_by128(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY128

`pub fn is_divide_by256(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY256

`pub fn is_divide_by256bis(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY256BIS

`impl R<u32, Reg<u32, _PR>>`[src]

`pub fn pr(&self) -> PR_R`[src]

Bits 0:2 - Prescaler divider

`impl R<u32, Reg<u32, _RLR>>`[src]

`pub fn rl(&self) -> RL_R`[src]

Bits 0:11 - Watchdog counter reload value

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn rvu(&self) -> RVU_R`[src]

Bit 1 - Watchdog counter reload value update

`pub fn pvu(&self) -> PVU_R`[src]

Bit 0 - Watchdog prescaler value update

`pub fn wvu(&self) -> WVU_R`[src]

Bit 2 - Watchdog counter window value update

Checks if the value of the field is NOFILTER

`pub fn is_filter1(&self) -> bool`[src]

Checks if the value of the field is FILTER1

`pub fn is_filter2(&self) -> bool`[src]

Checks if the value of the field is FILTER2

`pub fn is_filter3(&self) -> bool`[src]

Checks if the value of the field is FILTER3

`pub fn is_filter4(&self) -> bool`[src]

Checks if the value of the field is FILTER4

`pub fn is_filter5(&self) -> bool`[src]

Checks if the value of the field is FILTER5

`pub fn is_filter6(&self) -> bool`[src]

Checks if the value of the field is FILTER6

`pub fn is_filter7(&self) -> bool`[src]

Checks if the value of the field is FILTER7

`pub fn is_filter8(&self) -> bool`[src]

Checks if the value of the field is FILTER8

`pub fn is_filter9(&self) -> bool`[src]

Checks if the value of the field is FILTER9

`pub fn is_filter10(&self) -> bool`[src]

Checks if the value of the field is FILTER10

`pub fn is_filter11(&self) -> bool`[src]

Checks if the value of the field is FILTER11

`pub fn is_filter12(&self) -> bool`[src]

`pub fn addrie(&self) -> ADDRIE_R`[src]

Bit 3 - Address match interrupt enable (slave only)

`pub fn nackie(&self) -> NACKIE_R`[src]

Bit 4 - Not acknowledge received interrupt enable

`pub fn stopie(&self) -> STOPIE_R`[src]

Bit 5 - STOP detection Interrupt enable

`pub fn tcie(&self) -> TCIE_R`[src]

Bit 6 - Transfer Complete interrupt enable

`pub fn errie(&self) -> ERRIE_R`[src]

Bit 7 - Error interrupts enable

`pub fn dnf(&self) -> DNF_R`[src]

Bits 8:11 - Digital noise filter

`pub fn anfoff(&self) -> ANFOFF_R`[src]

Bit 12 - Analog noise filter OFF

`pub fn txdmaen(&self) -> TXDMAEN_R`[src]

Bit 14 - DMA transmission requests enable

`pub fn rxdmaen(&self) -> RXDMAEN_R`[src]

Bit 15 - DMA reception requests enable

`pub fn sbc(&self) -> SBC_R`[src]

Bit 16 - Slave byte control

`pub fn nostretch(&self) -> NOSTRETCH_R`[src]

Bit 17 - Clock stretching disable

`pub fn gcen(&self) -> GCEN_R`[src]

Bit 19 - General call enable

`pub fn smbhen(&self) -> SMBHEN_R`[src]

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn pecbyte(&self) -> PECBYTE_R`[src]

Bit 26 - Packet error checking byte

`pub fn autoend(&self) -> AUTOEND_R`[src]

Bit 25 - Automatic end mode (master mode)

`pub fn reload(&self) -> RELOAD_R`[src]

Bit 24 - NBYTES reload mode

`pub fn nbytes(&self) -> NBYTES_R`[src]

Bits 16:23 - Number of bytes

`pub fn nack(&self) -> NACK_R`[src]

Bit 15 - NACK generation (slave mode)

`pub fn stop(&self) -> STOP_R`[src]

Bit 14 - Stop generation (master mode)

`pub fn start(&self) -> START_R`[src]

Bit 13 - Start generation

`pub fn head10r(&self) -> HEAD10R_R`[src]

Bit 12 - 10-bit address header only read direction (master receiver mode)

`pub fn add10(&self) -> ADD10_R`[src]

Bit 11 - 10-bit addressing mode (master mode)

`pub fn rd_wrn(&self) -> RD_WRN_R`[src]

Bit 10 - Transfer direction (master mode)

`pub fn sadd(&self) -> SADD_R`[src]

Bits 0:9 - Slave address bit (master mode)

`impl R<bool, OA1MODE_A>`[src]

`pub fn variant(&self) -> OA1MODE_A`[src]

Get enumerated values variant

`pub fn is_bit7(&self) -> bool`[src]

Checks if the value of the field is BIT7

`pub fn is_bit10(&self) -> bool`[src]

Checks if the value of the field is BIT10

`impl R<bool, OA1EN_A>`[src]

`pub fn variant(&self) -> OA1EN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _OAR1>>`[src]

`pub fn oa1(&self) -> OA1_R`[src]

Bits 0:9 - Interface address

`pub fn oa1mode(&self) -> OA1MODE_R`[src]

Bit 10 - Own Address 1 10-bit mode

`pub fn oa1en(&self) -> OA1EN_R`[src]

Bit 15 - Own Address 1 enable

`impl R<u8, OA2MSK_A>`[src]

`pub fn variant(&self) -> OA2MSK_A`[src]

Get enumerated values variant

`pub fn is_no_mask(&self) -> bool`[src]

Checks if the value of the field is NOMASK

`pub fn is_mask1(&self) -> bool`[src]

Checks if the value of the field is MASK1

`pub fn is_mask2(&self) -> bool`[src]

Checks if the value of the field is MASK2

`pub fn is_mask3(&self) -> bool`[src]

Checks if the value of the field is MASK3

`pub fn is_mask4(&self) -> bool`[src]

Checks if the value of the field is MASK4

`pub fn is_mask5(&self) -> bool`[src]

Checks if the value of the field is MASK5

`pub fn is_mask6(&self) -> bool`[src]

Checks if the value of the field is MASK6

`pub fn is_mask7(&self) -> bool`[src]

Checks if the value of the field is MASK7

`impl R<bool, OA2EN_A>`[src]

`pub fn variant(&self) -> OA2EN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _OAR2>>`[src]

`pub fn oa2(&self) -> OA2_R`[src]

Bits 1:7 - Interface address

`pub fn oa2msk(&self) -> OA2MSK_R`[src]

Bits 8:10 - Own Address 2 masks

`pub fn oa2en(&self) -> OA2EN_R`[src]

Bit 15 - Own Address 2 enable

`impl R<u32, Reg<u32, _TIMINGR>>`[src]

`pub fn scll(&self) -> SCLL_R`[src]

Bits 0:7 - SCL low period (master mode)

`pub fn sclh(&self) -> SCLH_R`[src]

Bits 8:15 - SCL high period (master mode)

`pub fn sdadel(&self) -> SDADEL_R`[src]

Bits 16:19 - Data hold time

`pub fn scldel(&self) -> SCLDEL_R`[src]

Bits 20:23 - Data setup time

`pub fn presc(&self) -> PRESC_R`[src]

Bits 28:31 - Timing prescaler

`impl R<bool, TIDLE_A>`[src]

`pub fn variant(&self) -> TIDLE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, TIMOUTEN_A>`[src]

`pub fn variant(&self) -> TIMOUTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, TEXTEN_A>`[src]

`pub fn variant(&self) -> TEXTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _TIMEOUTR>>`[src]

`pub fn timeouta(&self) -> TIMEOUTA_R`[src]

Bits 0:11 - Bus timeout A

`pub fn tidle(&self) -> TIDLE_R`[src]

`pub fn alert(&self) -> ALERT_R`[src]

Bit 13 - SMBus alert

`pub fn timeout(&self) -> TIMEOUT_R`[src]

Bit 12 - Timeout or t_low detection flag

`pub fn pecerr(&self) -> PECERR_R`[src]

Bit 11 - PEC Error in reception

`pub fn ovr(&self) -> OVR_R`[src]

Bit 10 - Overrun/Underrun (slave mode)

`pub fn arlo(&self) -> ARLO_R`[src]

Bit 9 - Arbitration lost

`pub fn berr(&self) -> BERR_R`[src]

Bit 8 - Bus error

`pub fn tcr(&self) -> TCR_R`[src]

Bit 7 - Transfer Complete Reload

`pub fn tc(&self) -> TC_R`[src]

Bit 6 - Transfer Complete (master mode)

`pub fn stopf(&self) -> STOPF_R`[src]

Bit 5 - Stop detection flag

`pub fn nackf(&self) -> NACKF_R`[src]

Bit 4 - Not acknowledge received flag

`pub fn addr(&self) -> ADDR_R`[src]

Bit 3 - Address matched (slave mode)

`pub fn rxne(&self) -> RXNE_R`[src]

Bit 2 - Receive data register not empty (receivers)

`pub fn txis(&self) -> TXIS_R`[src]

Bit 1 - Transmit interrupt status (transmitters)

`pub fn txe(&self) -> TXE_R`[src]

Bit 0 - Transmit data register empty (transmitters)

`impl R<u32, Reg<u32, _PECR>>`[src]

`pub fn pec(&self) -> PEC_R`[src]

Bits 0:7 - Packet error checking register

`impl R<u32, Reg<u32, _RXDR>>`[src]

`pub fn rxdata(&self) -> RXDATA_R`[src]

Bits 0:7 - 8-bit receive data

`impl R<u32, Reg<u32, _TXDR>>`[src]

`pub fn txdata(&self) -> TXDATA_R`[src]

Bits 0:7 - 8-bit transmit data

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn down(&self) -> DOWN_R`[src]

Bit 6 - Counter direction change up to down

`pub fn up(&self) -> UP_R`[src]

Bit 5 - Counter direction change down to up

`pub fn arrok(&self) -> ARROK_R`[src]

Bit 4 - Autoreload register update OK

`pub fn cmpok(&self) -> CMPOK_R`[src]

Bit 3 - Compare register update OK

`pub fn exttrig(&self) -> EXTTRIG_R`[src]

Bit 2 - External trigger edge event

`pub fn arrm(&self) -> ARRM_R`[src]

Bit 1 - Autoreload match

`pub fn cmpm(&self) -> CMPM_R`[src]

Bit 0 - Compare match

`impl R<u32, Reg<u32, _IER>>`[src]

`pub fn downie(&self) -> DOWNIE_R`[src]

Bit 6 - Direction change to down Interrupt Enable

`pub fn upie(&self) -> UPIE_R`[src]

Bit 5 - Direction change to UP Interrupt Enable

`pub fn arrokie(&self) -> ARROKIE_R`[src]

Bit 4 - Autoreload register update OK Interrupt Enable

`pub fn cmpokie(&self) -> CMPOKIE_R`[src]

Bit 3 - Compare register update OK Interrupt Enable

`pub fn exttrigie(&self) -> EXTTRIGIE_R`[src]

Bit 2 - External trigger valid edge Interrupt Enable

`pub fn arrmie(&self) -> ARRMIE_R`[src]

Bit 1 - Autoreload match Interrupt Enable

`pub fn cmpmie(&self) -> CMPMIE_R`[src]

Bit 0 - Compare match Interrupt Enable

`impl R<u32, Reg<u32, _CFGR>>`[src]

`pub fn enc(&self) -> ENC_R`[src]

Bit 24 - Encoder mode enable

`pub fn countmode(&self) -> COUNTMODE_R`[src]

Bit 23 - counter mode enabled

`pub fn preload(&self) -> PRELOAD_R`[src]

Bit 22 - Registers update mode

`pub fn wavpol(&self) -> WAVPOL_R`[src]

Bit 21 - Waveform shape polarity

`pub fn wave(&self) -> WAVE_R`[src]

Bit 20 - Waveform shape

`pub fn timout(&self) -> TIMOUT_R`[src]

Bit 19 - Timeout enable

`pub fn trigen(&self) -> TRIGEN_R`[src]

Bits 17:18 - Trigger enable and polarity

`pub fn trigsel(&self) -> TRIGSEL_R`[src]

Bits 13:15 - Trigger selector

`pub fn presc(&self) -> PRESC_R`[src]

Bits 9:11 - Clock prescaler

`pub fn trgflt(&self) -> TRGFLT_R`[src]

Bits 6:7 - Configurable digital filter for trigger

`pub fn ckflt(&self) -> CKFLT_R`[src]

Bits 3:4 - Configurable digital filter for external clock

`pub fn ckpol(&self) -> CKPOL_R`[src]

Bits 1:2 - Clock Polarity

`pub fn cksel(&self) -> CKSEL_R`[src]

Bit 0 - Clock selector

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn cntstrt(&self) -> CNTSTRT_R`[src]

Bit 2 - Timer start in continuous mode

`pub fn sngstrt(&self) -> SNGSTRT_R`[src]

Bit 1 - LPTIM start in single mode

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 0 - LPTIM Enable

`impl R<u32, Reg<u32, _CMP>>`[src]

`pub fn cmp(&self) -> CMP_R`[src]

Bits 0:15 - Compare value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto reload value

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - Counter value

`impl R<bool, PDDS_A>`[src]

`pub fn variant(&self) -> PDDS_A`[src]

Get enumerated values variant

`pub fn is_stop_mode(&self) -> bool`[src]

Checks if the value of the field is STOP_MODE

`pub fn is_standby_mode(&self) -> bool`[src]

Checks if the value of the field is STANDBY_MODE

`impl R<u8, VOS_A>`[src]

`pub fn variant(&self) -> Variant<u8, VOS_A>`[src]

Get enumerated values variant

`pub fn is_scale1(&self) -> bool`[src]

Checks if the value of the field is SCALE1

`pub fn is_scale2(&self) -> bool`[src]

Checks if the value of the field is SCALE2

`pub fn is_scale3(&self) -> bool`[src]

Checks if the value of the field is SCALE3

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn lpds(&self) -> LPDS_R`[src]

Bit 0 - Low-power deep sleep

`pub fn pdds(&self) -> PDDS_R`[src]

Bit 1 - Power down deepsleep

`pub fn csbf(&self) -> CSBF_R`[src]

Bit 3 - Clear standby flag

`pub fn pvde(&self) -> PVDE_R`[src]

Bit 4 - Power voltage detector enable

`pub fn pls(&self) -> PLS_R`[src]

Bits 5:7 - PVD level selection

`pub fn dbp(&self) -> DBP_R`[src]

Bit 8 - Disable backup domain write protection

`pub fn fpds(&self) -> FPDS_R`[src]

Bit 9 - Flash power down in Stop mode

`pub fn lpuds(&self) -> LPUDS_R`[src]

Bit 10 - Low-power regulator in deepsleep under-drive mode

`pub fn mruds(&self) -> MRUDS_R`[src]

Bit 11 - Main regulator in deepsleep under-drive mode

`pub fn adcdc1(&self) -> ADCDC1_R`[src]

Bit 13 - ADCDC1

`pub fn vos(&self) -> VOS_R`[src]

Bits 14:15 - Regulator voltage scaling output selection

`pub fn oden(&self) -> ODEN_R`[src]

Bit 16 - Over-drive enable

`pub fn odswen(&self) -> ODSWEN_R`[src]

Bit 17 - Over-drive switching enabled

`pub fn uden(&self) -> UDEN_R`[src]

Bits 18:19 - Under-drive enable in stop mode

`impl R<u32, Reg<u32, _CSR1>>`[src]

`pub fn wuif(&self) -> WUIF_R`[src]

Bit 0 - Wakeup internal flag

`pub fn sbf(&self) -> SBF_R`[src]

Bit 1 - Standby flag

`pub fn pvdo(&self) -> PVDO_R`[src]

Bit 2 - PVD output

`pub fn brr(&self) -> BRR_R`[src]

Bit 3 - Backup regulator ready

`pub fn bre(&self) -> BRE_R`[src]

Bit 9 - Backup regulator enable

`pub fn vosrdy(&self) -> VOSRDY_R`[src]

Bit 14 - Regulator voltage scaling output selection ready bit

`pub fn odrdy(&self) -> ODRDY_R`[src]

Bit 16 - Over-drive mode ready

`pub fn odswrdy(&self) -> ODSWRDY_R`[src]

Bit 17 - Over-drive mode switching ready

`pub fn udrdy(&self) -> UDRDY_R`[src]

Bits 18:19 - Under-drive ready flag

`pub fn eiwup(&self) -> EIWUP_R`[src]

Bit 8 - Enable internal wakeup

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn cwupf1(&self) -> CWUPF1_R`[src]

Bit 0 - Clear Wakeup Pin flag for PA0

`pub fn cwupf2(&self) -> CWUPF2_R`[src]

Bit 1 - Clear Wakeup Pin flag for PA2

`pub fn cwupf3(&self) -> CWUPF3_R`[src]

Bit 2 - Clear Wakeup Pin flag for PC1

`pub fn cwupf4(&self) -> CWUPF4_R`[src]

Bit 3 - Clear Wakeup Pin flag for PC13

`pub fn cwupf5(&self) -> CWUPF5_R`[src]

Bit 4 - Clear Wakeup Pin flag for PI8

`pub fn cwupf6(&self) -> CWUPF6_R`[src]

Bit 5 - Clear Wakeup Pin flag for PI11

`pub fn wupp1(&self) -> WUPP1_R`[src]

Bit 8 - Wakeup pin polarity bit for PA0

`pub fn wupp2(&self) -> WUPP2_R`[src]

Bit 9 - Wakeup pin polarity bit for PA2

`pub fn wupp3(&self) -> WUPP3_R`[src]

Bit 10 - Wakeup pin polarity bit for PC1

`pub fn wupp4(&self) -> WUPP4_R`[src]

Bit 11 - Wakeup pin polarity bit for PC13

`pub fn wupp5(&self) -> WUPP5_R`[src]

Bit 12 - Wakeup pin polarity bit for PI8

`pub fn wupp6(&self) -> WUPP6_R`[src]

Bit 13 - Wakeup pin polarity bit for PI11

`impl R<u32, Reg<u32, _CSR2>>`[src]

`pub fn wupf1(&self) -> WUPF1_R`[src]

Bit 0 - Wakeup Pin flag for PA0

`pub fn wupf2(&self) -> WUPF2_R`[src]

Bit 1 - Wakeup Pin flag for PA2

`pub fn wupf3(&self) -> WUPF3_R`[src]

Bit 2 - Wakeup Pin flag for PC1

`pub fn wupf4(&self) -> WUPF4_R`[src]

Bit 3 - Wakeup Pin flag for PC13

`pub fn wupf5(&self) -> WUPF5_R`[src]

Bit 4 - Wakeup Pin flag for PI8

`pub fn wupf6(&self) -> WUPF6_R`[src]

Bit 5 - Wakeup Pin flag for PI11

`pub fn ewup1(&self) -> EWUP1_R`[src]

Bit 8 - Enable Wakeup pin for PA0

`pub fn ewup2(&self) -> EWUP2_R`[src]

Bit 9 - Enable Wakeup pin for PA2

`pub fn ewup3(&self) -> EWUP3_R`[src]

Bit 10 - Enable Wakeup pin for PC1

`pub fn ewup4(&self) -> EWUP4_R`[src]

Bit 11 - Enable Wakeup pin for PC13

`pub fn ewup5(&self) -> EWUP5_R`[src]

Bit 12 - Enable Wakeup pin for PI8

`pub fn ewup6(&self) -> EWUP6_R`[src]

Bit 13 - Enable Wakeup pin for PI11

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn prescaler(&self) -> PRESCALER_R`[src]

Bits 24:31 - Clock prescaler

`pub fn pmm(&self) -> PMM_R`[src]

Bit 23 - Polling match mode

`pub fn apms(&self) -> APMS_R`[src]

Bit 22 - Automatic poll mode stop

`pub fn toie(&self) -> TOIE_R`[src]

Bit 20 - TimeOut interrupt enable

`pub fn smie(&self) -> SMIE_R`[src]

Bit 19 - Status match interrupt enable

`pub fn ftie(&self) -> FTIE_R`[src]

Bit 18 - FIFO threshold interrupt enable

`pub fn tcie(&self) -> TCIE_R`[src]

Bit 17 - Transfer complete interrupt enable

`pub fn teie(&self) -> TEIE_R`[src]

Bit 16 - Transfer error interrupt enable

`pub fn fthres(&self) -> FTHRES_R`[src]

Bits 8:12 - IFO threshold level

`pub fn fsel(&self) -> FSEL_R`[src]

Bit 7 - FLASH memory selection

`pub fn dfm(&self) -> DFM_R`[src]

Bit 6 - Dual-flash mode

`pub fn sshift(&self) -> SSHIFT_R`[src]

Bit 4 - Sample shift

`pub fn tcen(&self) -> TCEN_R`[src]

Bit 3 - Timeout counter enable

`pub fn dmaen(&self) -> DMAEN_R`[src]

Bit 2 - DMA enable

`pub fn abort(&self) -> ABORT_R`[src]

Bit 1 - Abort request

`pub fn en(&self) -> EN_R`[src]

Bit 0 - Enable

`impl R<u32, Reg<u32, _DCR>>`[src]

`pub fn fsize(&self) -> FSIZE_R`[src]

Bits 16:20 - FLASH memory size

`pub fn csht(&self) -> CSHT_R`[src]

Bits 8:10 - Chip select high time

`pub fn ckmode(&self) -> CKMODE_R`[src]

Bit 0 - Mode 0 / mode 3

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn flevel(&self) -> FLEVEL_R`[src]

Bits 8:14 - FIFO level

`pub fn busy(&self) -> BUSY_R`[src]

Bit 5 - Busy

`pub fn tof(&self) -> TOF_R`[src]

Bit 4 - Timeout flag

`pub fn smf(&self) -> SMF_R`[src]

Bit 3 - Status match flag

`pub fn ftf(&self) -> FTF_R`[src]

Bit 2 - FIFO threshold flag

`pub fn tcf(&self) -> TCF_R`[src]

Bit 1 - Transfer complete flag

`pub fn tef(&self) -> TEF_R`[src]

Bit 0 - Transfer error flag

`impl R<u32, Reg<u32, _FCR>>`[src]

`pub fn ctof(&self) -> CTOF_R`[src]

Bit 4 - Clear timeout flag

`pub fn csmf(&self) -> CSMF_R`[src]

Bit 3 - Clear status match flag

`pub fn ctcf(&self) -> CTCF_R`[src]

Bit 1 - Clear transfer complete flag

`pub fn ctef(&self) -> CTEF_R`[src]

Bit 0 - Clear transfer error flag

`impl R<u32, Reg<u32, _DLR>>`[src]

`pub fn dl(&self) -> DL_R`[src]

Bits 0:31 - Data length

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ddrm(&self) -> DDRM_R`[src]

Bit 31 - Double data rate mode

`pub fn dhhc(&self) -> DHHC_R`[src]

Bit 30 - DDR hold half cycle

`pub fn sioo(&self) -> SIOO_R`[src]

Bit 28 - Send instruction only once mode

`pub fn fmode(&self) -> FMODE_R`[src]

Bits 26:27 - Functional mode

`pub fn dmode(&self) -> DMODE_R`[src]

Bits 24:25 - Data mode

`pub fn dcyc(&self) -> DCYC_R`[src]

Bits 18:22 - Number of dummy cycles

`pub fn absize(&self) -> ABSIZE_R`[src]

Bits 16:17 - Alternate bytes size

`pub fn abmode(&self) -> ABMODE_R`[src]

Bits 14:15 - Alternate bytes mode

`pub fn adsize(&self) -> ADSIZE_R`[src]

Bits 12:13 - Address size

`pub fn admode(&self) -> ADMODE_R`[src]

Bits 10:11 - Address mode

`pub fn imode(&self) -> IMODE_R`[src]

Bits 8:9 - Instruction mode

`pub fn instruction(&self) -> INSTRUCTION_R`[src]

Bits 0:7 - Instruction

`impl R<u32, Reg<u32, _AR>>`[src]

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:31 - Address

`impl R<u32, Reg<u32, _ABR>>`[src]

`pub fn alternate(&self) -> ALTERNATE_R`[src]

Bits 0:31 - ALTERNATE

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn data(&self) -> DATA_R`[src]

Bits 0:31 - Data

`impl R<u32, Reg<u32, _PSMKR>>`[src]

`pub fn mask(&self) -> MASK_R`[src]

Bits 0:31 - Status mask

`impl R<u32, Reg<u32, _PSMAR>>`[src]

`pub fn match_(&self) -> MATCH_R`[src]

Bits 0:31 - Status match

`impl R<u32, Reg<u32, _PIR>>`[src]

`pub fn interval(&self) -> INTERVAL_R`[src]

Bits 0:15 - Polling interval

`impl R<u32, Reg<u32, _LPTR>>`[src]

`pub fn timeout(&self) -> TIMEOUT_R`[src]

Bits 0:15 - Timeout period

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn ie(&self) -> IE_R`[src]

Bit 3 - Interrupt enable

`pub fn rngen(&self) -> RNGEN_R`[src]

Bit 2 - Random number generator enable

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn seis(&self) -> SEIS_R`[src]

Bit 6 - Seed error interrupt status

`pub fn ceis(&self) -> CEIS_R`[src]

Bit 5 - Clock error interrupt status

`pub fn secs(&self) -> SECS_R`[src]

Bit 2 - Seed error current status

`pub fn cecs(&self) -> CECS_R`[src]

Bit 1 - Clock error current status

`pub fn drdy(&self) -> DRDY_R`[src]

Bit 0 - Data ready

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn rndata(&self) -> RNDATA_R`[src]

Bits 0:31 - Random data

`impl R<u32, Reg<u32, _TR>>`[src]

`pub fn pm(&self) -> PM_R`[src]

Bit 22 - AM/PM notation

`pub fn ht(&self) -> HT_R`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&self) -> HU_R`[src]

Bits 16:19 - Hour units in BCD format

`pub fn mnt(&self) -> MNT_R`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&self) -> MNU_R`[src]

Bits 8:11 - Minute units in BCD format

`pub fn st(&self) -> ST_R`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&self) -> SU_R`[src]

Bits 0:3 - Second units in BCD format

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn yt(&self) -> YT_R`[src]

Bits 20:23 - Year tens in BCD format

`pub fn yu(&self) -> YU_R`[src]

Bits 16:19 - Year units in BCD format

`pub fn wdu(&self) -> WDU_R`[src]

Bits 13:15 - Week day units

`pub fn mt(&self) -> MT_R`[src]

Bit 12 - Month tens in BCD format

`pub fn mu(&self) -> MU_R`[src]

Bits 8:11 - Month units in BCD format

`pub fn dt(&self) -> DT_R`[src]

Bits 4:5 - Date tens in BCD format

`pub fn du(&self) -> DU_R`[src]

Bits 0:3 - Date units in BCD format

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn wcksel(&self) -> WCKSEL_R`[src]

Bits 0:2 - Wakeup clock selection

`pub fn tsedge(&self) -> TSEDGE_R`[src]

Bit 3 - Time-stamp event active edge

`pub fn refckon(&self) -> REFCKON_R`[src]

Bit 4 - Reference clock detection enable (50 or 60 Hz)

`pub fn bypshad(&self) -> BYPSHAD_R`[src]

Bit 5 - Bypass the shadow registers

`pub fn fmt(&self) -> FMT_R`[src]

Bit 6 - Hour format

`pub fn alrae(&self) -> ALRAE_R`[src]

Bit 8 - Alarm A enable

`pub fn alrbe(&self) -> ALRBE_R`[src]

Bit 9 - Alarm B enable

`pub fn wute(&self) -> WUTE_R`[src]

Bit 10 - Wakeup timer enable

`pub fn tse(&self) -> TSE_R`[src]

Bit 11 - Time stamp enable

`pub fn alraie(&self) -> ALRAIE_R`[src]

Bit 12 - Alarm A interrupt enable

`pub fn alrbie(&self) -> ALRBIE_R`[src]

Bit 13 - Alarm B interrupt enable

`pub fn wutie(&self) -> WUTIE_R`[src]

Bit 14 - Wakeup timer interrupt enable

`pub fn tsie(&self) -> TSIE_R`[src]

Bit 15 - Time-stamp interrupt enable

`pub fn add1h(&self) -> ADD1H_R`[src]

Bit 16 - Add 1 hour (summer time change)

`pub fn sub1h(&self) -> SUB1H_R`[src]

Bit 17 - Subtract 1 hour (winter time change)

`pub fn bkp(&self) -> BKP_R`[src]

Bit 18 - Backup

`pub fn cosel(&self) -> COSEL_R`[src]

Bit 19 - Calibration output selection

`pub fn pol(&self) -> POL_R`[src]

Bit 20 - Output polarity

`pub fn osel(&self) -> OSEL_R`[src]

Bits 21:22 - Output selection

`pub fn coe(&self) -> COE_R`[src]

Bit 23 - Calibration output enable

`pub fn itse(&self) -> ITSE_R`[src]

Bit 24 - timestamp on internal event enable

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn alrawf(&self) -> ALRAWF_R`[src]

Bit 0 - Alarm A write flag

`pub fn alrbwf(&self) -> ALRBWF_R`[src]

Bit 1 - Alarm B write flag

`pub fn wutwf(&self) -> WUTWF_R`[src]

Bit 2 - Wakeup timer write flag

`pub fn shpf(&self) -> SHPF_R`[src]

Bit 3 - Shift operation pending

`pub fn inits(&self) -> INITS_R`[src]

Bit 4 - Initialization status flag

`pub fn rsf(&self) -> RSF_R`[src]

Bit 5 - Registers synchronization flag

`pub fn initf(&self) -> INITF_R`[src]

Bit 6 - Initialization flag

`pub fn init(&self) -> INIT_R`[src]

Bit 7 - Initialization mode

`pub fn alraf(&self) -> ALRAF_R`[src]

Bit 8 - Alarm A flag

`pub fn alrbf(&self) -> ALRBF_R`[src]

Bit 9 - Alarm B flag

`pub fn wutf(&self) -> WUTF_R`[src]

Bit 10 - Wakeup timer flag

`pub fn tsf(&self) -> TSF_R`[src]

Bit 11 - Time-stamp flag

`pub fn tsovf(&self) -> TSOVF_R`[src]

Bit 12 - Time-stamp overflow flag

`pub fn tamp1f(&self) -> TAMP1F_R`[src]

Bit 13 - Tamper detection flag

`pub fn tamp2f(&self) -> TAMP2F_R`[src]

Bit 14 - RTC_TAMP2 detection flag

`pub fn tamp3f(&self) -> TAMP3F_R`[src]

Bit 15 - RTC_TAMP3 detection flag

`pub fn recalpf(&self) -> RECALPF_R`[src]

Bit 16 - Recalibration pending Flag

`pub fn itsf(&self) -> ITSF_R`[src]

Bit 17 - Internal tTime-stamp flag

`impl R<u32, Reg<u32, _PRER>>`[src]

`pub fn prediv_a(&self) -> PREDIV_A_R`[src]

Bits 16:22 - Asynchronous prescaler factor

`pub fn prediv_s(&self) -> PREDIV_S_R`[src]

Bits 0:14 - Synchronous prescaler factor

`impl R<u32, Reg<u32, _WUTR>>`[src]

`pub fn wut(&self) -> WUT_R`[src]

Bits 0:15 - Wakeup auto-reload value bits

`impl R<u32, Reg<u32, _ALRMAR>>`[src]

`pub fn msk4(&self) -> MSK4_R`[src]

Bit 31 - Alarm A date mask

`pub fn wdsel(&self) -> WDSEL_R`[src]

Bit 30 - Week day selection

`pub fn dt(&self) -> DT_R`[src]

Bits 28:29 - Date tens in BCD format

`pub fn du(&self) -> DU_R`[src]

Bits 24:27 - Date units or day in BCD format

`pub fn msk3(&self) -> MSK3_R`[src]

Bit 23 - Alarm A hours mask

`pub fn pm(&self) -> PM_R`[src]

Bit 22 - AM/PM notation

`pub fn ht(&self) -> HT_R`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&self) -> HU_R`[src]

Bits 16:19 - Hour units in BCD format

`pub fn msk2(&self) -> MSK2_R`[src]

Bit 15 - Alarm A minutes mask

`pub fn mnt(&self) -> MNT_R`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&self) -> MNU_R`[src]

Bits 8:11 - Minute units in BCD format

`pub fn msk1(&self) -> MSK1_R`[src]

Bit 7 - Alarm A seconds mask

`pub fn st(&self) -> ST_R`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&self) -> SU_R`[src]

Bits 0:3 - Second units in BCD format

`impl R<u32, Reg<u32, _ALRMBR>>`[src]

`pub fn msk4(&self) -> MSK4_R`[src]

Bit 31 - Alarm B date mask

`pub fn wdsel(&self) -> WDSEL_R`[src]

Bit 30 - Week day selection

`pub fn dt(&self) -> DT_R`[src]

Bits 28:29 - Date tens in BCD format

`pub fn du(&self) -> DU_R`[src]

Bits 24:27 - Date units or day in BCD format

`pub fn msk3(&self) -> MSK3_R`[src]

Bit 23 - Alarm B hours mask

`pub fn pm(&self) -> PM_R`[src]

Bit 22 - AM/PM notation

`pub fn ht(&self) -> HT_R`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&self) -> HU_R`[src]

Bits 16:19 - Hour units in BCD format

`pub fn msk2(&self) -> MSK2_R`[src]

Bit 15 - Alarm B minutes mask

`pub fn mnt(&self) -> MNT_R`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&self) -> MNU_R`[src]

Bits 8:11 - Minute units in BCD format

`pub fn msk1(&self) -> MSK1_R`[src]

Bit 7 - Alarm B seconds mask

`pub fn st(&self) -> ST_R`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&self) -> SU_R`[src]

Bits 0:3 - Second units in BCD format

`impl R<u32, Reg<u32, _SSR>>`[src]

`pub fn ss(&self) -> SS_R`[src]

Bits 0:15 - Sub second value

`impl R<u32, Reg<u32, _TSTR>>`[src]

`pub fn su(&self) -> SU_R`[src]

Bits 0:3 - Second units in BCD format

`pub fn st(&self) -> ST_R`[src]

Bits 4:6 - Second tens in BCD format

`pub fn mnu(&self) -> MNU_R`[src]

Bits 8:11 - Minute units in BCD format

`pub fn mnt(&self) -> MNT_R`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn hu(&self) -> HU_R`[src]

Bits 16:19 - Hour units in BCD format

`pub fn ht(&self) -> HT_R`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn pm(&self) -> PM_R`[src]

Bit 22 - AM/PM notation

`impl R<u32, Reg<u32, _TSDR>>`[src]

`pub fn wdu(&self) -> WDU_R`[src]

Bits 13:15 - Week day units

`pub fn mt(&self) -> MT_R`[src]

Bit 12 - Month tens in BCD format

`pub fn mu(&self) -> MU_R`[src]

Bits 8:11 - Month units in BCD format

`pub fn dt(&self) -> DT_R`[src]

Bits 4:5 - Date tens in BCD format

`pub fn du(&self) -> DU_R`[src]

Bits 0:3 - Date units in BCD format

`impl R<u32, Reg<u32, _TSSSR>>`[src]

`pub fn ss(&self) -> SS_R`[src]

Bits 0:15 - Sub second value

`impl R<u32, Reg<u32, _CALR>>`[src]

`pub fn calp(&self) -> CALP_R`[src]

Bit 15 - Increase frequency of RTC by 488.5 ppm

`pub fn calw8(&self) -> CALW8_R`[src]

Bit 14 - Use an 8-second calibration cycle period

`pub fn calw16(&self) -> CALW16_R`[src]

Bit 13 - Use a 16-second calibration cycle period

`pub fn calm(&self) -> CALM_R`[src]

Bits 0:8 - Calibration minus

`impl R<u32, Reg<u32, _TAMPCR>>`[src]

`pub fn tamp1e(&self) -> TAMP1E_R`[src]

Bit 0 - Tamper 1 detection enable

`pub fn tamp1trg(&self) -> TAMP1TRG_R`[src]

Bit 1 - Active level for tamper 1

`pub fn tampie(&self) -> TAMPIE_R`[src]

Bit 2 - Tamper interrupt enable

`pub fn tamp2e(&self) -> TAMP2E_R`[src]

Bit 3 - Tamper 2 detection enable

`pub fn tamp2trg(&self) -> TAMP2TRG_R`[src]

Bit 4 - Active level for tamper 2

`pub fn tamp3e(&self) -> TAMP3E_R`[src]

Bit 5 - Tamper 3 detection enable

`pub fn tamp3trg(&self) -> TAMP3TRG_R`[src]

Bit 6 - Active level for tamper 3

`pub fn tampts(&self) -> TAMPTS_R`[src]

Bit 7 - Activate timestamp on tamper detection event

`pub fn tampfreq(&self) -> TAMPFREQ_R`[src]

Bits 8:10 - Tamper sampling frequency

`pub fn tampflt(&self) -> TAMPFLT_R`[src]

Bits 11:12 - Tamper filter count

`pub fn tampprch(&self) -> TAMPPRCH_R`[src]

Bits 13:14 - Tamper precharge duration

`pub fn tamppudis(&self) -> TAMPPUDIS_R`[src]

Bit 15 - TAMPER pull-up disable

`pub fn tamp1ie(&self) -> TAMP1IE_R`[src]

Bit 16 - Tamper 1 interrupt enable

`pub fn tamp1noerase(&self) -> TAMP1NOERASE_R`[src]

Bit 17 - Tamper 1 no erase

`pub fn tamp1mf(&self) -> TAMP1MF_R`[src]

Bit 18 - Tamper 1 mask flag

`pub fn tamp2ie(&self) -> TAMP2IE_R`[src]

Bit 19 - Tamper 2 interrupt enable

`pub fn tamp2noerase(&self) -> TAMP2NOERASE_R`[src]

Bit 20 - Tamper 2 no erase

`pub fn tamp2mf(&self) -> TAMP2MF_R`[src]

Bit 21 - Tamper 2 mask flag

`pub fn tamp3ie(&self) -> TAMP3IE_R`[src]

Bit 22 - Tamper 3 interrupt enable

`pub fn tamp3noerase(&self) -> TAMP3NOERASE_R`[src]

Bit 23 - Tamper 3 no erase

`pub fn tamp3mf(&self) -> TAMP3MF_R`[src]

Bit 24 - Tamper 3 mask flag

`impl R<u32, Reg<u32, _ALRMASSR>>`[src]

`pub fn maskss(&self) -> MASKSS_R`[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

`pub fn ss(&self) -> SS_R`[src]

Bits 0:14 - Sub seconds value

`impl R<u32, Reg<u32, _ALRMBSSR>>`[src]

`pub fn maskss(&self) -> MASKSS_R`[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

`pub fn ss(&self) -> SS_R`[src]

Bits 0:14 - Sub seconds value

`impl R<u32, Reg<u32, _OR>>`[src]

`pub fn rtc_alarm_type(&self) -> RTC_ALARM_TYPE_R`[src]

Bit 3 - RTC_ALARM on PC13 output type

`pub fn tsinsel(&self) -> TSINSEL_R`[src]

Bit 1 - TIMESTAMP mapping

`impl R<u32, Reg<u32, _BKPR>>`[src]

`pub fn bkp(&self) -> BKP_R`[src]

Bits 0:31 - BKP

`impl R<bool, PLLI2SRDY_A>`[src]

`pub fn variant(&self) -> PLLI2SRDY_A`[src]

Get enumerated values variant

`pub fn is_not_ready(&self) -> bool`[src]

Checks if the value of the field is NOTREADY

`pub fn is_ready(&self) -> bool`[src]

Checks if the value of the field is READY

`impl R<bool, PLLI2SON_A>`[src]

`pub fn variant(&self) -> PLLI2SON_A`[src]

Get enumerated values variant

`pub fn is_off(&self) -> bool`[src]

Checks if the value of the field is OFF

`pub fn is_on(&self) -> bool`[src]

Checks if the value of the field is ON

`impl R<bool, CSSON_A>`[src]

`pub fn variant(&self) -> CSSON_A`[src]

Get enumerated values variant

`pub fn is_off(&self) -> bool`[src]

Checks if the value of the field is OFF

`pub fn is_on(&self) -> bool`[src]

Checks if the value of the field is ON

`impl R<bool, HSEBYP_A>`[src]

`pub fn variant(&self) -> HSEBYP_A`[src]

Get enumerated values variant

`pub fn is_not_bypassed(&self) -> bool`[src]

Checks if the value of the field is NOTBYPASSED

`pub fn is_bypassed(&self) -> bool`[src]

Checks if the value of the field is BYPASSED

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn plli2srdy(&self) -> PLLI2SRDY_R`[src]

Bit 27 - PLLI2S clock ready flag

`pub fn plli2son(&self) -> PLLI2SON_R`[src]

Bit 26 - PLLI2S enable

`pub fn pllrdy(&self) -> PLLRDY_R`[src]

Bit 25 - Main PLL (PLL) clock ready flag

`pub fn pllon(&self) -> PLLON_R`[src]

Bit 24 - Main PLL (PLL) enable

`pub fn csson(&self) -> CSSON_R`[src]

Bit 19 - Clock security system enable

`pub fn hsebyp(&self) -> HSEBYP_R`[src]

Bit 18 - HSE clock bypass

`pub fn hserdy(&self) -> HSERDY_R`[src]

Bit 17 - HSE clock ready flag

`pub fn hseon(&self) -> HSEON_R`[src]

Bit 16 - HSE clock enable

`pub fn hsical(&self) -> HSICAL_R`[src]

Bits 8:15 - Internal high-speed clock calibration

`pub fn hsitrim(&self) -> HSITRIM_R`[src]

Bits 3:7 - Internal high-speed clock trimming

`pub fn hsirdy(&self) -> HSIRDY_R`[src]

Bit 1 - Internal high-speed clock ready flag

`pub fn hsion(&self) -> HSION_R`[src]

Bit 0 - Internal high-speed clock enable

`pub fn pllsairdy(&self) -> PLLSAIRDY_R`[src]

Bit 29 - PLLSAI clock ready flag

`pub fn pllsaion(&self) -> PLLSAION_R`[src]

Bit 28 - PLLSAI enable

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div3(&self) -> bool`[src]

Checks if the value of the field is DIV3

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div5(&self) -> bool`[src]

Checks if the value of the field is DIV5

`impl R<bool, I2SSRC_A>`[src]

`pub fn variant(&self) -> I2SSRC_A`[src]

Get enumerated values variant

`pub fn is_plli2s(&self) -> bool`[src]

Checks if the value of the field is PLLI2S

`pub fn is_ckin(&self) -> bool`[src]

Checks if the value of the field is CKIN

`impl R<u8, MCO1_A>`[src]

`pub fn variant(&self) -> MCO1_A`[src]

Get enumerated values variant

`pub fn is_hsi(&self) -> bool`[src]

Checks if the value of the field is HSI

`pub fn is_lse(&self) -> bool`[src]

Checks if the value of the field is LSE

`pub fn is_hse(&self) -> bool`[src]

Checks if the value of the field is HSE

`pub fn is_pll(&self) -> bool`[src]

Checks if the value of the field is PLL

`impl R<u8, PPRE2_A>`[src]

`pub fn variant(&self) -> Variant<u8, PPRE2_A>`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`impl R<u8, HPRE_A>`[src]

`pub fn variant(&self) -> Variant<u8, HPRE_A>`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`pub fn is_div64(&self) -> bool`[src]

Checks if the value of the field is DIV64

`pub fn is_div128(&self) -> bool`[src]

Checks if the value of the field is DIV128

`pub fn is_div256(&self) -> bool`[src]

Checks if the value of the field is DIV256

`pub fn is_div512(&self) -> bool`[src]

Checks if the value of the field is DIV512

`impl R<u8, SW_A>`[src]

`pub fn variant(&self) -> Variant<u8, SW_A>`[src]

Get enumerated values variant

`pub fn is_hsi(&self) -> bool`[src]

Checks if the value of the field is HSI

`pub fn is_hse(&self) -> bool`[src]

Checks if the value of the field is HSE

`pub fn is_pll(&self) -> bool`[src]

Checks if the value of the field is PLL

`impl R<u8, SWS_A>`[src]

`pub fn variant(&self) -> Variant<u8, SWS_A>`[src]

Get enumerated values variant

`pub fn is_hsi(&self) -> bool`[src]

Checks if the value of the field is HSI

`pub fn is_hse(&self) -> bool`[src]

Checks if the value of the field is HSE

`pub fn is_pll(&self) -> bool`[src]

Checks if the value of the field is PLL

`impl R<u32, Reg<u32, _CFGR>>`[src]

`pub fn mco2(&self) -> MCO2_R`[src]

Bits 30:31 - Microcontroller clock output 2

`pub fn mco2pre(&self) -> MCO2PRE_R`[src]

Bits 27:29 - MCO2 prescaler

`pub fn mco1pre(&self) -> MCO1PRE_R`[src]

Bits 24:26 - MCO1 prescaler

`pub fn i2ssrc(&self) -> I2SSRC_R`[src]

Bit 23 - I2S clock selection

`pub fn mco1(&self) -> MCO1_R`[src]

Bits 21:22 - Microcontroller clock output 1

`pub fn rtcpre(&self) -> RTCPRE_R`[src]

Bits 16:20 - HSE division factor for RTC clock

`pub fn ppre2(&self) -> PPRE2_R`[src]

Bits 13:15 - APB high-speed prescaler (APB2)

`pub fn ppre1(&self) -> PPRE1_R`[src]

Bits 10:12 - APB Low speed prescaler (APB1)

`pub fn hpre(&self) -> HPRE_R`[src]

Bits 4:7 - AHB prescaler

`pub fn sw(&self) -> SW_R`[src]

Bits 0:1 - System clock switch

`pub fn sws(&self) -> SWS_R`[src]

Bits 2:3 - System clock switch status

`impl R<bool, PLLSAIRDYIE_A>`[src]

`pub fn variant(&self) -> PLLSAIRDYIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, CSSF_A>`[src]

`pub fn variant(&self) -> CSSF_A`[src]

Get enumerated values variant

`pub fn is_not_interrupted(&self) -> bool`[src]

Checks if the value of the field is NOTINTERRUPTED

`pub fn is_interrupted(&self) -> bool`[src]

Checks if the value of the field is INTERRUPTED

`impl R<bool, PLLSAIRDYF_A>`[src]

`pub fn variant(&self) -> PLLSAIRDYF_A`[src]

Get enumerated values variant

`pub fn is_not_interrupted(&self) -> bool`[src]

Checks if the value of the field is NOTINTERRUPTED

`pub fn is_interrupted(&self) -> bool`[src]

Checks if the value of the field is INTERRUPTED

`impl R<u32, Reg<u32, _CIR>>`[src]

`pub fn pllsairdyie(&self) -> PLLSAIRDYIE_R`[src]

Bit 14 - PLLSAI Ready Interrupt Enable

`pub fn plli2srdyie(&self) -> PLLI2SRDYIE_R`[src]

Bit 13 - PLLI2S ready interrupt enable

`pub fn pllrdyie(&self) -> PLLRDYIE_R`[src]

Bit 12 - Main PLL (PLL) ready interrupt enable

`pub fn hserdyie(&self) -> HSERDYIE_R`[src]

Bit 11 - HSE ready interrupt enable

`pub fn hsirdyie(&self) -> HSIRDYIE_R`[src]

Bit 10 - HSI ready interrupt enable

`pub fn lserdyie(&self) -> LSERDYIE_R`[src]

Bit 9 - LSE ready interrupt enable

`pub fn lsirdyie(&self) -> LSIRDYIE_R`[src]

Bit 8 - LSI ready interrupt enable

`pub fn cssf(&self) -> CSSF_R`[src]

Bit 7 - Clock security system interrupt flag

`pub fn pllsairdyf(&self) -> PLLSAIRDYF_R`[src]

Bit 6 - PLLSAI ready interrupt flag

`pub fn plli2srdyf(&self) -> PLLI2SRDYF_R`[src]

Bit 5 - PLLI2S ready interrupt flag

`pub fn pllrdyf(&self) -> PLLRDYF_R`[src]

Bit 4 - Main PLL (PLL) ready interrupt flag

`pub fn hserdyf(&self) -> HSERDYF_R`[src]

Bit 3 - HSE ready interrupt flag

`pub fn hsirdyf(&self) -> HSIRDYF_R`[src]

Bit 2 - HSI ready interrupt flag

`pub fn lserdyf(&self) -> LSERDYF_R`[src]

Bit 1 - LSE ready interrupt flag

`pub fn lsirdyf(&self) -> LSIRDYF_R`[src]

Bit 0 - LSI ready interrupt flag

`impl R<bool, OTGHSRST_A>`[src]

`pub fn variant(&self) -> Variant<bool, OTGHSRST_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _AHB1RSTR>>`[src]

`pub fn otghsrst(&self) -> OTGHSRST_R`[src]

Bit 29 - USB OTG HS module reset

`pub fn dma2rst(&self) -> DMA2RST_R`[src]

Bit 22 - DMA2 reset

`pub fn dma1rst(&self) -> DMA1RST_R`[src]

Bit 21 - DMA2 reset

`pub fn crcrst(&self) -> CRCRST_R`[src]

Bit 12 - CRC reset

`pub fn gpioirst(&self) -> GPIOIRST_R`[src]

Bit 8 - IO port I reset

`pub fn gpiohrst(&self) -> GPIOHRST_R`[src]

Bit 7 - IO port H reset

`pub fn gpiogrst(&self) -> GPIOGRST_R`[src]

Bit 6 - IO port G reset

`pub fn gpiofrst(&self) -> GPIOFRST_R`[src]

Bit 5 - IO port F reset

`pub fn gpioerst(&self) -> GPIOERST_R`[src]

Bit 4 - IO port E reset

`pub fn gpiodrst(&self) -> GPIODRST_R`[src]

Bit 3 - IO port D reset

`pub fn gpiocrst(&self) -> GPIOCRST_R`[src]

Bit 2 - IO port C reset

`pub fn gpiobrst(&self) -> GPIOBRST_R`[src]

Bit 1 - IO port B reset

`pub fn gpioarst(&self) -> GPIOARST_R`[src]

Bit 0 - IO port A reset

`impl R<bool, OTGFSRST_A>`[src]

`pub fn variant(&self) -> Variant<bool, OTGFSRST_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _AHB2RSTR>>`[src]

`pub fn otgfsrst(&self) -> OTGFSRST_R`[src]

Bit 7 - USB OTG FS module reset

`pub fn rngrst(&self) -> RNGRST_R`[src]

Bit 6 - Random number generator module reset

`pub fn aesrst(&self) -> AESRST_R`[src]

Bit 4 - AES module reset

`impl R<bool, FMCRST_A>`[src]

`pub fn variant(&self) -> Variant<bool, FMCRST_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _AHB3RSTR>>`[src]

`pub fn fmcrst(&self) -> FMCRST_R`[src]

Bit 0 - Flexible memory controller module reset

`pub fn qspirst(&self) -> QSPIRST_R`[src]

Bit 1 - Quad SPI memory controller reset

`impl R<bool, TIM2RST_A>`[src]

`pub fn variant(&self) -> Variant<bool, TIM2RST_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _APB1RSTR>>`[src]

`pub fn tim2rst(&self) -> TIM2RST_R`[src]

Bit 0 - TIM2 reset

`pub fn tim3rst(&self) -> TIM3RST_R`[src]

Bit 1 - TIM3 reset

`pub fn tim4rst(&self) -> TIM4RST_R`[src]

Bit 2 - TIM4 reset

`pub fn tim5rst(&self) -> TIM5RST_R`[src]

Bit 3 - TIM5 reset

`pub fn tim6rst(&self) -> TIM6RST_R`[src]

Bit 4 - TIM6 reset

`pub fn tim7rst(&self) -> TIM7RST_R`[src]

Bit 5 - TIM7 reset

`pub fn tim12rst(&self) -> TIM12RST_R`[src]

Bit 6 - TIM12 reset

`pub fn tim13rst(&self) -> TIM13RST_R`[src]

Bit 7 - TIM13 reset

`pub fn tim14rst(&self) -> TIM14RST_R`[src]

Bit 8 - TIM14 reset

`pub fn wwdgrst(&self) -> WWDGRST_R`[src]

Bit 11 - Window watchdog reset

`pub fn spi2rst(&self) -> SPI2RST_R`[src]

Bit 14 - SPI 2 reset

`pub fn spi3rst(&self) -> SPI3RST_R`[src]

Bit 15 - SPI 3 reset

`pub fn uart2rst(&self) -> UART2RST_R`[src]

Bit 17 - USART 2 reset

`pub fn uart3rst(&self) -> UART3RST_R`[src]

Bit 18 - USART 3 reset

`pub fn uart4rst(&self) -> UART4RST_R`[src]

Bit 19 - USART 4 reset

`pub fn uart5rst(&self) -> UART5RST_R`[src]

Bit 20 - USART 5 reset

`pub fn i2c1rst(&self) -> I2C1RST_R`[src]

Bit 21 - I2C 1 reset

`pub fn i2c2rst(&self) -> I2C2RST_R`[src]

Bit 22 - I2C 2 reset

`pub fn i2c3rst(&self) -> I2C3RST_R`[src]

Bit 23 - I2C3 reset

`pub fn can1rst(&self) -> CAN1RST_R`[src]

Bit 25 - CAN1 reset

`pub fn pwrrst(&self) -> PWRRST_R`[src]

Bit 28 - Power interface reset

`pub fn dacrst(&self) -> DACRST_R`[src]

Bit 29 - DAC reset

`pub fn uart7rst(&self) -> UART7RST_R`[src]

Bit 30 - UART7 reset

`pub fn uart8rst(&self) -> UART8RST_R`[src]

Bit 31 - UART8 reset

`pub fn cecrst(&self) -> CECRST_R`[src]

Bit 27 - HDMI-CEC reset

`pub fn lptim1rst(&self) -> LPTIM1RST_R`[src]

Bit 9 - Low power timer 1 reset

`impl R<bool, TIM1RST_A>`[src]

`pub fn variant(&self) -> Variant<bool, TIM1RST_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _APB2RSTR>>`[src]

`pub fn tim1rst(&self) -> TIM1RST_R`[src]

Bit 0 - TIM1 reset

`pub fn tim8rst(&self) -> TIM8RST_R`[src]

Bit 1 - TIM8 reset

`pub fn usart1rst(&self) -> USART1RST_R`[src]

Bit 4 - USART1 reset

`pub fn usart6rst(&self) -> USART6RST_R`[src]

Bit 5 - USART6 reset

`pub fn adcrst(&self) -> ADCRST_R`[src]

Bit 8 - ADC interface reset (common to all ADCs)

`pub fn spi1rst(&self) -> SPI1RST_R`[src]

Bit 12 - SPI 1 reset

`pub fn spi4rst(&self) -> SPI4RST_R`[src]

Bit 13 - SPI4 reset

`pub fn syscfgrst(&self) -> SYSCFGRST_R`[src]

Bit 14 - System configuration controller reset

`pub fn tim9rst(&self) -> TIM9RST_R`[src]

Bit 16 - TIM9 reset

`pub fn tim10rst(&self) -> TIM10RST_R`[src]

Bit 17 - TIM10 reset

`pub fn tim11rst(&self) -> TIM11RST_R`[src]

Bit 18 - TIM11 reset

`pub fn spi5rst(&self) -> SPI5RST_R`[src]

Bit 20 - SPI5 reset

`pub fn sai1rst(&self) -> SAI1RST_R`[src]

Bit 22 - SAI1 reset

`pub fn sai2rst(&self) -> SAI2RST_R`[src]

Bit 23 - SAI2 reset

`pub fn sdmmc1rst(&self) -> SDMMC1RST_R`[src]

Bit 11 - SDMMC1 reset

`pub fn sdmmc2rst(&self) -> SDMMC2RST_R`[src]

Bit 7 - SDMMC2 reset

`pub fn usbphycrst(&self) -> USBPHYCRST_R`[src]

Bit 31 - USB OTG HS PHY controller reset

`impl R<bool, OTGHSULPIEN_A>`[src]

`pub fn variant(&self) -> OTGHSULPIEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _AHB1ENR>>`[src]

`pub fn otghsulpien(&self) -> OTGHSULPIEN_R`[src]

Bit 30 - USB OTG HSULPI clock enable

`pub fn otghsen(&self) -> OTGHSEN_R`[src]

Bit 29 - USB OTG HS clock enable

`pub fn dma2en(&self) -> DMA2EN_R`[src]

Bit 22 - DMA2 clock enable

`pub fn dma1en(&self) -> DMA1EN_R`[src]

Bit 21 - DMA1 clock enable

`pub fn dtcmramen(&self) -> DTCMRAMEN_R`[src]

Bit 20 - CCM data RAM clock enable

`pub fn bkpsramen(&self) -> BKPSRAMEN_R`[src]

Bit 18 - Backup SRAM interface clock enable

`pub fn crcen(&self) -> CRCEN_R`[src]

Bit 12 - CRC clock enable

`pub fn gpioien(&self) -> GPIOIEN_R`[src]

Bit 8 - IO port I clock enable

`pub fn gpiohen(&self) -> GPIOHEN_R`[src]

Bit 7 - IO port H clock enable

`pub fn gpiogen(&self) -> GPIOGEN_R`[src]

Bit 6 - IO port G clock enable

`pub fn gpiofen(&self) -> GPIOFEN_R`[src]

Bit 5 - IO port F clock enable

`pub fn gpioeen(&self) -> GPIOEEN_R`[src]

Bit 4 - IO port E clock enable

`pub fn gpioden(&self) -> GPIODEN_R`[src]

Bit 3 - IO port D clock enable

`pub fn gpiocen(&self) -> GPIOCEN_R`[src]

Bit 2 - IO port C clock enable

`pub fn gpioben(&self) -> GPIOBEN_R`[src]

Bit 1 - IO port B clock enable

`pub fn gpioaen(&self) -> GPIOAEN_R`[src]

Bit 0 - IO port A clock enable

`impl R<bool, OTGFSEN_A>`[src]

`pub fn variant(&self) -> OTGFSEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _AHB2ENR>>`[src]

`pub fn otgfsen(&self) -> OTGFSEN_R`[src]

Bit 7 - USB OTG FS clock enable

`pub fn rngen(&self) -> RNGEN_R`[src]

Bit 6 - Random number generator clock enable

`pub fn aesen(&self) -> AESEN_R`[src]

Bit 4 - AES module clock enable

`impl R<bool, FMCEN_A>`[src]

`pub fn variant(&self) -> FMCEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _AHB3ENR>>`[src]

`pub fn fmcen(&self) -> FMCEN_R`[src]

Bit 0 - Flexible memory controller module clock enable

`pub fn qspien(&self) -> QSPIEN_R`[src]

Bit 1 - Quad SPI memory controller clock enable

`impl R<bool, TIM2EN_A>`[src]

`pub fn variant(&self) -> TIM2EN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _APB1ENR>>`[src]

`pub fn tim2en(&self) -> TIM2EN_R`[src]

Bit 0 - TIM2 clock enable

`pub fn tim3en(&self) -> TIM3EN_R`[src]

Bit 1 - TIM3 clock enable

`pub fn tim4en(&self) -> TIM4EN_R`[src]

Bit 2 - TIM4 clock enable

`pub fn tim5en(&self) -> TIM5EN_R`[src]

Bit 3 - TIM5 clock enable

`pub fn tim6en(&self) -> TIM6EN_R`[src]

Bit 4 - TIM6 clock enable

`pub fn tim7en(&self) -> TIM7EN_R`[src]

Bit 5 - TIM7 clock enable

`pub fn tim12en(&self) -> TIM12EN_R`[src]

Bit 6 - TIM12 clock enable

`pub fn tim13en(&self) -> TIM13EN_R`[src]

Bit 7 - TIM13 clock enable

`pub fn tim14en(&self) -> TIM14EN_R`[src]

Bit 8 - TIM14 clock enable

`pub fn wwdgen(&self) -> WWDGEN_R`[src]

Bit 11 - Window watchdog clock enable

`pub fn spi2en(&self) -> SPI2EN_R`[src]

Bit 14 - SPI2 clock enable

`pub fn spi3en(&self) -> SPI3EN_R`[src]

Bit 15 - SPI3 clock enable

`pub fn usart2en(&self) -> USART2EN_R`[src]

Bit 17 - USART 2 clock enable

`pub fn usart3en(&self) -> USART3EN_R`[src]

Bit 18 - USART3 clock enable

`pub fn uart4en(&self) -> UART4EN_R`[src]

Bit 19 - UART4 clock enable

`pub fn uart5en(&self) -> UART5EN_R`[src]

Bit 20 - UART5 clock enable

`pub fn i2c1en(&self) -> I2C1EN_R`[src]

Bit 21 - I2C1 clock enable

`pub fn i2c2en(&self) -> I2C2EN_R`[src]

Bit 22 - I2C2 clock enable

`pub fn i2c3en(&self) -> I2C3EN_R`[src]

Bit 23 - I2C3 clock enable

`pub fn can1en(&self) -> CAN1EN_R`[src]

Bit 25 - CAN 1 clock enable

`pub fn pwren(&self) -> PWREN_R`[src]

Bit 28 - Power interface clock enable

`pub fn dacen(&self) -> DACEN_R`[src]

Bit 29 - DAC interface clock enable

`pub fn uart7en(&self) -> UART7EN_R`[src]

Bit 30 - UART7 clock enable

`pub fn uart8en(&self) -> UART8EN_R`[src]

Bit 31 - UART8 clock enable

`pub fn lptim1en(&self) -> LPTIM1EN_R`[src]

Bit 9 - Low power timer 1 clock enable

`pub fn rtcapben(&self) -> RTCAPBEN_R`[src]

Bit 10 - RTCAPB clock enable

`impl R<bool, TIM1EN_A>`[src]

`pub fn variant(&self) -> TIM1EN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _APB2ENR>>`[src]

`pub fn tim1en(&self) -> TIM1EN_R`[src]

Bit 0 - TIM1 clock enable

`pub fn tim8en(&self) -> TIM8EN_R`[src]

Bit 1 - TIM8 clock enable

`pub fn usart1en(&self) -> USART1EN_R`[src]

Bit 4 - USART1 clock enable

`pub fn usart6en(&self) -> USART6EN_R`[src]

Bit 5 - USART6 clock enable

`pub fn adc1en(&self) -> ADC1EN_R`[src]

Bit 8 - ADC1 clock enable

`pub fn adc2en(&self) -> ADC2EN_R`[src]

Bit 9 - ADC2 clock enable

`pub fn adc3en(&self) -> ADC3EN_R`[src]

Bit 10 - ADC3 clock enable

`pub fn spi1en(&self) -> SPI1EN_R`[src]

Bit 12 - SPI1 clock enable

`pub fn spi4en(&self) -> SPI4EN_R`[src]

Bit 13 - SPI4 clock enable

`pub fn syscfgen(&self) -> SYSCFGEN_R`[src]

Bit 14 - System configuration controller clock enable

`pub fn tim9en(&self) -> TIM9EN_R`[src]

Bit 16 - TIM9 clock enable

`pub fn tim10en(&self) -> TIM10EN_R`[src]

Bit 17 - TIM10 clock enable

`pub fn tim11en(&self) -> TIM11EN_R`[src]

Bit 18 - TIM11 clock enable

`pub fn spi5en(&self) -> SPI5EN_R`[src]

Bit 20 - SPI5 clock enable

`pub fn sai1en(&self) -> SAI1EN_R`[src]

Bit 22 - SAI1 clock enable

`pub fn sai2en(&self) -> SAI2EN_R`[src]

Bit 23 - SAI2 clock enable

`pub fn sdmmc1en(&self) -> SDMMC1EN_R`[src]

Bit 11 - SDMMC1 clock enable

`pub fn sdmmc2en(&self) -> SDMMC2EN_R`[src]

Bit 7 - SDMMC2 clock enable

`pub fn usbphycen(&self) -> USBPHYCEN_R`[src]

Bit 31 - USB OTG HS PHY controller clock enable

`impl R<bool, GPIOALPEN_A>`[src]

`pub fn variant(&self) -> GPIOALPEN_A`[src]

Get enumerated values variant

`pub fn is_disabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is DISABLEDINSLEEP

`pub fn is_enabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is ENABLEDINSLEEP

`impl R<u32, Reg<u32, _AHB1LPENR>>`[src]

`pub fn gpioalpen(&self) -> GPIOALPEN_R`[src]

Bit 0 - IO port A clock enable during sleep mode

`pub fn gpioblpen(&self) -> GPIOBLPEN_R`[src]

Bit 1 - IO port B clock enable during Sleep mode

`pub fn gpioclpen(&self) -> GPIOCLPEN_R`[src]

Bit 2 - IO port C clock enable during Sleep mode

`pub fn gpiodlpen(&self) -> GPIODLPEN_R`[src]

Bit 3 - IO port D clock enable during Sleep mode

`pub fn gpioelpen(&self) -> GPIOELPEN_R`[src]

Bit 4 - IO port E clock enable during Sleep mode

`pub fn gpioflpen(&self) -> GPIOFLPEN_R`[src]

Bit 5 - IO port F clock enable during Sleep mode

`pub fn gpioglpen(&self) -> GPIOGLPEN_R`[src]

Bit 6 - IO port G clock enable during Sleep mode

`pub fn gpiohlpen(&self) -> GPIOHLPEN_R`[src]

Bit 7 - IO port H clock enable during Sleep mode

`pub fn gpioilpen(&self) -> GPIOILPEN_R`[src]

Bit 8 - IO port I clock enable during Sleep mode

`pub fn gpiojlpen(&self) -> GPIOJLPEN_R`[src]

Bit 9 - IO port J clock enable during Sleep mode

`pub fn gpioklpen(&self) -> GPIOKLPEN_R`[src]

Bit 10 - IO port K clock enable during Sleep mode

`pub fn crclpen(&self) -> CRCLPEN_R`[src]

Bit 12 - CRC clock enable during Sleep mode

`pub fn flitflpen(&self) -> FLITFLPEN_R`[src]

Bit 15 - Flash interface clock enable during Sleep mode

`pub fn sram1lpen(&self) -> SRAM1LPEN_R`[src]

Bit 16 - SRAM 1interface clock enable during Sleep mode

`pub fn sram2lpen(&self) -> SRAM2LPEN_R`[src]

Bit 17 - SRAM 2 interface clock enable during Sleep mode

`pub fn bkpsramlpen(&self) -> BKPSRAMLPEN_R`[src]

Bit 18 - Backup SRAM interface clock enable during Sleep mode

`pub fn sram3lpen(&self) -> SRAM3LPEN_R`[src]

Bit 19 - SRAM 3 interface clock enable during Sleep mode

`pub fn dma1lpen(&self) -> DMA1LPEN_R`[src]

Bit 21 - DMA1 clock enable during Sleep mode

`pub fn dma2lpen(&self) -> DMA2LPEN_R`[src]

Bit 22 - DMA2 clock enable during Sleep mode

`pub fn dma2dlpen(&self) -> DMA2DLPEN_R`[src]

Bit 23 - DMA2D clock enable during Sleep mode

`pub fn ethmaclpen(&self) -> ETHMACLPEN_R`[src]

Bit 25 - Ethernet MAC clock enable during Sleep mode

`pub fn ethmactxlpen(&self) -> ETHMACTXLPEN_R`[src]

Bit 26 - Ethernet transmission clock enable during Sleep mode

`pub fn ethmacrxlpen(&self) -> ETHMACRXLPEN_R`[src]

Bit 27 - Ethernet reception clock enable during Sleep mode

`pub fn ethmacptplpen(&self) -> ETHMACPTPLPEN_R`[src]

Bit 28 - Ethernet PTP clock enable during Sleep mode

`pub fn otghslpen(&self) -> OTGHSLPEN_R`[src]

Bit 29 - USB OTG HS clock enable during Sleep mode

`pub fn otghsulpilpen(&self) -> OTGHSULPILPEN_R`[src]

Bit 30 - USB OTG HS ULPI clock enable during Sleep mode

`pub fn axilpen(&self) -> AXILPEN_R`[src]

Bit 13 - AXI to AHB bridge clock enable during Sleep mode

`pub fn dtcmlpen(&self) -> DTCMLPEN_R`[src]

Bit 20 - DTCM RAM interface clock enable during Sleep mode

`impl R<bool, OTGFSLPEN_A>`[src]

`pub fn variant(&self) -> OTGFSLPEN_A`[src]

Get enumerated values variant

`pub fn is_disabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is DISABLEDINSLEEP

`pub fn is_enabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is ENABLEDINSLEEP

`impl R<u32, Reg<u32, _AHB2LPENR>>`[src]

`pub fn otgfslpen(&self) -> OTGFSLPEN_R`[src]

Bit 7 - USB OTG FS clock enable during Sleep mode

`pub fn rnglpen(&self) -> RNGLPEN_R`[src]

Bit 6 - Random number generator clock enable during Sleep mode

`pub fn aeslpen(&self) -> AESLPEN_R`[src]

Bit 4 - AES module clock enable during Sleep mode

`impl R<bool, FMCLPEN_A>`[src]

`pub fn variant(&self) -> FMCLPEN_A`[src]

Get enumerated values variant

`pub fn is_disabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is DISABLEDINSLEEP

`pub fn is_enabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is ENABLEDINSLEEP

`impl R<u32, Reg<u32, _AHB3LPENR>>`[src]

`pub fn fmclpen(&self) -> FMCLPEN_R`[src]

Bit 0 - Flexible memory controller module clock enable during Sleep mode

`pub fn qspilpen(&self) -> QSPILPEN_R`[src]

Bit 1 - Quand SPI memory controller clock enable during Sleep mode

`impl R<bool, TIM2LPEN_A>`[src]

`pub fn variant(&self) -> TIM2LPEN_A`[src]

Get enumerated values variant

`pub fn is_disabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is DISABLEDINSLEEP

`pub fn is_enabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is ENABLEDINSLEEP

`impl R<u32, Reg<u32, _APB1LPENR>>`[src]

`pub fn tim2lpen(&self) -> TIM2LPEN_R`[src]

Bit 0 - TIM2 clock enable during Sleep mode

`pub fn tim3lpen(&self) -> TIM3LPEN_R`[src]

Bit 1 - TIM3 clock enable during Sleep mode

`pub fn tim4lpen(&self) -> TIM4LPEN_R`[src]

Bit 2 - TIM4 clock enable during Sleep mode

`pub fn tim5lpen(&self) -> TIM5LPEN_R`[src]

Bit 3 - TIM5 clock enable during Sleep mode

`pub fn tim6lpen(&self) -> TIM6LPEN_R`[src]

Bit 4 - TIM6 clock enable during Sleep mode

`pub fn tim7lpen(&self) -> TIM7LPEN_R`[src]

Bit 5 - TIM7 clock enable during Sleep mode

`pub fn tim12lpen(&self) -> TIM12LPEN_R`[src]

Bit 6 - TIM12 clock enable during Sleep mode

`pub fn tim13lpen(&self) -> TIM13LPEN_R`[src]

Bit 7 - TIM13 clock enable during Sleep mode

`pub fn tim14lpen(&self) -> TIM14LPEN_R`[src]

Bit 8 - TIM14 clock enable during Sleep mode

`pub fn wwdglpen(&self) -> WWDGLPEN_R`[src]

Bit 11 - Window watchdog clock enable during Sleep mode

`pub fn spi2lpen(&self) -> SPI2LPEN_R`[src]

Bit 14 - SPI2 clock enable during Sleep mode

`pub fn spi3lpen(&self) -> SPI3LPEN_R`[src]

Bit 15 - SPI3 clock enable during Sleep mode

`pub fn usart2lpen(&self) -> USART2LPEN_R`[src]

Bit 17 - USART2 clock enable during Sleep mode

`pub fn usart3lpen(&self) -> USART3LPEN_R`[src]

Bit 18 - USART3 clock enable during Sleep mode

`pub fn uart4lpen(&self) -> UART4LPEN_R`[src]

Bit 19 - UART4 clock enable during Sleep mode

`pub fn uart5lpen(&self) -> UART5LPEN_R`[src]

Bit 20 - UART5 clock enable during Sleep mode

`pub fn i2c1lpen(&self) -> I2C1LPEN_R`[src]

Bit 21 - I2C1 clock enable during Sleep mode

`pub fn i2c2lpen(&self) -> I2C2LPEN_R`[src]

Bit 22 - I2C2 clock enable during Sleep mode

`pub fn i2c3lpen(&self) -> I2C3LPEN_R`[src]

Bit 23 - I2C3 clock enable during Sleep mode

`pub fn can1lpen(&self) -> CAN1LPEN_R`[src]

Bit 25 - CAN 1 clock enable during Sleep mode

`pub fn can2lpen(&self) -> CAN2LPEN_R`[src]

Bit 26 - CAN 2 clock enable during Sleep mode

`pub fn pwrlpen(&self) -> PWRLPEN_R`[src]

Bit 28 - Power interface clock enable during Sleep mode

`pub fn daclpen(&self) -> DACLPEN_R`[src]

Bit 29 - DAC interface clock enable during Sleep mode

`pub fn uart7lpen(&self) -> UART7LPEN_R`[src]

Bit 30 - UART7 clock enable during Sleep mode

`pub fn uart8lpen(&self) -> UART8LPEN_R`[src]

Bit 31 - UART8 clock enable during Sleep mode

`pub fn lptim1lpen(&self) -> LPTIM1LPEN_R`[src]

Bit 9 - low power timer 1 clock enable during Sleep mode

`impl R<bool, TIM1LPEN_A>`[src]

`pub fn variant(&self) -> TIM1LPEN_A`[src]

Get enumerated values variant

`pub fn is_disabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is DISABLEDINSLEEP

`pub fn is_enabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is ENABLEDINSLEEP

`impl R<u32, Reg<u32, _APB2LPENR>>`[src]

`pub fn tim1lpen(&self) -> TIM1LPEN_R`[src]

Bit 0 - TIM1 clock enable during Sleep mode

`pub fn tim8lpen(&self) -> TIM8LPEN_R`[src]

Bit 1 - TIM8 clock enable during Sleep mode

`pub fn usart1lpen(&self) -> USART1LPEN_R`[src]

Bit 4 - USART1 clock enable during Sleep mode

`pub fn usart6lpen(&self) -> USART6LPEN_R`[src]

Bit 5 - USART6 clock enable during Sleep mode

`pub fn adc1lpen(&self) -> ADC1LPEN_R`[src]

Bit 8 - ADC1 clock enable during Sleep mode

`pub fn adc2lpen(&self) -> ADC2LPEN_R`[src]

Bit 9 - ADC2 clock enable during Sleep mode

`pub fn adc3lpen(&self) -> ADC3LPEN_R`[src]

Bit 10 - ADC 3 clock enable during Sleep mode

`pub fn spi1lpen(&self) -> SPI1LPEN_R`[src]

Bit 12 - SPI 1 clock enable during Sleep mode

`pub fn spi4lpen(&self) -> SPI4LPEN_R`[src]

Bit 13 - SPI 4 clock enable during Sleep mode

`pub fn syscfglpen(&self) -> SYSCFGLPEN_R`[src]

Bit 14 - System configuration controller clock enable during Sleep mode

`pub fn tim9lpen(&self) -> TIM9LPEN_R`[src]

Bit 16 - TIM9 clock enable during sleep mode

`pub fn tim10lpen(&self) -> TIM10LPEN_R`[src]

Bit 17 - TIM10 clock enable during Sleep mode

`pub fn tim11lpen(&self) -> TIM11LPEN_R`[src]

Bit 18 - TIM11 clock enable during Sleep mode

`pub fn spi5lpen(&self) -> SPI5LPEN_R`[src]

Bit 20 - SPI 5 clock enable during Sleep mode

`pub fn sai1lpen(&self) -> SAI1LPEN_R`[src]

Bit 15 - RTC clock enable

`pub fn lsebyp(&self) -> LSEBYP_R`[src]

Bit 2 - External low-speed oscillator bypass

`pub fn lserdy(&self) -> LSERDY_R`[src]

Bit 1 - External low-speed oscillator ready

`pub fn lseon(&self) -> LSEON_R`[src]

Bit 0 - External low-speed oscillator enable

`pub fn lsedrv(&self) -> LSEDRV_R`[src]

Bits 3:4 - LSE oscillator drive capability

`pub fn rtcsel(&self) -> RTCSEL_R`[src]

Bits 8:9 - RTC clock source selection

`impl R<bool, LPWRRSTF_A>`[src]

`pub fn variant(&self) -> LPWRRSTF_A`[src]

`pub fn is_ready(&self) -> bool`[src]

Checks if the value of the field is READY

`impl R<bool, LSION_A>`[src]

`pub fn variant(&self) -> LSION_A`[src]

Get enumerated values variant

`pub fn is_off(&self) -> bool`[src]

Checks if the value of the field is OFF

`pub fn is_on(&self) -> bool`[src]

Checks if the value of the field is ON

`impl R<u32, Reg<u32, _CSR>>`[src]

`pub fn lpwrrstf(&self) -> LPWRRSTF_R`[src]

Bit 31 - Low-power reset flag

`pub fn wwdgrstf(&self) -> WWDGRSTF_R`[src]

Bit 30 - Window watchdog reset flag

`pub fn wdgrstf(&self) -> WDGRSTF_R`[src]

Bit 29 - Independent watchdog reset flag

`pub fn sftrstf(&self) -> SFTRSTF_R`[src]

Bit 28 - Software reset flag

`pub fn porrstf(&self) -> PORRSTF_R`[src]

Bit 27 - POR/PDR reset flag

`pub fn padrstf(&self) -> PADRSTF_R`[src]

Bit 26 - PIN reset flag

`pub fn borrstf(&self) -> BORRSTF_R`[src]

Bit 25 - BOR reset flag

`pub fn rmvf(&self) -> RMVF_R`[src]

Bit 24 - Remove reset flag

`pub fn lsirdy(&self) -> LSIRDY_R`[src]

Bit 1 - Internal low-speed oscillator ready

`pub fn lsion(&self) -> LSION_R`[src]

Bit 0 - Internal low-speed oscillator enable

`impl R<bool, SSCGEN_A>`[src]

`pub fn variant(&self) -> SSCGEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, SPREADSEL_A>`[src]

`pub fn variant(&self) -> SPREADSEL_A`[src]

Get enumerated values variant

`pub fn is_center(&self) -> bool`[src]

Checks if the value of the field is CENTER

`pub fn is_down(&self) -> bool`[src]

Checks if the value of the field is DOWN

`impl R<u32, Reg<u32, _SSCGR>>`[src]

`pub fn sscgen(&self) -> SSCGEN_R`[src]

Bit 31 - Spread spectrum modulation enable

`pub fn spreadsel(&self) -> SPREADSEL_R`[src]

Bit 30 - Spread Select

`pub fn incstep(&self) -> INCSTEP_R`[src]

Bits 13:27 - Incrementation step

`pub fn modper(&self) -> MODPER_R`[src]

Bits 0:12 - Modulation period

`impl R<u32, Reg<u32, _PLLI2SCFGR>>`[src]

`pub fn plli2sr(&self) -> PLLI2SR_R`[src]

Bits 28:30 - PLLI2S division factor for I2S clocks

`pub fn plli2sq(&self) -> PLLI2SQ_R`[src]

Bits 24:27 - PLLI2S division factor for SAI1 clock

`pub fn plli2sn(&self) -> PLLI2SN_R`[src]

Bits 6:14 - PLLI2S multiplication factor for VCO

`impl R<u8, PLLSAIP_A>`[src]

`pub fn variant(&self) -> PLLSAIP_A`[src]

Get enumerated values variant

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div6(&self) -> bool`[src]

Checks if the value of the field is DIV6

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u32, Reg<u32, _PLLSAICFGR>>`[src]

`pub fn pllsain(&self) -> PLLSAIN_R`[src]

Bits 6:14 - PLLSAI division factor for VCO

`pub fn pllsaip(&self) -> PLLSAIP_R`[src]

Bits 16:17 - PLLSAI division factor for 48MHz clock

`pub fn pllsaiq(&self) -> PLLSAIQ_R`[src]

Bits 24:27 - PLLSAI division factor for SAI clock

`impl R<u8, PLLI2SDIVQ_A>`[src]

`pub fn variant(&self) -> PLLI2SDIVQ_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div3(&self) -> bool`[src]

Checks if the value of the field is DIV3

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div5(&self) -> bool`[src]

Checks if the value of the field is DIV5

`pub fn is_div6(&self) -> bool`[src]

Checks if the value of the field is DIV6

`pub fn is_div7(&self) -> bool`[src]

Checks if the value of the field is DIV7

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div9(&self) -> bool`[src]

Checks if the value of the field is DIV9

`pub fn is_div10(&self) -> bool`[src]

Checks if the value of the field is DIV10

`pub fn is_div11(&self) -> bool`[src]

Checks if the value of the field is DIV11

`pub fn is_div12(&self) -> bool`[src]

Checks if the value of the field is DIV12

`pub fn is_div13(&self) -> bool`[src]

Checks if the value of the field is DIV13

`pub fn is_div14(&self) -> bool`[src]

Checks if the value of the field is DIV14

`pub fn is_div15(&self) -> bool`[src]

Checks if the value of the field is DIV15

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`pub fn is_div17(&self) -> bool`[src]

Checks if the value of the field is DIV17

`pub fn is_div18(&self) -> bool`[src]

Checks if the value of the field is DIV18

`pub fn is_div19(&self) -> bool`[src]

Checks if the value of the field is DIV19

`pub fn is_div20(&self) -> bool`[src]

Checks if the value of the field is DIV20

`pub fn is_div21(&self) -> bool`[src]

Checks if the value of the field is DIV21

`pub fn is_div22(&self) -> bool`[src]

Checks if the value of the field is DIV22

`pub fn is_div23(&self) -> bool`[src]

Checks if the value of the field is DIV23

`pub fn is_div24(&self) -> bool`[src]

Checks if the value of the field is DIV24

`pub fn is_div25(&self) -> bool`[src]

Checks if the value of the field is DIV25

`pub fn is_div26(&self) -> bool`[src]

Checks if the value of the field is DIV26

`pub fn is_div27(&self) -> bool`[src]

Checks if the value of the field is DIV27

`pub fn is_div28(&self) -> bool`[src]

Checks if the value of the field is DIV28

`pub fn is_div29(&self) -> bool`[src]

Checks if the value of the field is DIV29

`pub fn is_div30(&self) -> bool`[src]

Checks if the value of the field is DIV30

`pub fn is_div31(&self) -> bool`[src]

Checks if the value of the field is DIV31

`pub fn is_div32(&self) -> bool`[src]

Checks if the value of the field is DIV32

`impl R<u8, PLLSAIDIVQ_A>`[src]

`pub fn variant(&self) -> PLLSAIDIVQ_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div3(&self) -> bool`[src]

Checks if the value of the field is DIV3

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div5(&self) -> bool`[src]

Checks if the value of the field is DIV5

`pub fn is_div6(&self) -> bool`[src]

Checks if the value of the field is DIV6

`pub fn is_div7(&self) -> bool`[src]

Checks if the value of the field is DIV7

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div9(&self) -> bool`[src]

Checks if the value of the field is DIV9

`pub fn is_div10(&self) -> bool`[src]

Checks if the value of the field is DIV10

`pub fn is_div11(&self) -> bool`[src]

Checks if the value of the field is DIV11

`pub fn is_div12(&self) -> bool`[src]

Checks if the value of the field is DIV12

`pub fn is_div13(&self) -> bool`[src]

Checks if the value of the field is DIV13

`pub fn is_div14(&self) -> bool`[src]

Checks if the value of the field is DIV14

`pub fn is_div15(&self) -> bool`[src]

Checks if the value of the field is DIV15

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`pub fn is_div17(&self) -> bool`[src]

Checks if the value of the field is DIV17

`pub fn is_div18(&self) -> bool`[src]

Checks if the value of the field is DIV18

`pub fn is_div19(&self) -> bool`[src]

Checks if the value of the field is DIV19

`pub fn is_div20(&self) -> bool`[src]

Checks if the value of the field is DIV20

`pub fn is_div21(&self) -> bool`[src]

Checks if the value of the field is DIV21

`pub fn is_div22(&self) -> bool`[src]

Checks if the value of the field is DIV22

`pub fn is_div23(&self) -> bool`[src]

Checks if the value of the field is DIV23

`pub fn is_div24(&self) -> bool`[src]

Checks if the value of the field is DIV24

`pub fn is_div25(&self) -> bool`[src]

Checks if the value of the field is DIV25

`pub fn is_div26(&self) -> bool`[src]

Checks if the value of the field is DIV26

`pub fn is_div27(&self) -> bool`[src]

Checks if the value of the field is DIV27

`pub fn is_div28(&self) -> bool`[src]

Checks if the value of the field is DIV28

`pub fn is_div29(&self) -> bool`[src]

Checks if the value of the field is DIV29

`pub fn is_div30(&self) -> bool`[src]

Checks if the value of the field is DIV30

`pub fn is_div31(&self) -> bool`[src]

Checks if the value of the field is DIV31

`pub fn is_div32(&self) -> bool`[src]

Checks if the value of the field is DIV32

`impl R<u8, SAI1SEL_A>`[src]

`pub fn variant(&self) -> SAI1SEL_A`[src]

Get enumerated values variant

`pub fn is_pllsai(&self) -> bool`[src]

Checks if the value of the field is PLLSAI

`pub fn is_plli2s(&self) -> bool`[src]

Checks if the value of the field is PLLI2S

`pub fn is_afif(&self) -> bool`[src]

Checks if the value of the field is AFIF

`pub fn is_hsi_hse(&self) -> bool`[src]

Checks if the value of the field is HSI_HSE

`impl R<u8, SAI2SEL_A>`[src]

`pub fn variant(&self) -> SAI2SEL_A`[src]

Get enumerated values variant

`pub fn is_pllsai(&self) -> bool`[src]

Checks if the value of the field is PLLSAI

`pub fn is_plli2s(&self) -> bool`[src]

Checks if the value of the field is PLLI2S

`pub fn is_afif(&self) -> bool`[src]

Checks if the value of the field is AFIF

`pub fn is_hsi_hse(&self) -> bool`[src]

Checks if the value of the field is HSI_HSE

`pub fn is_lse(&self) -> bool`[src]

Checks if the value of the field is LSE

`impl R<bool, CK48MSEL_A>`[src]

`pub fn variant(&self) -> CK48MSEL_A`[src]

Get enumerated values variant

`pub fn is_pll(&self) -> bool`[src]

Checks if the value of the field is PLL

`pub fn is_pllsai(&self) -> bool`[src]

Checks if the value of the field is PLLSAI

`impl R<bool, SDMMC1SEL_A>`[src]

`pub fn variant(&self) -> SDMMC1SEL_A`[src]

Get enumerated values variant

`pub fn is_ck48m(&self) -> bool`[src]

Checks if the value of the field is CK48M

`pub fn is_sysclk(&self) -> bool`[src]

Checks if the value of the field is SYSCLK

`impl R<u32, Reg<u32, _DCKCFGR2>>`[src]

`pub fn usart1sel(&self) -> USART1SEL_R`[src]

Bits 0:1 - USART 1 clock source selection

`pub fn usart2sel(&self) -> USART2SEL_R`[src]

Bits 2:3 - USART 2 clock source selection

`pub fn usart3sel(&self) -> USART3SEL_R`[src]

Bits 4:5 - USART 3 clock source selection

`pub fn uart4sel(&self) -> UART4SEL_R`[src]

Bits 6:7 - UART 4 clock source selection

`pub fn uart5sel(&self) -> UART5SEL_R`[src]

Bits 8:9 - UART 5 clock source selection

`pub fn usart6sel(&self) -> USART6SEL_R`[src]

Bits 10:11 - USART 6 clock source selection

`pub fn uart7sel(&self) -> UART7SEL_R`[src]

Bits 12:13 - UART 7 clock source selection

`pub fn uart8sel(&self) -> UART8SEL_R`[src]

Bits 14:15 - UART 8 clock source selection

`pub fn i2c1sel(&self) -> I2C1SEL_R`[src]

Bits 16:17 - I2C1 clock source selection

`pub fn i2c2sel(&self) -> I2C2SEL_R`[src]

Bits 18:19 - I2C2 clock source selection

`pub fn i2c3sel(&self) -> I2C3SEL_R`[src]

Bits 20:21 - I2C3 clock source selection

`pub fn lptim1sel(&self) -> LPTIM1SEL_R`[src]

Bits 24:25 - Low power timer 1 clock source selection

`pub fn ck48msel(&self) -> CK48MSEL_R`[src]

Bit 27 - 48MHz clock source selection

`pub fn sdmmc1sel(&self) -> SDMMC1SEL_R`[src]

Bit 28 - SDMMC1 clock source selection

`pub fn sdmmc2sel(&self) -> SDMMC2SEL_R`[src]

Bit 29 - SDMMC2 clock source selection

`impl R<u32, Reg<u32, _POWER>>`[src]

`pub fn pwrctrl(&self) -> PWRCTRL_R`[src]

Bits 0:1 - PWRCTRL

`impl R<u32, Reg<u32, _CLKCR>>`[src]

`pub fn hwfc_en(&self) -> HWFC_EN_R`[src]

Bit 14 - HW Flow Control enable

`pub fn negedge(&self) -> NEGEDGE_R`[src]

Bit 13 - SDIO_CK dephasing selection bit

`pub fn widbus(&self) -> WIDBUS_R`[src]

Bits 11:12 - Wide bus mode enable bit

`pub fn bypass(&self) -> BYPASS_R`[src]

Bit 10 - Clock divider bypass enable bit

`pub fn pwrsav(&self) -> PWRSAV_R`[src]

Bit 9 - Power saving configuration bit

`pub fn clken(&self) -> CLKEN_R`[src]

Bit 8 - Clock enable bit

`pub fn clkdiv(&self) -> CLKDIV_R`[src]

Bits 0:7 - Clock divide factor

`impl R<u32, Reg<u32, _ARG>>`[src]

`pub fn cmdarg(&self) -> CMDARG_R`[src]

Bits 0:31 - Command argument

`impl R<u32, Reg<u32, _CMD>>`[src]

`pub fn sdiosuspend(&self) -> SDIOSUSPEND_R`[src]

Bit 11 - SD I/O suspend command

`pub fn cpsmen(&self) -> CPSMEN_R`[src]

Bit 10 - Command path state machine (CPSM) Enable bit

`pub fn waitpend(&self) -> WAITPEND_R`[src]

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)

`pub fn waitint(&self) -> WAITINT_R`[src]

Bit 8 - CPSM waits for interrupt request

`pub fn waitresp(&self) -> WAITRESP_R`[src]

`impl R<u32, Reg<u32, _DCTRL>>`[src]

`pub fn sdioen(&self) -> SDIOEN_R`[src]

Bit 11 - SD I/O enable functions

`pub fn rwmod(&self) -> RWMOD_R`[src]

Bit 10 - Read wait mode

`pub fn rwstop(&self) -> RWSTOP_R`[src]

Bit 9 - Read wait stop

`pub fn rwstart(&self) -> RWSTART_R`[src]

Bit 8 - Read wait start

`pub fn dblocksize(&self) -> DBLOCKSIZE_R`[src]

Bits 4:7 - Data block size

`pub fn dmaen(&self) -> DMAEN_R`[src]

Bit 3 - DMA enable bit

`pub fn dtmode(&self) -> DTMODE_R`[src]

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer

`pub fn dtdir(&self) -> DTDIR_R`[src]

Bit 1 - Data transfer direction selection

`pub fn dten(&self) -> DTEN_R`[src]

Bit 0 - DTEN

`impl R<u32, Reg<u32, _DCOUNT>>`[src]

`pub fn datacount(&self) -> DATACOUNT_R`[src]

Bits 0:24 - Data count value

`impl R<u32, Reg<u32, _STA>>`[src]

`pub fn sdioit(&self) -> SDIOIT_R`[src]

Bit 22 - SDIO interrupt received

`pub fn rxdavl(&self) -> RXDAVL_R`[src]

Bit 21 - Data available in receive FIFO

`pub fn txdavl(&self) -> TXDAVL_R`[src]

Bit 20 - Data available in transmit FIFO

`pub fn rxfifoe(&self) -> RXFIFOE_R`[src]

Bit 19 - Receive FIFO empty

`pub fn txfifoe(&self) -> TXFIFOE_R`[src]

Bit 18 - Transmit FIFO empty

`pub fn rxfifof(&self) -> RXFIFOF_R`[src]

Bit 17 - Receive FIFO full

`pub fn txfifof(&self) -> TXFIFOF_R`[src]

Bit 16 - Transmit FIFO full

`pub fn rxfifohf(&self) -> RXFIFOHF_R`[src]

Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO

`pub fn txfifohe(&self) -> TXFIFOHE_R`[src]

Bit 14 - Transmit FIFO half empty: at least 8 words can be written into the FIFO

`pub fn rxact(&self) -> RXACT_R`[src]

Bit 13 - Data receive in progress

`pub fn txact(&self) -> TXACT_R`[src]

Bit 12 - Data transmit in progress

`pub fn cmdact(&self) -> CMDACT_R`[src]

Bit 11 - Command transfer in progress

`pub fn dbckend(&self) -> DBCKEND_R`[src]

Bit 10 - Data block sent/received (CRC check passed)

`pub fn dataend(&self) -> DATAEND_R`[src]

Bit 8 - Data end (data counter, SDIDCOUNT, is zero)

`pub fn cmdsent(&self) -> CMDSENT_R`[src]

Bit 7 - Command sent (no response required)

`pub fn cmdrend(&self) -> CMDREND_R`[src]

Bit 6 - Command response received (CRC check passed)

`pub fn rxoverr(&self) -> RXOVERR_R`[src]

Bit 5 - Received FIFO overrun error

`pub fn txunderr(&self) -> TXUNDERR_R`[src]

Bit 4 - Transmit FIFO underrun error

`pub fn dtimeout(&self) -> DTIMEOUT_R`[src]

Bit 3 - Data timeout

`pub fn ctimeout(&self) -> CTIMEOUT_R`[src]

Bit 2 - Command response timeout

`pub fn dcrcfail(&self) -> DCRCFAIL_R`[src]

Bit 1 - Data block sent/received (CRC check failed)

`pub fn ccrcfail(&self) -> CCRCFAIL_R`[src]

Bit 0 - Command response received (CRC check failed)

`impl R<u32, Reg<u32, _ICR>>`[src]

`pub fn sdioitc(&self) -> SDIOITC_R`[src]

Bit 22 - SDIOIT flag clear bit

`pub fn dbckendc(&self) -> DBCKENDC_R`[src]

Bit 10 - DBCKEND flag clear bit

`pub fn dataendc(&self) -> DATAENDC_R`[src]

Bit 8 - DATAEND flag clear bit

`pub fn cmdsentc(&self) -> CMDSENTC_R`[src]

Bit 7 - CMDSENT flag clear bit

`pub fn cmdrendc(&self) -> CMDRENDC_R`[src]

Bit 6 - CMDREND flag clear bit

`pub fn rxoverrc(&self) -> RXOVERRC_R`[src]

Bit 5 - RXOVERR flag clear bit

`pub fn txunderrc(&self) -> TXUNDERRC_R`[src]

Bit 4 - TXUNDERR flag clear bit

`pub fn dtimeoutc(&self) -> DTIMEOUTC_R`[src]

Bit 3 - DTIMEOUT flag clear bit

`pub fn ctimeoutc(&self) -> CTIMEOUTC_R`[src]

Bit 2 - CTIMEOUT flag clear bit

`pub fn dcrcfailc(&self) -> DCRCFAILC_R`[src]

Bit 1 - DCRCFAIL flag clear bit

`pub fn ccrcfailc(&self) -> CCRCFAILC_R`[src]

Bit 0 - CCRCFAIL flag clear bit

`impl R<u32, Reg<u32, _MASK>>`[src]

`pub fn sdioitie(&self) -> SDIOITIE_R`[src]

Bit 22 - SDIO mode interrupt received interrupt enable

`pub fn rxdavlie(&self) -> RXDAVLIE_R`[src]

Bit 21 - Data available in Rx FIFO interrupt enable

`pub fn txdavlie(&self) -> TXDAVLIE_R`[src]

Bit 20 - Data available in Tx FIFO interrupt enable

`pub fn rxfifoeie(&self) -> RXFIFOEIE_R`[src]

Bit 19 - Rx FIFO empty interrupt enable

`pub fn txfifoeie(&self) -> TXFIFOEIE_R`[src]

Bit 18 - Tx FIFO empty interrupt enable

`pub fn rxfifofie(&self) -> RXFIFOFIE_R`[src]

Bit 17 - Rx FIFO full interrupt enable

`pub fn txfifofie(&self) -> TXFIFOFIE_R`[src]

Bit 16 - Tx FIFO full interrupt enable

`pub fn rxfifohfie(&self) -> RXFIFOHFIE_R`[src]

Bit 15 - Rx FIFO half full interrupt enable

`pub fn txfifoheie(&self) -> TXFIFOHEIE_R`[src]

Bit 14 - Tx FIFO half empty interrupt enable

`pub fn rxactie(&self) -> RXACTIE_R`[src]

Bit 13 - Data receive acting interrupt enable

`pub fn txactie(&self) -> TXACTIE_R`[src]

Bit 12 - Data transmit acting interrupt enable

`pub fn cmdactie(&self) -> CMDACTIE_R`[src]

Bit 11 - Command acting interrupt enable

`pub fn dbckendie(&self) -> DBCKENDIE_R`[src]

Bit 10 - Data block end interrupt enable

`pub fn dataendie(&self) -> DATAENDIE_R`[src]

Bit 8 - Data end interrupt enable

`pub fn cmdsentie(&self) -> CMDSENTIE_R`[src]

Bit 7 - Command sent interrupt enable

`pub fn cmdrendie(&self) -> CMDRENDIE_R`[src]

Bit 6 - Command response received interrupt enable

`pub fn rxoverrie(&self) -> RXOVERRIE_R`[src]

Bit 5 - Rx FIFO overrun error interrupt enable

`pub fn txunderrie(&self) -> TXUNDERRIE_R`[src]

Bit 4 - Tx FIFO underrun error interrupt enable

`pub fn dtimeoutie(&self) -> DTIMEOUTIE_R`[src]

Bit 3 - Data timeout interrupt enable

`pub fn ctimeoutie(&self) -> CTIMEOUTIE_R`[src]

Bit 2 - Command timeout interrupt enable

`pub fn dcrcfailie(&self) -> DCRCFAILIE_R`[src]

Bit 1 - Data CRC fail interrupt enable

`pub fn ccrcfailie(&self) -> CCRCFAILIE_R`[src]

Bit 0 - Command CRC fail interrupt enable

`impl R<u32, Reg<u32, _FIFOCNT>>`[src]

`pub fn fifocount(&self) -> FIFOCOUNT_R`[src]

Bits 0:23 - Remaining number of words to be written to or read from the FIFO

Checks if the value of the field is ASYNCHRONOUS

`pub fn is_internal(&self) -> bool`[src]

Checks if the value of the field is INTERNAL

`pub fn is_external(&self) -> bool`[src]

Checks if the value of the field is EXTERNAL

`impl R<bool, CKSTR_A>`[src]

`pub fn variant(&self) -> CKSTR_A`[src]

Get enumerated values variant

`pub fn is_falling_edge(&self) -> bool`[src]

Checks if the value of the field is FALLINGEDGE

`pub fn is_rising_edge(&self) -> bool`[src]

Checks if the value of the field is RISINGEDGE

`impl R<bool, LSBFIRST_A>`[src]

`pub fn variant(&self) -> LSBFIRST_A`[src]

Get enumerated values variant

`pub fn is_msb_first(&self) -> bool`[src]

Checks if the value of the field is MSBFIRST

`pub fn is_lsb_first(&self) -> bool`[src]

Checks if the value of the field is LSBFIRST

`impl R<u8, DS_A>`[src]

`pub fn variant(&self) -> Variant<u8, DS_A>`[src]

Get enumerated values variant

`pub fn is_bit8(&self) -> bool`[src]

Checks if the value of the field is BIT8

`pub fn is_bit10(&self) -> bool`[src]

Checks if the value of the field is BIT10

`pub fn is_bit16(&self) -> bool`[src]

Checks if the value of the field is BIT16

`pub fn is_bit20(&self) -> bool`[src]

Checks if the value of the field is BIT20

`pub fn is_bit24(&self) -> bool`[src]

Checks if the value of the field is BIT24

`pub fn is_bit32(&self) -> bool`[src]

Checks if the value of the field is BIT32

`impl R<u8, PRTCFG_A>`[src]

`pub fn variant(&self) -> Variant<u8, PRTCFG_A>`[src]

Get enumerated values variant

`pub fn is_free(&self) -> bool`[src]

Checks if the value of the field is FREE

`pub fn is_spdif(&self) -> bool`[src]

Checks if the value of the field is SPDIF

`pub fn is_ac97(&self) -> bool`[src]

Checks if the value of the field is AC97

`impl R<u8, MODE_A>`[src]

`pub fn variant(&self) -> MODE_A`[src]

Get enumerated values variant

`pub fn is_master_tx(&self) -> bool`[src]

Checks if the value of the field is MASTERTX

`pub fn is_master_rx(&self) -> bool`[src]

Checks if the value of the field is MASTERRX

`pub fn is_slave_tx(&self) -> bool`[src]

Checks if the value of the field is SLAVETX

`pub fn is_slave_rx(&self) -> bool`[src]

Checks if the value of the field is SLAVERX

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn mckdiv(&self) -> MCKDIV_R`[src]

Bits 20:23 - Master clock divider

`pub fn nodiv(&self) -> NODIV_R`[src]

Bit 19 - No divider

`pub fn dmaen(&self) -> DMAEN_R`[src]

Bit 17 - DMA enable

`pub fn saien(&self) -> SAIEN_R`[src]

Bit 16 - Audio block A enable

`pub fn outdriv(&self) -> OUTDRIV_R`[src]

Bit 13 - Output drive

`pub fn mono(&self) -> MONO_R`[src]

Bit 12 - Mono mode

`pub fn syncen(&self) -> SYNCEN_R`[src]

Bits 10:11 - Synchronization enable

`pub fn ckstr(&self) -> CKSTR_R`[src]

Bit 9 - Clock strobing edge

`pub fn lsbfirst(&self) -> LSBFIRST_R`[src]

Bit 8 - Least significant bit first

`pub fn ds(&self) -> DS_R`[src]

Bits 5:7 - Data size

`pub fn prtcfg(&self) -> PRTCFG_R`[src]

Bits 2:3 - Protocol configuration

`pub fn mode(&self) -> MODE_R`[src]

Bits 0:1 - Audio block mode

`impl R<u8, COMP_A>`[src]

`pub fn variant(&self) -> Variant<u8, COMP_A>`[src]

`pub fn is_quarter2(&self) -> bool`[src]

Checks if the value of the field is QUARTER2

`pub fn is_quarter3(&self) -> bool`[src]

Checks if the value of the field is QUARTER3

`pub fn is_full(&self) -> bool`[src]

Checks if the value of the field is FULL

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn comp(&self) -> COMP_R`[src]

Bits 14:15 - Companding mode

`pub fn cpl(&self) -> CPL_R`[src]

Bit 13 - Complement bit

`pub fn mutecn(&self) -> MUTECN_R`[src]

Bits 7:12 - Mute counter

`pub fn muteval(&self) -> MUTEVAL_R`[src]

Bit 6 - Mute value

`pub fn mute(&self) -> MUTE_R`[src]

Bit 5 - Mute

`pub fn tris(&self) -> TRIS_R`[src]

Bit 4 - Tristate management on data line

`pub fn fflush(&self) -> FFLUSH_R`[src]

Bit 3 - FIFO flush

`pub fn fth(&self) -> FTH_R`[src]

Bits 0:2 - FIFO threshold

`impl R<bool, FSOFF_A>`[src]

`pub fn variant(&self) -> FSOFF_A`[src]

Get enumerated values variant

`pub fn is_on_first(&self) -> bool`[src]

Checks if the value of the field is ONFIRST

`pub fn is_before_first(&self) -> bool`[src]

Checks if the value of the field is BEFOREFIRST

`impl R<bool, FSPOL_A>`[src]

`pub fn variant(&self) -> FSPOL_A`[src]

Get enumerated values variant

`pub fn is_falling_edge(&self) -> bool`[src]

Checks if the value of the field is FALLINGEDGE

`pub fn is_rising_edge(&self) -> bool`[src]

Checks if the value of the field is RISINGEDGE

`impl R<u32, Reg<u32, _FRCR>>`[src]

`pub fn fsoff(&self) -> FSOFF_R`[src]

Bit 18 - Frame synchronization offset

`pub fn fspol(&self) -> FSPOL_R`[src]

Bit 17 - Frame synchronization polarity

`pub fn fsdef(&self) -> FSDEF_R`[src]

Bit 16 - Frame synchronization definition

`pub fn fsall(&self) -> FSALL_R`[src]

Bits 8:14 - Frame synchronization active level length

`pub fn frl(&self) -> FRL_R`[src]

Bits 0:7 - Frame length

`impl R<u16, SLOTEN_A>`[src]

`pub fn variant(&self) -> Variant<u16, SLOTEN_A>`[src]

Get enumerated values variant

`pub fn is_inactive(&self) -> bool`[src]

Checks if the value of the field is INACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<u8, SLOTSZ_A>`[src]

`pub fn variant(&self) -> Variant<u8, SLOTSZ_A>`[src]

Get enumerated values variant

`pub fn is_data_size(&self) -> bool`[src]

Checks if the value of the field is DATASIZE

`pub fn is_bit16(&self) -> bool`[src]

Checks if the value of the field is BIT16

`pub fn is_bit32(&self) -> bool`[src]

Checks if the value of the field is BIT32

`impl R<u32, Reg<u32, _SLOTR>>`[src]

`pub fn sloten(&self) -> SLOTEN_R`[src]

`impl R<u32, Reg<u32, _IM>>`[src]

`pub fn lfsdetie(&self) -> LFSDETIE_R`[src]

Bit 6 - Late frame synchronization detection interrupt enable

`pub fn afsdetie(&self) -> AFSDETIE_R`[src]

Bit 5 - Anticipated frame synchronization detection interrupt enable

`pub fn cnrdyie(&self) -> CNRDYIE_R`[src]

Bit 4 - Codec not ready interrupt enable

`pub fn freqie(&self) -> FREQIE_R`[src]

Bit 3 - FIFO request interrupt enable

`pub fn wckcfgie(&self) -> WCKCFGIE_R`[src]

Bit 2 - Wrong clock configuration interrupt enable

`pub fn mutedetie(&self) -> MUTEDETIE_R`[src]

Bit 1 - Mute detection interrupt enable

`pub fn ovrudrie(&self) -> OVRUDRIE_R`[src]

Bit 0 - Overrun/underrun interrupt enable

`impl R<u8, FLVL_A>`[src]

`pub fn variant(&self) -> Variant<u8, FLVL_A>`[src]

Get enumerated values variant

`pub fn is_empty(&self) -> bool`[src]

Checks if the value of the field is EMPTY

`pub fn is_quarter1(&self) -> bool`[src]

Checks if the value of the field is QUARTER1

`pub fn is_quarter2(&self) -> bool`[src]

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn flvl(&self) -> FLVL_R`[src]

Bits 16:18 - FIFO level threshold

`pub fn lfsdet(&self) -> LFSDET_R`[src]

Bit 6 - Late frame synchronization detection

`pub fn afsdet(&self) -> AFSDET_R`[src]

Bit 5 - Anticipated frame synchronization detection

`pub fn cnrdy(&self) -> CNRDY_R`[src]

Bit 4 - Codec not ready

`pub fn freq(&self) -> FREQ_R`[src]

Bit 3 - FIFO request

`pub fn wckcfg(&self) -> WCKCFG_R`[src]

Bit 2 - Wrong clock configuration flag. This bit is read only.

`pub fn mutedet(&self) -> MUTEDET_R`[src]

Bit 1 - Mute detection

`pub fn ovrudr(&self) -> OVRUDR_R`[src]

Bit 0 - Overrun / underrun

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn data(&self) -> DATA_R`[src]

Bits 0:31 - Data

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, BR_A>`[src]

`pub fn variant(&self) -> BR_A`[src]

Get enumerated values variant

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`pub fn is_div32(&self) -> bool`[src]

Checks if the value of the field is DIV32

`pub fn is_div64(&self) -> bool`[src]

Checks if the value of the field is DIV64

`pub fn is_div128(&self) -> bool`[src]

Checks if the value of the field is DIV128

`pub fn is_div256(&self) -> bool`[src]

Checks if the value of the field is DIV256

`impl R<bool, MSTR_A>`[src]

`pub fn variant(&self) -> MSTR_A`[src]

Get enumerated values variant

`pub fn is_slave(&self) -> bool`[src]

Checks if the value of the field is SLAVE

`pub fn is_master(&self) -> bool`[src]

Checks if the value of the field is MASTER

`impl R<bool, CPOL_A>`[src]

`pub fn variant(&self) -> CPOL_A`[src]

Get enumerated values variant

`pub fn is_idle_low(&self) -> bool`[src]

Checks if the value of the field is IDLELOW

`pub fn is_idle_high(&self) -> bool`[src]

Checks if the value of the field is IDLEHIGH

`impl R<bool, CPHA_A>`[src]

`pub fn variant(&self) -> CPHA_A`[src]

Get enumerated values variant

`pub fn is_first_edge(&self) -> bool`[src]

Checks if the value of the field is FIRSTEDGE

`pub fn is_second_edge(&self) -> bool`[src]

Checks if the value of the field is SECONDEDGE

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn bidimode(&self) -> BIDIMODE_R`[src]

Bit 15 - Bidirectional data mode enable

`pub fn bidioe(&self) -> BIDIOE_R`[src]

Bit 14 - Output enable in bidirectional mode

`pub fn crcen(&self) -> CRCEN_R`[src]

Bit 13 - Hardware CRC calculation enable

`pub fn crcnext(&self) -> CRCNEXT_R`[src]

Bit 12 - CRC transfer next

`pub fn crcl(&self) -> CRCL_R`[src]

Bit 11 - CRC length

`pub fn rxonly(&self) -> RXONLY_R`[src]

Bit 10 - Receive only

`pub fn ssm(&self) -> SSM_R`[src]

Bit 9 - Software slave management

`pub fn ssi(&self) -> SSI_R`[src]

Bit 8 - Internal slave select

`pub fn lsbfirst(&self) -> LSBFIRST_R`[src]

Bit 7 - Frame format

`pub fn spe(&self) -> SPE_R`[src]

Bit 6 - SPI enable

`pub fn br(&self) -> BR_R`[src]

`pub fn is_six_bit(&self) -> bool`[src]

Checks if the value of the field is SIXBIT

`pub fn is_seven_bit(&self) -> bool`[src]

Checks if the value of the field is SEVENBIT

`pub fn is_eight_bit(&self) -> bool`[src]

Checks if the value of the field is EIGHTBIT

`pub fn is_nine_bit(&self) -> bool`[src]

Checks if the value of the field is NINEBIT

`pub fn is_ten_bit(&self) -> bool`[src]

Checks if the value of the field is TENBIT

`pub fn is_eleven_bit(&self) -> bool`[src]

Checks if the value of the field is ELEVENBIT

`pub fn is_twelve_bit(&self) -> bool`[src]

Checks if the value of the field is TWELVEBIT

`pub fn is_thirteen_bit(&self) -> bool`[src]

Checks if the value of the field is THIRTEENBIT

`pub fn is_fourteen_bit(&self) -> bool`[src]

Checks if the value of the field is FOURTEENBIT

`pub fn is_fifteen_bit(&self) -> bool`[src]

Checks if the value of the field is FIFTEENBIT

`pub fn is_sixteen_bit(&self) -> bool`[src]

Checks if the value of the field is SIXTEENBIT

`impl R<bool, FRXTH_A>`[src]

`pub fn variant(&self) -> FRXTH_A`[src]

Get enumerated values variant

`pub fn is_half(&self) -> bool`[src]

Checks if the value of the field is HALF

`pub fn is_quarter(&self) -> bool`[src]

Checks if the value of the field is QUARTER

`impl R<bool, LDMA_RX_A>`[src]

`pub fn variant(&self) -> LDMA_RX_A`[src]

Get enumerated values variant

`pub fn is_even(&self) -> bool`[src]

Checks if the value of the field is EVEN

`pub fn is_odd(&self) -> bool`[src]

Checks if the value of the field is ODD

`impl R<bool, LDMA_TX_A>`[src]

`pub fn variant(&self) -> LDMA_TX_A`[src]

Get enumerated values variant

`pub fn is_even(&self) -> bool`[src]

Checks if the value of the field is EVEN

`pub fn is_odd(&self) -> bool`[src]

Checks if the value of the field is ODD

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn rxdmaen(&self) -> RXDMAEN_R`[src]

Bit 0 - Rx buffer DMA enable

`pub fn txdmaen(&self) -> TXDMAEN_R`[src]

Bit 1 - Tx buffer DMA enable

`pub fn ssoe(&self) -> SSOE_R`[src]

Bit 2 - SS output enable

`pub fn nssp(&self) -> NSSP_R`[src]

Bit 3 - NSS pulse management

`pub fn frf(&self) -> FRF_R`[src]

Bit 4 - Frame format

`pub fn errie(&self) -> ERRIE_R`[src]

Bit 5 - Error interrupt enable

`pub fn rxneie(&self) -> RXNEIE_R`[src]

Bit 6 - RX buffer not empty interrupt enable

`pub fn txeie(&self) -> TXEIE_R`[src]

Bit 7 - Tx buffer empty interrupt enable

`pub fn ds(&self) -> DS_R`[src]

Bit 7 - Busy flag

`pub fn ovr(&self) -> OVR_R`[src]

Bit 6 - Overrun flag

`pub fn modf(&self) -> MODF_R`[src]

Bit 5 - Mode fault

`pub fn crcerr(&self) -> CRCERR_R`[src]

Bit 4 - CRC error flag

`pub fn udr(&self) -> UDR_R`[src]

Bit 3 - Underrun flag

`pub fn chside(&self) -> CHSIDE_R`[src]

Bit 2 - Channel side

`pub fn txe(&self) -> TXE_R`[src]

Bit 1 - Transmit buffer empty

`pub fn rxne(&self) -> RXNE_R`[src]

Bit 0 - Receive buffer not empty

`pub fn frlvl(&self) -> FRLVL_R`[src]

Bits 9:10 - FIFO reception level

`pub fn ftlvl(&self) -> FTLVL_R`[src]

Bits 11:12 - FIFO Transmission Level

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&self) -> DR_R`[src]

Bits 0:15 - Data register

`impl R<u32, Reg<u32, _CRCPR>>`[src]

`pub fn crcpoly(&self) -> CRCPOLY_R`[src]

Bits 0:15 - CRC polynomial register

`impl R<u32, Reg<u32, _RXCRCR>>`[src]

`pub fn rx_crc(&self) -> RXCRC_R`[src]

Bits 0:15 - Rx CRC register

Checks if the value of the field is SLAVETX

`pub fn is_slave_rx(&self) -> bool`[src]

Checks if the value of the field is SLAVERX

`pub fn is_master_tx(&self) -> bool`[src]

Checks if the value of the field is MASTERTX

`pub fn is_master_rx(&self) -> bool`[src]

Checks if the value of the field is MASTERRX

`impl R<bool, PCMSYNC_A>`[src]

`pub fn variant(&self) -> PCMSYNC_A`[src]

Get enumerated values variant

`pub fn is_short(&self) -> bool`[src]

Checks if the value of the field is SHORT

`pub fn is_long(&self) -> bool`[src]

Checks if the value of the field is LONG

`impl R<u8, I2SSTD_A>`[src]

`pub fn variant(&self) -> I2SSTD_A`[src]

Get enumerated values variant

`pub fn is_philips(&self) -> bool`[src]

Checks if the value of the field is PHILIPS

`pub fn is_msb(&self) -> bool`[src]

Checks if the value of the field is MSB

`pub fn is_lsb(&self) -> bool`[src]

Checks if the value of the field is LSB

`pub fn is_pcm(&self) -> bool`[src]

Checks if the value of the field is PCM

`impl R<bool, CKPOL_A>`[src]

`pub fn variant(&self) -> CKPOL_A`[src]

Get enumerated values variant

`pub fn is_idle_low(&self) -> bool`[src]

Checks if the value of the field is IDLELOW

`pub fn is_idle_high(&self) -> bool`[src]

Checks if the value of the field is IDLEHIGH

`impl R<u8, DATLEN_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATLEN_A>`[src]

Get enumerated values variant

`pub fn is_sixteen_bit(&self) -> bool`[src]

Checks if the value of the field is SIXTEENBIT

`pub fn is_twenty_four_bit(&self) -> bool`[src]

Checks if the value of the field is TWENTYFOURBIT

`pub fn is_thirty_two_bit(&self) -> bool`[src]

Checks if the value of the field is THIRTYTWOBIT

`impl R<bool, CHLEN_A>`[src]

`pub fn variant(&self) -> CHLEN_A`[src]

Get enumerated values variant

`pub fn is_sixteen_bit(&self) -> bool`[src]

Checks if the value of the field is SIXTEENBIT

`pub fn is_thirty_two_bit(&self) -> bool`[src]

Checks if the value of the field is THIRTYTWOBIT

`impl R<u32, Reg<u32, _I2SCFGR>>`[src]

`pub fn i2smod(&self) -> I2SMOD_R`[src]

Bit 11 - I2S mode selection

`pub fn i2se(&self) -> I2SE_R`[src]

Bit 10 - I2S Enable

`pub fn i2scfg(&self) -> I2SCFG_R`[src]

Bits 8:9 - I2S configuration mode

`pub fn pcmsync(&self) -> PCMSYNC_R`[src]

Bit 7 - PCM frame synchronization

`pub fn i2sstd(&self) -> I2SSTD_R`[src]

Bits 4:5 - I2S standard selection

`pub fn ckpol(&self) -> CKPOL_R`[src]

Bit 3 - Steady state clock polarity

`pub fn datlen(&self) -> DATLEN_R`[src]

Bits 1:2 - Data length to be transferred

`pub fn chlen(&self) -> CHLEN_R`[src]

Bit 0 - Channel length (number of bits per audio channel)

`pub fn astrten(&self) -> ASTRTEN_R`[src]

Bit 12 - Asynchronous start enable

`impl R<bool, MCKOE_A>`[src]

`pub fn variant(&self) -> MCKOE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, ODD_A>`[src]

`pub fn variant(&self) -> ODD_A`[src]

Get enumerated values variant

`pub fn is_even(&self) -> bool`[src]

Checks if the value of the field is EVEN

`pub fn is_odd(&self) -> bool`[src]

Checks if the value of the field is ODD

`impl R<u32, Reg<u32, _I2SPR>>`[src]

`pub fn mckoe(&self) -> MCKOE_R`[src]

Bit 9 - Master clock output enable

`pub fn odd(&self) -> ODD_R`[src]

Bit 8 - Odd factor for the prescaler

`pub fn i2sdiv(&self) -> I2SDIV_R`[src]

Bits 0:7 - I2S Linear prescaler

`impl R<u32, Reg<u32, _MEMRMP>>`[src]

`pub fn mem_boot(&self) -> MEM_BOOT_R`[src]

Bit 0 - Memory boot mapping

`pub fn swp_fmc(&self) -> SWP_FMC_R`[src]

Bits 10:11 - FMC memory mapping swap

`impl R<u32, Reg<u32, _PMC>>`[src]

`pub fn pb7_fmp(&self) -> PB7_FMP_R`[src]

Bit 5 - PB7_FMP Fast Mode + Enable

`pub fn pb8_fmp(&self) -> PB8_FMP_R`[src]

Bit 6 - PB8_FMP Fast Mode + Enable

`pub fn pb9_fmp(&self) -> PB9_FMP_R`[src]

Bit 7 - Fast Mode + Enable

`pub fn adcdc2(&self) -> ADCDC2_R`[src]

Bits 16:18 - ADC3DC2

`pub fn pb6_fmp(&self) -> PB6_FMP_R`[src]

Bit 4 - PB6_FMP Fast Mode

`pub fn i2c3_fmp(&self) -> I2C3_FMP_R`[src]

Bit 2 - I2C3_FMP I2C3 Fast Mode + Enable

`pub fn i2c2_fmp(&self) -> I2C2_FMP_R`[src]

Bit 1 - I2C2_FMP I2C2 Fast Mode + Enable

`pub fn i2c1_fmp(&self) -> I2C1_FMP_R`[src]

Bit 0 - I2C1_FMP I2C1 Fast Mode + Enable

`impl R<u32, Reg<u32, _EXTICR1>>`[src]

`pub fn exti3(&self) -> EXTI3_R`[src]

Bits 12:15 - EXTI x configuration (x = 0 to 3)

`pub fn exti2(&self) -> EXTI2_R`[src]

Bits 8:11 - EXTI x configuration (x = 0 to 3)

`pub fn exti1(&self) -> EXTI1_R`[src]

Bits 4:7 - EXTI x configuration (x = 0 to 3)

`pub fn exti0(&self) -> EXTI0_R`[src]

Bits 0:3 - EXTI x configuration (x = 0 to 3)

`impl R<u32, Reg<u32, _EXTICR2>>`[src]

`pub fn exti7(&self) -> EXTI7_R`[src]

Bits 12:15 - EXTI x configuration (x = 4 to 7)

`pub fn exti6(&self) -> EXTI6_R`[src]

Bits 8:11 - EXTI x configuration (x = 4 to 7)

`pub fn exti5(&self) -> EXTI5_R`[src]

Bits 4:7 - EXTI x configuration (x = 4 to 7)

`pub fn exti4(&self) -> EXTI4_R`[src]

Bits 0:3 - EXTI x configuration (x = 4 to 7)

`impl R<u32, Reg<u32, _EXTICR3>>`[src]

`pub fn exti11(&self) -> EXTI11_R`[src]

Bits 12:15 - EXTI x configuration (x = 8 to 11)

`pub fn exti10(&self) -> EXTI10_R`[src]

Bits 8:11 - EXTI10

`pub fn exti9(&self) -> EXTI9_R`[src]

Bits 4:7 - EXTI x configuration (x = 8 to 11)

`pub fn exti8(&self) -> EXTI8_R`[src]

Bits 0:3 - EXTI x configuration (x = 8 to 11)

`impl R<u32, Reg<u32, _EXTICR4>>`[src]

`pub fn exti15(&self) -> EXTI15_R`[src]

Bits 12:15 - EXTI x configuration (x = 12 to 15)

`pub fn exti14(&self) -> EXTI14_R`[src]

Bits 8:11 - EXTI x configuration (x = 12 to 15)

`pub fn exti13(&self) -> EXTI13_R`[src]

Bits 4:7 - EXTI x configuration (x = 12 to 15)

`pub fn exti12(&self) -> EXTI12_R`[src]

Bits 0:3 - EXTI x configuration (x = 12 to 15)

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn m1(&self) -> M1_R`[src]

Bit 28 - Word length

`pub fn eobie(&self) -> EOBIE_R`[src]

Bit 27 - End of Block interrupt enable

`pub fn rtoie(&self) -> RTOIE_R`[src]

Bit 26 - Receiver timeout interrupt enable

`pub fn over8(&self) -> OVER8_R`[src]

Bit 15 - Oversampling mode

`pub fn cmie(&self) -> CMIE_R`[src]

Bit 14 - Character match interrupt enable

`pub fn mme(&self) -> MME_R`[src]

Bit 13 - Mute mode enable

`pub fn m0(&self) -> M0_R`[src]

Bit 12 - Word length

`pub fn wake(&self) -> WAKE_R`[src]

Bit 11 - Receiver wakeup method

`pub fn pce(&self) -> PCE_R`[src]

Bit 10 - Parity control enable

`pub fn ps(&self) -> PS_R`[src]

Bit 9 - Parity selection

`pub fn peie(&self) -> PEIE_R`[src]

Bit 8 - PE interrupt enable

`pub fn txeie(&self) -> TXEIE_R`[src]

Bit 7 - interrupt enable

`pub fn tcie(&self) -> TCIE_R`[src]

Bit 6 - Transmission complete interrupt enable

`pub fn rxneie(&self) -> RXNEIE_R`[src]

Bit 5 - RXNE interrupt enable

`pub fn idleie(&self) -> IDLEIE_R`[src]

Bit 4 - IDLE interrupt enable

`pub fn te(&self) -> TE_R`[src]

Bit 3 - Transmitter enable

`pub fn re(&self) -> RE_R`[src]

Bit 2 - Receiver enable

`pub fn ue(&self) -> UE_R`[src]

Bit 0 - USART enable

`pub fn deat(&self) -> DEAT_R`[src]

Bits 21:25 - Driver Enable assertion time

`pub fn dedt(&self) -> DEDT_R`[src]

Bits 16:20 - Driver Enable de-assertion time

`impl R<bool, RTOEN_A>`[src]

`pub fn variant(&self) -> STOP_A`[src]

Get enumerated values variant

`pub fn is_stop1(&self) -> bool`[src]

Checks if the value of the field is STOP1

`pub fn is_stop0p5(&self) -> bool`[src]

Checks if the value of the field is STOP0P5

`pub fn is_start(&self) -> bool`[src]

Checks if the value of the field is START

`pub fn is_edge(&self) -> bool`[src]

Checks if the value of the field is EDGE

`pub fn is_frame7f(&self) -> bool`[src]

Checks if the value of the field is FRAME7F

`pub fn is_frame55(&self) -> bool`[src]

Checks if the value of the field is FRAME55

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn rtoen(&self) -> RTOEN_R`[src]

Bit 23 - Receiver timeout enable

`pub fn abren(&self) -> ABREN_R`[src]

Bit 20 - Auto baud rate enable

`pub fn msbfirst(&self) -> MSBFIRST_R`[src]

Bit 19 - Most significant bit first

`pub fn datainv(&self) -> DATAINV_R`[src]

Bit 18 - Binary data inversion

`pub fn txinv(&self) -> TXINV_R`[src]

Bit 17 - TX pin active level inversion

`pub fn rxinv(&self) -> RXINV_R`[src]

Bit 16 - RX pin active level inversion

`pub fn swap(&self) -> SWAP_R`[src]

Bit 15 - Swap TX/RX pins

`pub fn linen(&self) -> LINEN_R`[src]

Bit 14 - LIN mode enable

`pub fn stop(&self) -> STOP_R`[src]

Bits 12:13 - STOP bits

`pub fn clken(&self) -> CLKEN_R`[src]

Bit 11 - Clock enable

`pub fn cpol(&self) -> CPOL_R`[src]

Bit 10 - Clock polarity

`pub fn cpha(&self) -> CPHA_R`[src]

Bit 9 - Clock phase

`pub fn lbcl(&self) -> LBCL_R`[src]

Bit 8 - Last bit clock pulse

`pub fn lbdie(&self) -> LBDIE_R`[src]

Bit 6 - LIN break detection interrupt enable

`pub fn lbdl(&self) -> LBDL_R`[src]

`pub fn ddre(&self) -> DDRE_R`[src]

Bit 13 - DMA Disable on Reception Error

`pub fn ovrdis(&self) -> OVRDIS_R`[src]

Bit 12 - Overrun Disable

`pub fn onebit(&self) -> ONEBIT_R`[src]

Bit 11 - One sample bit method enable

`pub fn ctsie(&self) -> CTSIE_R`[src]

Bit 10 - CTS interrupt enable

`pub fn ctse(&self) -> CTSE_R`[src]

Bit 9 - CTS enable

`pub fn rtse(&self) -> RTSE_R`[src]

Bit 8 - RTS enable

`pub fn dmat(&self) -> DMAT_R`[src]

Bit 7 - DMA enable transmitter

`pub fn dmar(&self) -> DMAR_R`[src]

Bit 6 - DMA enable receiver

`pub fn scen(&self) -> SCEN_R`[src]

Bit 5 - Smartcard mode enable

`pub fn nack(&self) -> NACK_R`[src]

Bit 4 - Smartcard NACK enable

`pub fn hdsel(&self) -> HDSEL_R`[src]

Bit 3 - Half-duplex selection

`pub fn irlp(&self) -> IRLP_R`[src]

Bit 2 - Ir low-power

`pub fn iren(&self) -> IREN_R`[src]

Bit 1 - Ir mode enable

`pub fn eie(&self) -> EIE_R`[src]

Bit 0 - Error interrupt enable

`pub fn tcbgtie(&self) -> TCBGTIE_R`[src]

Bit 24 - Transmission complete before guard time interrupt enable

`impl R<u32, Reg<u32, _BRR>>`[src]

`pub fn brr(&self) -> BRR_R`[src]

Bits 0:15 - USARTDIV

`impl R<u32, Reg<u32, _GTPR>>`[src]

`pub fn gt(&self) -> GT_R`[src]

Bits 8:15 - Guard time value

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:7 - Prescaler value

`impl R<u32, Reg<u32, _RTOR>>`[src]

`pub fn blen(&self) -> BLEN_R`[src]

Bits 24:31 - Block Length

`pub fn rto(&self) -> RTO_R`[src]

Bits 0:23 - Receiver timeout value

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn teack(&self) -> TEACK_R`[src]

Bit 21 - TEACK

`pub fn sbkf(&self) -> SBKF_R`[src]

Bit 18 - SBKF

`pub fn cmf(&self) -> CMF_R`[src]

Bit 17 - CMF

`pub fn busy(&self) -> BUSY_R`[src]

Bit 16 - BUSY

`pub fn abrf(&self) -> ABRF_R`[src]

Bit 15 - ABRF

`pub fn abre(&self) -> ABRE_R`[src]

Bit 14 - ABRE

`pub fn eobf(&self) -> EOBF_R`[src]

Bit 12 - EOBF

`pub fn rtof(&self) -> RTOF_R`[src]

Bit 11 - RTOF

`pub fn cts(&self) -> CTS_R`[src]

Bit 10 - CTS

`pub fn ctsif(&self) -> CTSIF_R`[src]

Bit 9 - CTSIF

`pub fn lbdf(&self) -> LBDF_R`[src]

Bit 8 - LBDF

`pub fn txe(&self) -> TXE_R`[src]

Bit 7 - TXE

`pub fn tc(&self) -> TC_R`[src]

Bit 6 - TC

`pub fn rxne(&self) -> RXNE_R`[src]

Bit 5 - RXNE

`pub fn idle(&self) -> IDLE_R`[src]

Bit 4 - IDLE

`pub fn ore(&self) -> ORE_R`[src]

Bit 3 - ORE

`pub fn nf(&self) -> NF_R`[src]

Bit 2 - NF

`pub fn fe(&self) -> FE_R`[src]

Bit 1 - FE

`pub fn pe(&self) -> PE_R`[src]

Bit 0 - PE

`pub fn tcbgt(&self) -> TCBGT_R`[src]

Bit 25 - Transmission complete before guard time completion

`impl R<u32, Reg<u32, _RDR>>`[src]

`pub fn rdr(&self) -> RDR_R`[src]

Bits 0:8 - Receive data value

`impl R<u32, Reg<u32, _TDR>>`[src]

`pub fn tdr(&self) -> TDR_R`[src]

Bits 0:8 - Transmit data value

`impl R<u32, Reg<u32, _OTG_FS_GOTGCTL>>`[src]

`pub fn srqscs(&self) -> SRQSCS_R`[src]

Bit 0 - Session request success

`pub fn srq(&self) -> SRQ_R`[src]

Bit 1 - Session request

`pub fn hngscs(&self) -> HNGSCS_R`[src]

Bit 8 - Host negotiation success

`pub fn hnprq(&self) -> HNPRQ_R`[src]

Bit 9 - HNP request

`pub fn hshnpen(&self) -> HSHNPEN_R`[src]

Bit 10 - Host set HNP enable

`pub fn dhnpen(&self) -> DHNPEN_R`[src]

Bit 11 - Device HNP enabled

`pub fn cidsts(&self) -> CIDSTS_R`[src]

Bit 16 - Connector ID status

`pub fn dbct(&self) -> DBCT_R`[src]

Bit 17 - Long/short debounce time

`pub fn asvld(&self) -> ASVLD_R`[src]

Bit 18 - A-session valid

`pub fn bsvld(&self) -> BSVLD_R`[src]

Bit 19 - B-session valid

`pub fn vbvaloen(&self) -> VBVALOEN_R`[src]

Bit 2 - VBUS valid override enable

`pub fn vbvaloval(&self) -> VBVALOVAL_R`[src]

Bit 3 - VBUS valid override value

`pub fn avaloen(&self) -> AVALOEN_R`[src]

Bit 4 - A-peripheral session valid override enable

`pub fn avaloval(&self) -> AVALOVAL_R`[src]

Bit 5 - A-peripheral session valid override value

`pub fn bvaloen(&self) -> BVALOEN_R`[src]

Bit 6 - B-peripheral session valid override enable

`pub fn bvaloval(&self) -> BVALOVAL_R`[src]

Bit 7 - B-peripheral session valid override value

`pub fn ehen(&self) -> EHEN_R`[src]

Bit 12 - Embedded host enable

`pub fn otgver(&self) -> OTGVER_R`[src]

Bit 20 - OTG version

`impl R<u32, Reg<u32, _OTG_FS_GOTGINT>>`[src]

`pub fn sedet(&self) -> SEDET_R`[src]

Bit 2 - Session end detected

`pub fn srsschg(&self) -> SRSSCHG_R`[src]

Bit 8 - Session request success status change

`pub fn hnsschg(&self) -> HNSSCHG_R`[src]

Bit 9 - Host negotiation success status change

`pub fn hngdet(&self) -> HNGDET_R`[src]

Bit 17 - Host negotiation detected

`pub fn adtochg(&self) -> ADTOCHG_R`[src]

Bit 18 - A-device timeout change

`pub fn dbcdne(&self) -> DBCDNE_R`[src]

Bit 19 - Debounce done

`pub fn idchng(&self) -> IDCHNG_R`[src]

Bit 20 - ID input pin changed

`impl R<u32, Reg<u32, _OTG_FS_GAHBCFG>>`[src]

`pub fn gint(&self) -> GINT_R`[src]

Bit 0 - Global interrupt mask

`pub fn txfelvl(&self) -> TXFELVL_R`[src]

Bit 7 - TxFIFO empty level

`pub fn ptxfelvl(&self) -> PTXFELVL_R`[src]

Bit 8 - Periodic TxFIFO empty level

`impl R<u32, Reg<u32, _OTG_FS_GUSBCFG>>`[src]

`pub fn tocal(&self) -> TOCAL_R`[src]

Bits 0:2 - FS timeout calibration

`pub fn srpcap(&self) -> SRPCAP_R`[src]

Bit 8 - SRP-capable

`pub fn hnpcap(&self) -> HNPCAP_R`[src]

Bit 9 - HNP-capable

`pub fn trdt(&self) -> TRDT_R`[src]

Bits 10:13 - USB turnaround time

`pub fn fhmod(&self) -> FHMOD_R`[src]

Bit 29 - Force host mode

`pub fn fdmod(&self) -> FDMOD_R`[src]

Bit 30 - Force device mode

`impl R<u32, Reg<u32, _OTG_FS_GRSTCTL>>`[src]

`pub fn csrst(&self) -> CSRST_R`[src]

Bit 0 - Core soft reset

`pub fn hsrst(&self) -> HSRST_R`[src]

Bit 1 - HCLK soft reset

`pub fn fcrst(&self) -> FCRST_R`[src]

Bit 2 - Host frame counter reset

`pub fn rxfflsh(&self) -> RXFFLSH_R`[src]

Bit 4 - RxFIFO flush

`pub fn txfflsh(&self) -> TXFFLSH_R`[src]

Bit 5 - TxFIFO flush

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 6:10 - TxFIFO number

`pub fn ahbidl(&self) -> AHBIDL_R`[src]

Bit 31 - AHB master idle

`impl R<u32, Reg<u32, _OTG_FS_GINTSTS>>`[src]

`pub fn cmod(&self) -> CMOD_R`[src]

Bit 0 - Current mode of operation

`pub fn mmis(&self) -> MMIS_R`[src]

Bit 1 - Mode mismatch interrupt

`pub fn otgint(&self) -> OTGINT_R`[src]

Bit 2 - OTG interrupt

`pub fn sof(&self) -> SOF_R`[src]

Bit 3 - Start of frame

`pub fn rxflvl(&self) -> RXFLVL_R`[src]

Bit 4 - RxFIFO non-empty

`pub fn nptxfe(&self) -> NPTXFE_R`[src]

Bit 5 - Non-periodic TxFIFO empty

`pub fn ginakeff(&self) -> GINAKEFF_R`[src]

Bit 6 - Global IN non-periodic NAK effective

`pub fn goutnakeff(&self) -> GOUTNAKEFF_R`[src]

Bit 7 - Global OUT NAK effective

`pub fn esusp(&self) -> ESUSP_R`[src]

Bit 10 - Early suspend

`pub fn usbsusp(&self) -> USBSUSP_R`[src]

Bit 11 - USB suspend

`pub fn usbrst(&self) -> USBRST_R`[src]

Bit 12 - USB reset

`pub fn enumdne(&self) -> ENUMDNE_R`[src]

Bit 13 - Enumeration done

`pub fn isoodrp(&self) -> ISOODRP_R`[src]

Bit 14 - Isochronous OUT packet dropped interrupt

`pub fn eopf(&self) -> EOPF_R`[src]

Bit 15 - End of periodic frame interrupt

`pub fn iepint(&self) -> IEPINT_R`[src]

Bit 18 - IN endpoint interrupt

`pub fn oepint(&self) -> OEPINT_R`[src]

Bit 19 - OUT endpoint interrupt

`pub fn iisoixfr(&self) -> IISOIXFR_R`[src]

Bit 20 - Incomplete isochronous IN transfer

`pub fn ipxfr_incompisoout(&self) -> IPXFR_INCOMPISOOUT_R`[src]

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

`pub fn hprtint(&self) -> HPRTINT_R`[src]

Bit 24 - Host port interrupt

`pub fn hcint(&self) -> HCINT_R`[src]

Bit 25 - Host channels interrupt

`pub fn ptxfe(&self) -> PTXFE_R`[src]

Bit 26 - Periodic TxFIFO empty

`pub fn cidschg(&self) -> CIDSCHG_R`[src]

Bit 28 - Connector ID status change

`pub fn discint(&self) -> DISCINT_R`[src]

Bit 29 - Disconnect detected interrupt

`pub fn srqint(&self) -> SRQINT_R`[src]

Bit 30 - Session request/new session detected interrupt

`pub fn wkupint(&self) -> WKUPINT_R`[src]

Bit 31 - Resume/remote wakeup detected interrupt

`pub fn rstdet(&self) -> RSTDET_R`[src]

Bit 23 - Reset detected interrupt

`impl R<u32, Reg<u32, _OTG_FS_GINTMSK>>`[src]

`pub fn mmism(&self) -> MMISM_R`[src]

Bit 1 - Mode mismatch interrupt mask

`pub fn otgint(&self) -> OTGINT_R`[src]

Bit 2 - OTG interrupt mask

`pub fn sofm(&self) -> SOFM_R`[src]

Bit 3 - Start of frame mask

`pub fn rxflvlm(&self) -> RXFLVLM_R`[src]

Bit 4 - Receive FIFO non-empty mask

`pub fn nptxfem(&self) -> NPTXFEM_R`[src]

Bit 5 - Non-periodic TxFIFO empty mask

`pub fn ginakeffm(&self) -> GINAKEFFM_R`[src]

Bit 6 - Global non-periodic IN NAK effective mask

`pub fn gonakeffm(&self) -> GONAKEFFM_R`[src]

Bit 7 - Global OUT NAK effective mask

`pub fn esuspm(&self) -> ESUSPM_R`[src]

Bit 10 - Early suspend mask

`pub fn usbsuspm(&self) -> USBSUSPM_R`[src]

Bit 11 - USB suspend mask

`pub fn usbrst(&self) -> USBRST_R`[src]

Bit 12 - USB reset mask

`pub fn enumdnem(&self) -> ENUMDNEM_R`[src]

Bit 13 - Enumeration done mask

`pub fn isoodrpm(&self) -> ISOODRPM_R`[src]

Bit 14 - Isochronous OUT packet dropped interrupt mask

`pub fn eopfm(&self) -> EOPFM_R`[src]

Bit 15 - End of periodic frame interrupt mask

`pub fn iepint(&self) -> IEPINT_R`[src]

Bit 18 - IN endpoints interrupt mask

`pub fn oepint(&self) -> OEPINT_R`[src]

Bit 19 - OUT endpoints interrupt mask

`pub fn iisoixfrm(&self) -> IISOIXFRM_R`[src]

Bit 20 - Incomplete isochronous IN transfer mask

`pub fn ipxfrm_iisooxfrm(&self) -> IPXFRM_IISOOXFRM_R`[src]

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

`pub fn prtim(&self) -> PRTIM_R`[src]

Bit 24 - Host port interrupt mask

`pub fn hcim(&self) -> HCIM_R`[src]

Bit 25 - Host channels interrupt mask

`pub fn ptxfem(&self) -> PTXFEM_R`[src]

Bit 26 - Periodic TxFIFO empty mask

`pub fn cidschgm(&self) -> CIDSCHGM_R`[src]

Bit 28 - Connector ID status change mask

`pub fn discint(&self) -> DISCINT_R`[src]

Bit 29 - Disconnect detected interrupt mask

`pub fn srqim(&self) -> SRQIM_R`[src]

Bit 30 - Session request/new session detected interrupt mask

`pub fn wuim(&self) -> WUIM_R`[src]

Bit 31 - Resume/remote wakeup detected interrupt mask

`pub fn rstdetm(&self) -> RSTDETM_R`[src]

Bit 23 - Reset detected interrupt mask

`pub fn lpmin(&self) -> LPMIN_R`[src]

Bit 27 - LPM interrupt mask

`impl R<u32, Reg<u32, _OTG_FS_GRXSTSR_DEVICE>>`[src]

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 0:3 - Endpoint number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`pub fn frmnum(&self) -> FRMNUM_R`[src]

Bits 21:24 - Frame number

`impl R<u32, Reg<u32, _OTG_FS_GRXSTSR_HOST>>`[src]

`pub fn chnum(&self) -> CHNUM_R`[src]

Bits 0:3 - Endpoint number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`impl R<u32, Reg<u32, _OTG_FS_GRXFSIZ>>`[src]

`pub fn rxfd(&self) -> RXFD_R`[src]

Bits 0:15 - RxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF0_DEVICE>>`[src]

`pub fn tx0fsa(&self) -> TX0FSA_R`[src]

Bits 0:15 - Endpoint 0 transmit RAM start address

`pub fn tx0fd(&self) -> TX0FD_R`[src]

Bits 16:31 - Endpoint 0 TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_HNPTXFSIZ_HOST>>`[src]

`pub fn nptxfsa(&self) -> NPTXFSA_R`[src]

Bits 0:15 - Non-periodic transmit RAM start address

`pub fn nptxfd(&self) -> NPTXFD_R`[src]

Bits 16:31 - Non-periodic TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_HNPTXSTS>>`[src]

`pub fn nptxfsav(&self) -> NPTXFSAV_R`[src]

Bits 0:15 - Non-periodic TxFIFO space available

`pub fn nptqxsav(&self) -> NPTQXSAV_R`[src]

Bits 16:23 - Non-periodic transmit request queue space available

`pub fn nptxqtop(&self) -> NPTXQTOP_R`[src]

Bits 24:30 - Top of the non-periodic transmit request queue

`impl R<u32, Reg<u32, _OTG_FS_GCCFG>>`[src]

`pub fn pwrdwn(&self) -> PWRDWN_R`[src]

Bit 16 - Power down

`pub fn bcden(&self) -> BCDEN_R`[src]

Bit 17 - Battery charging detector (BCD) enable

`pub fn dcden(&self) -> DCDEN_R`[src]

Bit 18 - Data contact detection (DCD) mode enable

`pub fn pden(&self) -> PDEN_R`[src]

Bit 19 - Primary detection (PD) mode enable

`pub fn sden(&self) -> SDEN_R`[src]

Bit 20 - Secondary detection (SD) mode enable

`pub fn vbden(&self) -> VBDEN_R`[src]

Bit 21 - USB VBUS detection enable

`pub fn dcdet(&self) -> DCDET_R`[src]

Bit 0 - Data contact detection (DCD) status

`pub fn pdet(&self) -> PDET_R`[src]

Bit 1 - Primary detection (PD) status

`pub fn sdet(&self) -> SDET_R`[src]

Bit 2 - Secondary detection (SD) status

`pub fn ps2det(&self) -> PS2DET_R`[src]

Bit 3 - DM pull-up detection status

`impl R<u32, Reg<u32, _OTG_FS_CID>>`[src]

`pub fn product_id(&self) -> PRODUCT_ID_R`[src]

Bits 0:31 - Product ID field

`impl R<u32, Reg<u32, _OTG_FS_HPTXFSIZ>>`[src]

`pub fn ptxsa(&self) -> PTXSA_R`[src]

Bits 0:15 - Host periodic TxFIFO start address

`pub fn ptxfsiz(&self) -> PTXFSIZ_R`[src]

Bits 16:31 - Host periodic TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF1>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF2>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFO3 transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF3>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFO4 transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_GRXSTSP_DEVICE>>`[src]

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 0:3 - Endpoint number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`pub fn frmnum(&self) -> FRMNUM_R`[src]

Bits 21:24 - Frame number

`impl R<u32, Reg<u32, _OTG_FS_GRXSTSP_HOST>>`[src]

`pub fn chnum(&self) -> CHNUM_R`[src]

Bits 0:3 - Channel number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`impl R<u32, Reg<u32, _OTG_FS_GI2CCTL>>`[src]

`pub fn rwdata(&self) -> RWDATA_R`[src]

Bits 0:7 - I2C Read/Write Data

`pub fn regaddr(&self) -> REGADDR_R`[src]

Bits 8:15 - I2C Register Address

`pub fn addr(&self) -> ADDR_R`[src]

Bits 16:22 - I2C Address

`pub fn i2cen(&self) -> I2CEN_R`[src]

Bit 23 - I2C Enable

`pub fn ack(&self) -> ACK_R`[src]

Bit 24 - I2C ACK

`pub fn i2cdevadr(&self) -> I2CDEVADR_R`[src]

Bits 26:27 - I2C Device Address

`pub fn i2cdatse0(&self) -> I2CDATSE0_R`[src]

Bit 28 - I2C DatSe0 USB mode

`pub fn rw(&self) -> RW_R`[src]

Bit 30 - Read/Write Indicator

`pub fn bsydne(&self) -> BSYDNE_R`[src]

Bit 31 - I2C Busy/Done

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF4>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint Tx FIFO depth

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF5>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint Tx FIFO depth

`impl R<u32, Reg<u32, _OTG_FS_GLPMCFG>>`[src]

`pub fn lpmen(&self) -> LPMEN_R`[src]

Bit 0 - LPM support enable

`pub fn lpmack(&self) -> LPMACK_R`[src]

Bit 1 - LPM token acknowledge enable

`pub fn besl(&self) -> BESL_R`[src]

Bits 2:5 - Best effort service latency

`pub fn remwake(&self) -> REMWAKE_R`[src]

Bit 6 - bRemoteWake value

`pub fn l1ssen(&self) -> L1SSEN_R`[src]

Bit 7 - L1 Shallow Sleep enable

`pub fn beslthrs(&self) -> BESLTHRS_R`[src]

Bits 8:11 - BESL threshold

`pub fn l1dsen(&self) -> L1DSEN_R`[src]

Bit 12 - L1 deep sleep enable

`pub fn lpmrst(&self) -> LPMRST_R`[src]

Bits 13:14 - LPM response

`pub fn slpsts(&self) -> SLPSTS_R`[src]

Bit 15 - Port sleep status

`pub fn l1rsmok(&self) -> L1RSMOK_R`[src]

Bit 16 - Sleep State Resume OK

`pub fn lpmchidx(&self) -> LPMCHIDX_R`[src]

Bits 17:20 - LPM Channel Index

`pub fn lpmrcnt(&self) -> LPMRCNT_R`[src]

Bits 21:23 - LPM retry count

`pub fn sndlpm(&self) -> SNDLPM_R`[src]

Bit 24 - Send LPM transaction

`pub fn lpmrcntsts(&self) -> LPMRCNTSTS_R`[src]

Bits 25:27 - LPM retry count status

`pub fn enbesl(&self) -> ENBESL_R`[src]

Bit 28 - Enable best effort service latency

`impl R<u32, Reg<u32, _OTG_FS_HCFG>>`[src]

`pub fn fslspcs(&self) -> FSLSPCS_R`[src]

Bits 0:1 - FS/LS PHY clock select

`pub fn fslss(&self) -> FSLSS_R`[src]

Bit 2 - FS- and LS-only support

`impl R<u32, Reg<u32, _OTG_FS_HFIR>>`[src]

`pub fn frivl(&self) -> FRIVL_R`[src]

Bits 0:15 - Frame interval

`impl R<u32, Reg<u32, _OTG_FS_HFNUM>>`[src]

`pub fn frnum(&self) -> FRNUM_R`[src]

Bits 0:15 - Frame number

`pub fn ftrem(&self) -> FTREM_R`[src]

Bits 16:31 - Frame time remaining

`impl R<u32, Reg<u32, _OTG_FS_HPTXSTS>>`[src]

`pub fn ptxfsavl(&self) -> PTXFSAVL_R`[src]

Bits 0:15 - Periodic transmit data FIFO space available

`pub fn ptxqsav(&self) -> PTXQSAV_R`[src]

Bits 16:23 - Periodic transmit request queue space available

`pub fn ptxqtop(&self) -> PTXQTOP_R`[src]

Bits 24:31 - Top of the periodic transmit request queue

`impl R<u32, Reg<u32, _OTG_FS_HAINT>>`[src]

`pub fn haint(&self) -> HAINT_R`[src]

Bits 0:15 - Channel interrupts

`impl R<u32, Reg<u32, _OTG_FS_HAINTMSK>>`[src]

`pub fn haintm(&self) -> HAINTM_R`[src]

Bits 0:15 - Channel interrupt mask

`impl R<u32, Reg<u32, _OTG_FS_HPRT>>`[src]

`pub fn pcsts(&self) -> PCSTS_R`[src]

Bit 0 - Port connect status

`pub fn pcdet(&self) -> PCDET_R`[src]

Bit 1 - Port connect detected

`pub fn pena(&self) -> PENA_R`[src]

Bit 2 - Port enable

`pub fn penchng(&self) -> PENCHNG_R`[src]

Bit 3 - Port enable/disable change

`pub fn poca(&self) -> POCA_R`[src]

Bit 4 - Port overcurrent active

`pub fn pocchng(&self) -> POCCHNG_R`[src]

Bit 5 - Port overcurrent change

`pub fn pres(&self) -> PRES_R`[src]

Bit 6 - Port resume

`pub fn psusp(&self) -> PSUSP_R`[src]

Bit 7 - Port suspend

`pub fn prst(&self) -> PRST_R`[src]

Bit 8 - Port reset

`pub fn plsts(&self) -> PLSTS_R`[src]

Bits 10:11 - Port line status

`pub fn ppwr(&self) -> PPWR_R`[src]

Bit 12 - Port power

`pub fn ptctl(&self) -> PTCTL_R`[src]

Bits 13:16 - Port test control

`pub fn pspd(&self) -> PSPD_R`[src]

Bits 17:18 - Port speed

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR0>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR1>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR2>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR3>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR4>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR5>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR6>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR7>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCINT0>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT1>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT2>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT3>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT4>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT5>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT6>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT7>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK0>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK1>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK2>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK3>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK4>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK5>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK6>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK7>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCINT8>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK8>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCTSIZ8>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR9>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCINT9>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK9>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCTSIZ9>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR10>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCINT10>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK10>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCTSIZ10>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR11>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCINT11>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK11>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCTSIZ11>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_FS_DCFG>>`[src]

`pub fn dspd(&self) -> DSPD_R`[src]

Bits 0:1 - Device speed

`pub fn nzlsohsk(&self) -> NZLSOHSK_R`[src]

Bit 2 - Non-zero-length status OUT handshake

`pub fn dad(&self) -> DAD_R`[src]

Bits 4:10 - Device address

`pub fn pfivl(&self) -> PFIVL_R`[src]

Bits 11:12 - Periodic frame interval

`impl R<u32, Reg<u32, _OTG_FS_DCTL>>`[src]

`pub fn rwusig(&self) -> RWUSIG_R`[src]

Bit 0 - Remote wakeup signaling

`pub fn sdis(&self) -> SDIS_R`[src]

Bit 1 - Soft disconnect

`pub fn ginsts(&self) -> GINSTS_R`[src]

Bit 2 - Global IN NAK status

`pub fn gonsts(&self) -> GONSTS_R`[src]

Bit 3 - Global OUT NAK status

`pub fn tctl(&self) -> TCTL_R`[src]

Bits 4:6 - Test control

`pub fn sginak(&self) -> SGINAK_R`[src]

Bit 7 - Set global IN NAK

`pub fn cginak(&self) -> CGINAK_R`[src]

Bit 8 - Clear global IN NAK

`pub fn sgonak(&self) -> SGONAK_R`[src]

Bit 9 - Set global OUT NAK

`pub fn cgonak(&self) -> CGONAK_R`[src]

Bit 10 - Clear global OUT NAK

`pub fn poprgdne(&self) -> POPRGDNE_R`[src]

Bit 11 - Power-on programming done

`impl R<u32, Reg<u32, _OTG_FS_DSTS>>`[src]

`pub fn suspsts(&self) -> SUSPSTS_R`[src]

Bit 0 - Suspend status

`pub fn enumspd(&self) -> ENUMSPD_R`[src]

Bits 1:2 - Enumerated speed

`pub fn eerr(&self) -> EERR_R`[src]

Bit 3 - Erratic error

`pub fn fnsof(&self) -> FNSOF_R`[src]

Bits 8:21 - Frame number of the received SOF

`impl R<u32, Reg<u32, _OTG_FS_DIEPMSK>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed interrupt mask

`pub fn epdm(&self) -> EPDM_R`[src]

Bit 1 - Endpoint disabled interrupt mask

`pub fn tom(&self) -> TOM_R`[src]

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

`pub fn ittxfemsk(&self) -> ITTXFEMSK_R`[src]

Bit 4 - IN token received when TxFIFO empty mask

`pub fn inepnmm(&self) -> INEPNMM_R`[src]

Bit 5 - IN token received with EP mismatch mask

`pub fn inepnem(&self) -> INEPNEM_R`[src]

Bit 6 - IN endpoint NAK effective mask

`impl R<u32, Reg<u32, _OTG_FS_DOEPMSK>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed interrupt mask

`pub fn epdm(&self) -> EPDM_R`[src]

Bit 1 - Endpoint disabled interrupt mask

`pub fn stupm(&self) -> STUPM_R`[src]

Bit 3 - SETUP phase done mask

`pub fn otepdm(&self) -> OTEPDM_R`[src]

Bit 4 - OUT token received when endpoint disabled mask

`impl R<u32, Reg<u32, _OTG_FS_DAINT>>`[src]

`pub fn iepint(&self) -> IEPINT_R`[src]

Bits 0:15 - IN endpoint interrupt bits

`pub fn oepint(&self) -> OEPINT_R`[src]

Bits 16:31 - OUT endpoint interrupt bits

`impl R<u32, Reg<u32, _OTG_FS_DAINTMSK>>`[src]

`pub fn iepm(&self) -> IEPM_R`[src]

Bits 0:15 - IN EP interrupt mask bits

`pub fn oepint(&self) -> OEPINT_R`[src]

Bits 16:31 - OUT endpoint interrupt bits

`impl R<u32, Reg<u32, _OTG_FS_DVBUSDIS>>`[src]

`pub fn vbusdt(&self) -> VBUSDT_R`[src]

Bits 0:15 - Device VBUS discharge time

`impl R<u32, Reg<u32, _OTG_FS_DVBUSPULSE>>`[src]

`pub fn dvbusp(&self) -> DVBUSP_R`[src]

Bits 0:11 - Device VBUS pulsing time

`impl R<u32, Reg<u32, _OTG_FS_DIEPEMPMSK>>`[src]

`pub fn ineptxfem(&self) -> INEPTXFEM_R`[src]

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL0>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:1 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL1>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TXFNUM

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL2>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TXFNUM

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL3>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TXFNUM

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL0>>`[src]

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - SNPM

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:1 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL1>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - SNPM

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL2>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - SNPM

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL3>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ0>>`[src]

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:20 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:6 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ0>>`[src]

`pub fn stupcnt(&self) -> STUPCNT_R`[src]

Bits 29:30 - SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bit 19 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:6 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ1>>`[src]

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 29:30 - Multi count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ2>>`[src]

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 29:30 - Multi count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ3>>`[src]

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 29:30 - Multi count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS0>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS1>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS2>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS3>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ1>>`[src]

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ2>>`[src]

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ3>>`[src]

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL4>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TXFNUM

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DIEPINT4>>`[src]

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - TXFE

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - INEPNE

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - ITTXFE

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - TOC

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - EPDISD

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - XFRC

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ4>>`[src]

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 29:30 - Multi count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS4>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL5>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TXFNUM

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DIEPINT5>>`[src]

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - TXFE

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - INEPNE

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - ITTXFE

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - TOC

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - EPDISD

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - XFRC

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ5>>`[src]

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 29:30 - Multi count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS5>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL4>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - SNPM

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPINT4>>`[src]

`pub fn b2bstup(&self) -> B2BSTUP_R`[src]

Bit 6 - B2BSTUP

`pub fn otepdis(&self) -> OTEPDIS_R`[src]

Bit 4 - OTEPDIS

`pub fn stup(&self) -> STUP_R`[src]

Bit 3 - STUP

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - EPDISD

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - XFRC

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ4>>`[src]

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL5>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - SNPM

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPINT5>>`[src]

`pub fn b2bstup(&self) -> B2BSTUP_R`[src]

Bit 6 - B2BSTUP

`pub fn otepdis(&self) -> OTEPDIS_R`[src]

Bit 4 - OTEPDIS

`pub fn stup(&self) -> STUP_R`[src]

Bit 3 - STUP

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - EPDISD

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - XFRC

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ5>>`[src]

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_PCGCCTL>>`[src]

`pub fn stppclk(&self) -> STPPCLK_R`[src]

Bit 0 - Stop PHY clock

`pub fn gatehclk(&self) -> GATEHCLK_R`[src]

Bit 1 - Gate HCLK

`pub fn physusp(&self) -> PHYSUSP_R`[src]

Bit 4 - PHY Suspended

`impl R<u32, Reg<u32, _OTG_HS_HCFG>>`[src]

`pub fn fslspcs(&self) -> FSLSPCS_R`[src]

Bits 0:1 - FS/LS PHY clock select

`pub fn fslss(&self) -> FSLSS_R`[src]

Bit 2 - FS- and LS-only support

`impl R<u32, Reg<u32, _OTG_HS_HFIR>>`[src]

`pub fn frivl(&self) -> FRIVL_R`[src]

Bits 0:15 - Frame interval

`impl R<u32, Reg<u32, _OTG_HS_HFNUM>>`[src]

`pub fn frnum(&self) -> FRNUM_R`[src]

Bits 0:15 - Frame number

`pub fn ftrem(&self) -> FTREM_R`[src]

Bits 16:31 - Frame time remaining

`impl R<u32, Reg<u32, _OTG_HS_HPTXSTS>>`[src]

`pub fn ptxfsavl(&self) -> PTXFSAVL_R`[src]

Bits 0:15 - Periodic transmit data FIFO space available

`pub fn ptxqsav(&self) -> PTXQSAV_R`[src]

Bits 16:23 - Periodic transmit request queue space available

`pub fn ptxqtop(&self) -> PTXQTOP_R`[src]

Bits 24:31 - Top of the periodic transmit request queue

`impl R<u32, Reg<u32, _OTG_HS_HAINT>>`[src]

`pub fn haint(&self) -> HAINT_R`[src]

Bits 0:15 - Channel interrupts

`impl R<u32, Reg<u32, _OTG_HS_HAINTMSK>>`[src]

`pub fn haintm(&self) -> HAINTM_R`[src]

Bits 0:15 - Channel interrupt mask

`impl R<u32, Reg<u32, _OTG_HS_HPRT>>`[src]

`pub fn pcsts(&self) -> PCSTS_R`[src]

Bit 0 - Port connect status

`pub fn pcdet(&self) -> PCDET_R`[src]

Bit 1 - Port connect detected

`pub fn pena(&self) -> PENA_R`[src]

Bit 2 - Port enable

`pub fn penchng(&self) -> PENCHNG_R`[src]

Bit 3 - Port enable/disable change

`pub fn poca(&self) -> POCA_R`[src]

Bit 4 - Port overcurrent active

`pub fn pocchng(&self) -> POCCHNG_R`[src]

Bit 5 - Port overcurrent change

`pub fn pres(&self) -> PRES_R`[src]

Bit 6 - Port resume

`pub fn psusp(&self) -> PSUSP_R`[src]

Bit 7 - Port suspend

`pub fn prst(&self) -> PRST_R`[src]

Bit 8 - Port reset

`pub fn plsts(&self) -> PLSTS_R`[src]

Bits 10:11 - Port line status

`pub fn ppwr(&self) -> PPWR_R`[src]

Bit 12 - Port power

`pub fn ptctl(&self) -> PTCTL_R`[src]

Bits 13:16 - Port test control

`pub fn pspd(&self) -> PSPD_R`[src]

Bits 17:18 - Port speed

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR0>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR1>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR2>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR3>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR4>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR5>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR6>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR7>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR8>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR9>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR10>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR11>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT0>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT1>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT2>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT3>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT4>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT5>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT6>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT7>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT8>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT9>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT10>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT11>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCINT0>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT1>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT2>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT3>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT4>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT5>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT6>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT7>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT8>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT9>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT10>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT11>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK0>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK1>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK2>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK3>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK4>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK5>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK6>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK7>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK8>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK9>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK10>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK11>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR12>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT12>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCINT12>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK12>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCTSIZ12>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_HS_HCDMA12>>`[src]

`pub fn dmaaddr(&self) -> DMAADDR_R`[src]

Bits 0:31 - DMA address

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR13>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT13>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCINT13>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK13>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALLM response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCTSIZ13>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_HS_HCDMA13>>`[src]

`pub fn dmaaddr(&self) -> DMAADDR_R`[src]

Bits 0:31 - DMA address

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR14>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT14>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCINT14>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK14>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAKM response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACKM response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCTSIZ14>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_HS_HCDMA14>>`[src]

`pub fn dmaaddr(&self) -> DMAADDR_R`[src]

Bits 0:31 - DMA address

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR15>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT15>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCINT15>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK15>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCTSIZ15>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_HS_HCDMA15>>`[src]

`pub fn dmaaddr(&self) -> DMAADDR_R`[src]

Bits 0:31 - DMA address

`impl R<u32, Reg<u32, _OTG_HS_GOTGCTL>>`[src]

`pub fn srqscs(&self) -> SRQSCS_R`[src]

Bit 0 - Session request success

`pub fn srq(&self) -> SRQ_R`[src]

Bit 1 - Session request

`pub fn hngscs(&self) -> HNGSCS_R`[src]

Bit 8 - Host negotiation success

`pub fn hnprq(&self) -> HNPRQ_R`[src]

Bit 9 - HNP request

`pub fn hshnpen(&self) -> HSHNPEN_R`[src]

Bit 10 - Host set HNP enable

`pub fn dhnpen(&self) -> DHNPEN_R`[src]

Bit 11 - Device HNP enabled

`pub fn cidsts(&self) -> CIDSTS_R`[src]

Bit 16 - Connector ID status

`pub fn dbct(&self) -> DBCT_R`[src]

Bit 17 - Long/short debounce time

`pub fn asvld(&self) -> ASVLD_R`[src]

Bit 18 - A-session valid

`pub fn bsvld(&self) -> BSVLD_R`[src]

Bit 19 - B-session valid

`pub fn ehen(&self) -> EHEN_R`[src]

Bit 12 - Embedded host enable

`impl R<u32, Reg<u32, _OTG_HS_GOTGINT>>`[src]

`pub fn sedet(&self) -> SEDET_R`[src]

Bit 2 - Session end detected

`pub fn srsschg(&self) -> SRSSCHG_R`[src]

Bit 8 - Session request success status change

`pub fn hnsschg(&self) -> HNSSCHG_R`[src]

Bit 9 - Host negotiation success status change

`pub fn hngdet(&self) -> HNGDET_R`[src]

Bit 17 - Host negotiation detected

`pub fn adtochg(&self) -> ADTOCHG_R`[src]

Bit 18 - A-device timeout change

`pub fn dbcdne(&self) -> DBCDNE_R`[src]

Bit 19 - Debounce done

`pub fn idchng(&self) -> IDCHNG_R`[src]

Bit 20 - ID input pin changed

`impl R<u32, Reg<u32, _OTG_HS_GAHBCFG>>`[src]

`pub fn gint(&self) -> GINT_R`[src]

Bit 0 - Global interrupt mask

`pub fn hbstlen(&self) -> HBSTLEN_R`[src]

Bits 1:4 - Burst length/type

`pub fn dmaen(&self) -> DMAEN_R`[src]

Bit 5 - DMA enable

`pub fn txfelvl(&self) -> TXFELVL_R`[src]

Bit 7 - TxFIFO empty level

`pub fn ptxfelvl(&self) -> PTXFELVL_R`[src]

Bit 8 - Periodic TxFIFO empty level

`impl R<u32, Reg<u32, _OTG_HS_GUSBCFG>>`[src]

`pub fn tocal(&self) -> TOCAL_R`[src]

Bits 0:2 - FS timeout calibration

`pub fn srpcap(&self) -> SRPCAP_R`[src]

Bit 8 - SRP-capable

`pub fn hnpcap(&self) -> HNPCAP_R`[src]

Bit 9 - HNP-capable

`pub fn trdt(&self) -> TRDT_R`[src]

Bits 10:13 - USB turnaround time

`pub fn phylpcs(&self) -> PHYLPCS_R`[src]

Bit 15 - PHY Low-power clock select

`pub fn ulpifsls(&self) -> ULPIFSLS_R`[src]

Bit 17 - ULPI FS/LS select

`pub fn ulpiar(&self) -> ULPIAR_R`[src]

Bit 18 - ULPI Auto-resume

`pub fn ulpicsm(&self) -> ULPICSM_R`[src]

Bit 19 - ULPI Clock SuspendM

`pub fn ulpievbusd(&self) -> ULPIEVBUSD_R`[src]

Bit 20 - ULPI External VBUS Drive

`pub fn ulpievbusi(&self) -> ULPIEVBUSI_R`[src]

Bit 21 - ULPI external VBUS indicator

`pub fn tsdps(&self) -> TSDPS_R`[src]

Bit 22 - TermSel DLine pulsing selection

`pub fn pcci(&self) -> PCCI_R`[src]

Bit 23 - Indicator complement

`pub fn ptci(&self) -> PTCI_R`[src]

Bit 24 - Indicator pass through

`pub fn ulpiipd(&self) -> ULPIIPD_R`[src]

Bit 25 - ULPI interface protect disable

`pub fn fhmod(&self) -> FHMOD_R`[src]

Bit 29 - Forced host mode

`pub fn fdmod(&self) -> FDMOD_R`[src]

Bit 30 - Forced peripheral mode

`impl R<u32, Reg<u32, _OTG_HS_GRSTCTL>>`[src]

`pub fn csrst(&self) -> CSRST_R`[src]

Bit 0 - Core soft reset

`pub fn hsrst(&self) -> HSRST_R`[src]

Bit 1 - HCLK soft reset

`pub fn fcrst(&self) -> FCRST_R`[src]

Bit 2 - Host frame counter reset

`pub fn rxfflsh(&self) -> RXFFLSH_R`[src]

Bit 4 - RxFIFO flush

`pub fn txfflsh(&self) -> TXFFLSH_R`[src]

Bit 5 - TxFIFO flush

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 6:10 - TxFIFO number

`pub fn ahbidl(&self) -> AHBIDL_R`[src]

Bit 31 - AHB master idle

`pub fn dmareq(&self) -> DMAREQ_R`[src]

Bit 30 - DMA request signal enabled for USB OTG HS

`impl R<u32, Reg<u32, _OTG_HS_GINTSTS>>`[src]

`pub fn cmod(&self) -> CMOD_R`[src]

Bit 0 - Current mode of operation

`pub fn mmis(&self) -> MMIS_R`[src]

Bit 1 - Mode mismatch interrupt

`pub fn otgint(&self) -> OTGINT_R`[src]

Bit 2 - OTG interrupt

`pub fn sof(&self) -> SOF_R`[src]

Bit 3 - Start of frame

`pub fn rxflvl(&self) -> RXFLVL_R`[src]

Bit 4 - RxFIFO nonempty

`pub fn nptxfe(&self) -> NPTXFE_R`[src]

Bit 5 - Nonperiodic TxFIFO empty

`pub fn ginakeff(&self) -> GINAKEFF_R`[src]

Bit 6 - Global IN nonperiodic NAK effective

`pub fn boutnakeff(&self) -> BOUTNAKEFF_R`[src]

Bit 7 - Global OUT NAK effective

`pub fn esusp(&self) -> ESUSP_R`[src]

Bit 10 - Early suspend

`pub fn usbsusp(&self) -> USBSUSP_R`[src]

Bit 11 - USB suspend

`pub fn usbrst(&self) -> USBRST_R`[src]

Bit 12 - USB reset

`pub fn enumdne(&self) -> ENUMDNE_R`[src]

Bit 13 - Enumeration done

`pub fn isoodrp(&self) -> ISOODRP_R`[src]

Bit 14 - Isochronous OUT packet dropped interrupt

`pub fn eopf(&self) -> EOPF_R`[src]

Bit 15 - End of periodic frame interrupt

`pub fn iepint(&self) -> IEPINT_R`[src]

Bit 18 - IN endpoint interrupt

`pub fn oepint(&self) -> OEPINT_R`[src]

Bit 19 - OUT endpoint interrupt

`pub fn iisoixfr(&self) -> IISOIXFR_R`[src]

Bit 20 - Incomplete isochronous IN transfer

`pub fn pxfr_incompisoout(&self) -> PXFR_INCOMPISOOUT_R`[src]

Bit 21 - Incomplete periodic transfer

`pub fn datafsusp(&self) -> DATAFSUSP_R`[src]

Bit 22 - Data fetch suspended

`pub fn hprtint(&self) -> HPRTINT_R`[src]

Bit 24 - Host port interrupt

`pub fn hcint(&self) -> HCINT_R`[src]

Bit 25 - Host channels interrupt

`pub fn ptxfe(&self) -> PTXFE_R`[src]

Bit 26 - Periodic TxFIFO empty

`pub fn cidschg(&self) -> CIDSCHG_R`[src]

Bit 28 - Connector ID status change

`pub fn discint(&self) -> DISCINT_R`[src]

Bit 29 - Disconnect detected interrupt

`pub fn srqint(&self) -> SRQINT_R`[src]

Bit 30 - Session request/new session detected interrupt

`pub fn wkuint(&self) -> WKUINT_R`[src]

Bit 31 - Resume/remote wakeup detected interrupt

`impl R<u32, Reg<u32, _OTG_HS_GINTMSK>>`[src]

`pub fn mmism(&self) -> MMISM_R`[src]

Bit 1 - Mode mismatch interrupt mask

`pub fn otgint(&self) -> OTGINT_R`[src]

Bit 2 - OTG interrupt mask

`pub fn sofm(&self) -> SOFM_R`[src]

Bit 3 - Start of frame mask

`pub fn rxflvlm(&self) -> RXFLVLM_R`[src]

Bit 4 - Receive FIFO nonempty mask

`pub fn nptxfem(&self) -> NPTXFEM_R`[src]

Bit 5 - Nonperiodic TxFIFO empty mask

`pub fn ginakeffm(&self) -> GINAKEFFM_R`[src]

Bit 6 - Global nonperiodic IN NAK effective mask

`pub fn gonakeffm(&self) -> GONAKEFFM_R`[src]

Bit 7 - Global OUT NAK effective mask

`pub fn esuspm(&self) -> ESUSPM_R`[src]

Bit 10 - Early suspend mask

`pub fn usbsuspm(&self) -> USBSUSPM_R`[src]

Bit 11 - USB suspend mask

`pub fn usbrst(&self) -> USBRST_R`[src]

Bit 12 - USB reset mask

`pub fn enumdnem(&self) -> ENUMDNEM_R`[src]

Bit 13 - Enumeration done mask

`pub fn isoodrpm(&self) -> ISOODRPM_R`[src]

Bit 14 - Isochronous OUT packet dropped interrupt mask

`pub fn eopfm(&self) -> EOPFM_R`[src]

Bit 15 - End of periodic frame interrupt mask

`pub fn iepint(&self) -> IEPINT_R`[src]

Bit 18 - IN endpoints interrupt mask

`pub fn oepint(&self) -> OEPINT_R`[src]

Bit 19 - OUT endpoints interrupt mask

`pub fn iisoixfrm(&self) -> IISOIXFRM_R`[src]

Bit 20 - Incomplete isochronous IN transfer mask

`pub fn pxfrm_iisooxfrm(&self) -> PXFRM_IISOOXFRM_R`[src]

Bit 21 - Incomplete periodic transfer mask

`pub fn fsuspm(&self) -> FSUSPM_R`[src]

Bit 22 - Data fetch suspended mask

`pub fn prtim(&self) -> PRTIM_R`[src]

Bit 24 - Host port interrupt mask

`pub fn hcim(&self) -> HCIM_R`[src]

Bit 25 - Host channels interrupt mask

`pub fn ptxfem(&self) -> PTXFEM_R`[src]

Bit 26 - Periodic TxFIFO empty mask

`pub fn cidschgm(&self) -> CIDSCHGM_R`[src]

Bit 28 - Connector ID status change mask

`pub fn discint(&self) -> DISCINT_R`[src]

Bit 29 - Disconnect detected interrupt mask

`pub fn srqim(&self) -> SRQIM_R`[src]

Bit 30 - Session request/new session detected interrupt mask

`pub fn wuim(&self) -> WUIM_R`[src]

Bit 31 - Resume/remote wakeup detected interrupt mask

`pub fn rstde(&self) -> RSTDE_R`[src]

Bit 23 - Reset detected interrupt mask

`pub fn lpmintm(&self) -> LPMINTM_R`[src]

Bit 27 - LPM interrupt mask

`impl R<u32, Reg<u32, _OTG_HS_GRXSTSR_HOST>>`[src]

`pub fn chnum(&self) -> CHNUM_R`[src]

Bits 0:3 - Channel number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`impl R<u32, Reg<u32, _OTG_HS_GRXSTSP_HOST>>`[src]

`pub fn chnum(&self) -> CHNUM_R`[src]

Bits 0:3 - Channel number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`impl R<u32, Reg<u32, _OTG_HS_GRXFSIZ>>`[src]

`pub fn rxfd(&self) -> RXFD_R`[src]

Bits 0:15 - RxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_HNPTXFSIZ_HOST>>`[src]

`pub fn nptxfsa(&self) -> NPTXFSA_R`[src]

Bits 0:15 - Nonperiodic transmit RAM start address

`pub fn nptxfd(&self) -> NPTXFD_R`[src]

Bits 16:31 - Nonperiodic TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF0_DEVICE>>`[src]

`pub fn tx0fsa(&self) -> TX0FSA_R`[src]

Bits 0:15 - Endpoint 0 transmit RAM start address

`pub fn tx0fd(&self) -> TX0FD_R`[src]

Bits 16:31 - Endpoint 0 TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_HNPTXSTS>>`[src]

`pub fn nptxfsav(&self) -> NPTXFSAV_R`[src]

Bits 0:15 - Nonperiodic TxFIFO space available

`pub fn nptqxsav(&self) -> NPTQXSAV_R`[src]

Bits 16:23 - Nonperiodic transmit request queue space available

`pub fn nptxqtop(&self) -> NPTXQTOP_R`[src]

Bits 24:30 - Top of the nonperiodic transmit request queue

`impl R<u32, Reg<u32, _OTG_HS_GCCFG>>`[src]

`pub fn pwrdwn(&self) -> PWRDWN_R`[src]

Bit 16 - Power down

`pub fn bcden(&self) -> BCDEN_R`[src]

Bit 17 - Battery charging detector (BCD) enable

`pub fn dcden(&self) -> DCDEN_R`[src]

Bit 18 - Data contact detection (DCD) mode enable

`pub fn pden(&self) -> PDEN_R`[src]

Bit 19 - Primary detection (PD) mode enable

`pub fn sden(&self) -> SDEN_R`[src]

Bit 20 - Secondary detection (SD) mode enable

`pub fn vbden(&self) -> VBDEN_R`[src]

Bit 21 - USB VBUS detection enable

`pub fn dcdet(&self) -> DCDET_R`[src]

Bit 0 - Data contact detection (DCD) status

`pub fn pdet(&self) -> PDET_R`[src]

Bit 1 - Primary detection (PD) status

`pub fn sdet(&self) -> SDET_R`[src]

Bit 2 - Secondary detection (SD) status

`pub fn ps2det(&self) -> PS2DET_R`[src]

Bit 3 - DM pull-up detection status

`impl R<u32, Reg<u32, _OTG_HS_CID>>`[src]

`pub fn product_id(&self) -> PRODUCT_ID_R`[src]

Bits 0:31 - Product ID field

`impl R<u32, Reg<u32, _OTG_HS_HPTXFSIZ>>`[src]

`pub fn ptxsa(&self) -> PTXSA_R`[src]

Bits 0:15 - Host periodic TxFIFO start address

`pub fn ptxfd(&self) -> PTXFD_R`[src]

Bits 16:31 - Host periodic TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF1>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF2>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF3>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF4>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF5>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF6>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF7>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_GRXSTSR_DEVICE>>`[src]

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 0:3 - Endpoint number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`pub fn frmnum(&self) -> FRMNUM_R`[src]

Bits 21:24 - Frame number

`impl R<u32, Reg<u32, _OTG_HS_GRXSTSP_DEVICE>>`[src]

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 0:3 - Endpoint number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`pub fn frmnum(&self) -> FRMNUM_R`[src]

Bits 21:24 - Frame number

`impl R<u32, Reg<u32, _OTG_HS_GLPMCFG>>`[src]

`pub fn lpmen(&self) -> LPMEN_R`[src]

Bit 0 - LPM support enable

`pub fn lpmack(&self) -> LPMACK_R`[src]

Bit 1 - LPM token acknowledge enable

`pub fn besl(&self) -> BESL_R`[src]

Bits 2:5 - Best effort service latency

`pub fn remwake(&self) -> REMWAKE_R`[src]

Bit 6 - bRemoteWake value

`pub fn l1ssen(&self) -> L1SSEN_R`[src]

Bit 7 - L1 Shallow Sleep enable

`pub fn beslthrs(&self) -> BESLTHRS_R`[src]

Bits 8:11 - BESL threshold

`pub fn l1dsen(&self) -> L1DSEN_R`[src]

Bit 12 - L1 deep sleep enable

`pub fn lpmrst(&self) -> LPMRST_R`[src]

Bits 13:14 - LPM response

`pub fn slpsts(&self) -> SLPSTS_R`[src]

Bit 15 - Port sleep status

`pub fn l1rsmok(&self) -> L1RSMOK_R`[src]

Bit 16 - Sleep State Resume OK

`pub fn lpmchidx(&self) -> LPMCHIDX_R`[src]

Bits 17:20 - LPM Channel Index

`pub fn lpmrcnt(&self) -> LPMRCNT_R`[src]

Bits 21:23 - LPM retry count

`pub fn sndlpm(&self) -> SNDLPM_R`[src]

Bit 24 - Send LPM transaction

`pub fn lpmrcntsts(&self) -> LPMRCNTSTS_R`[src]

Bits 25:27 - LPM retry count status

`pub fn enbesl(&self) -> ENBESL_R`[src]

Bit 28 - Enable best effort service latency

`impl R<u32, Reg<u32, _OTG_HS_GI2CCTL>>`[src]

`pub fn bsydne(&self) -> BSYDNE_R`[src]

Bit 31 - I2C Busy/Done

`pub fn rw(&self) -> RW_R`[src]

Bit 30 - Read/Write Indicator

`pub fn i2cdatse0(&self) -> I2CDATSE0_R`[src]

Bit 28 - I2C DatSe0 USB mode

`pub fn i2cdevadr(&self) -> I2CDEVADR_R`[src]

Bits 26:27 - I2C Device Address

`pub fn ack(&self) -> ACK_R`[src]

Bit 24 - I2C ACK

`pub fn i2cen(&self) -> I2CEN_R`[src]

Bit 23 - I2C Enable

`pub fn addr(&self) -> ADDR_R`[src]

Bits 16:22 - I2C Address

`pub fn regaddr(&self) -> REGADDR_R`[src]

Bits 8:15 - I2C Register Address

`pub fn rwdata(&self) -> RWDATA_R`[src]

Bits 0:7 - I2C Read/Write Data

`impl R<u32, Reg<u32, _OTG_HS_PCGCR>>`[src]

`pub fn stppclk(&self) -> STPPCLK_R`[src]

Bit 0 - Stop PHY clock

`pub fn gatehclk(&self) -> GATEHCLK_R`[src]

Bit 1 - Gate HCLK

`pub fn physusp(&self) -> PHYSUSP_R`[src]

Bit 4 - PHY suspended

`impl R<u32, Reg<u32, _OTG_HS_DCFG>>`[src]

`pub fn dspd(&self) -> DSPD_R`[src]

Bits 0:1 - Device speed

`pub fn nzlsohsk(&self) -> NZLSOHSK_R`[src]

Bit 2 - Nonzero-length status OUT handshake

`pub fn dad(&self) -> DAD_R`[src]

Bits 4:10 - Device address

`pub fn pfivl(&self) -> PFIVL_R`[src]

Bits 11:12 - Periodic (micro)frame interval

`pub fn perschivl(&self) -> PERSCHIVL_R`[src]

Bits 24:25 - Periodic scheduling interval

`impl R<u32, Reg<u32, _OTG_HS_DCTL>>`[src]

`pub fn rwusig(&self) -> RWUSIG_R`[src]

Bit 0 - Remote wakeup signaling

`pub fn sdis(&self) -> SDIS_R`[src]

Bit 1 - Soft disconnect

`pub fn ginsts(&self) -> GINSTS_R`[src]

Bit 2 - Global IN NAK status

`pub fn gonsts(&self) -> GONSTS_R`[src]

Bit 3 - Global OUT NAK status

`pub fn tctl(&self) -> TCTL_R`[src]

Bits 4:6 - Test control

`pub fn poprgdne(&self) -> POPRGDNE_R`[src]

Bit 11 - Power-on programming done

`impl R<u32, Reg<u32, _OTG_HS_DSTS>>`[src]

`pub fn suspsts(&self) -> SUSPSTS_R`[src]

Bit 0 - Suspend status

`pub fn enumspd(&self) -> ENUMSPD_R`[src]

Bits 1:2 - Enumerated speed

`pub fn eerr(&self) -> EERR_R`[src]

Bit 3 - Erratic error

`pub fn fnsof(&self) -> FNSOF_R`[src]

Bits 8:21 - Frame number of the received SOF

`impl R<u32, Reg<u32, _OTG_HS_DIEPMSK>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed interrupt mask

`pub fn epdm(&self) -> EPDM_R`[src]

Bit 1 - Endpoint disabled interrupt mask

`pub fn tom(&self) -> TOM_R`[src]

Bit 3 - Timeout condition mask (nonisochronous endpoints)

`pub fn ittxfemsk(&self) -> ITTXFEMSK_R`[src]

Bit 4 - IN token received when TxFIFO empty mask

`pub fn inepnmm(&self) -> INEPNMM_R`[src]

Bit 5 - IN token received with EP mismatch mask

`pub fn inepnem(&self) -> INEPNEM_R`[src]

Bit 6 - IN endpoint NAK effective mask

`pub fn txfurm(&self) -> TXFURM_R`[src]

Bit 8 - FIFO underrun mask

`pub fn bim(&self) -> BIM_R`[src]

Bit 9 - BNA interrupt mask

`impl R<u32, Reg<u32, _OTG_HS_DOEPMSK>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed interrupt mask

`pub fn epdm(&self) -> EPDM_R`[src]

Bit 1 - Endpoint disabled interrupt mask

`pub fn stupm(&self) -> STUPM_R`[src]

Bit 3 - SETUP phase done mask

`pub fn otepdm(&self) -> OTEPDM_R`[src]

Bit 4 - OUT token received when endpoint disabled mask

`pub fn b2bstup(&self) -> B2BSTUP_R`[src]

Bit 6 - Back-to-back SETUP packets received mask

`pub fn opem(&self) -> OPEM_R`[src]

Bit 8 - OUT packet error mask

`pub fn boim(&self) -> BOIM_R`[src]

Bit 9 - BNA interrupt mask

`impl R<u32, Reg<u32, _OTG_HS_DAINT>>`[src]

`pub fn iepint(&self) -> IEPINT_R`[src]

Bits 0:15 - IN endpoint interrupt bits

`pub fn oepint(&self) -> OEPINT_R`[src]

Bits 16:31 - OUT endpoint interrupt bits

`impl R<u32, Reg<u32, _OTG_HS_DAINTMSK>>`[src]

`pub fn iepm(&self) -> IEPM_R`[src]

Bits 0:15 - IN EP interrupt mask bits

`pub fn oepm(&self) -> OEPM_R`[src]

Bits 16:31 - OUT EP interrupt mask bits

`impl R<u32, Reg<u32, _OTG_HS_DVBUSDIS>>`[src]

`pub fn vbusdt(&self) -> VBUSDT_R`[src]

Bits 0:15 - Device VBUS discharge time

`impl R<u32, Reg<u32, _OTG_HS_DVBUSPULSE>>`[src]

`pub fn dvbusp(&self) -> DVBUSP_R`[src]

Bits 0:11 - Device VBUS pulsing time

`impl R<u32, Reg<u32, _OTG_HS_DTHRCTL>>`[src]

`pub fn nonisothren(&self) -> NONISOTHREN_R`[src]

Bit 0 - Nonisochronous IN endpoints threshold enable

`pub fn isothren(&self) -> ISOTHREN_R`[src]

Bit 1 - ISO IN endpoint threshold enable

`pub fn txthrlen(&self) -> TXTHRLEN_R`[src]

Bits 2:10 - Transmit threshold length

`pub fn rxthren(&self) -> RXTHREN_R`[src]

Bit 16 - Receive threshold enable

`pub fn rxthrlen(&self) -> RXTHRLEN_R`[src]

Bits 17:25 - Receive threshold length

`pub fn arpen(&self) -> ARPEN_R`[src]

Bit 27 - Arbiter parking enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPEMPMSK>>`[src]

`pub fn ineptxfem(&self) -> INEPTXFEM_R`[src]

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

`impl R<u32, Reg<u32, _OTG_HS_DEACHINT>>`[src]

`pub fn iep1int(&self) -> IEP1INT_R`[src]

Bit 1 - IN endpoint 1interrupt bit

`pub fn oep1int(&self) -> OEP1INT_R`[src]

Bit 17 - OUT endpoint 1 interrupt bit

`impl R<u32, Reg<u32, _OTG_HS_DEACHINTMSK>>`[src]

`pub fn iep1intm(&self) -> IEP1INTM_R`[src]

Bit 1 - IN Endpoint 1 interrupt mask bit

`pub fn oep1intm(&self) -> OEP1INTM_R`[src]

Bit 17 - OUT Endpoint 1 interrupt mask bit

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL0>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL1>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL2>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL3>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL4>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL5>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL6>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL7>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT0>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT1>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT2>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT3>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT4>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT5>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT6>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT7>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPTSIZ0>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bit 15 - USB active endpoint

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL1>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even odd frame/Endpoint data PID

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL2>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even odd frame/Endpoint data PID

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL3>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL5>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even odd frame/Endpoint data PID

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL6>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even odd frame/Endpoint data PID

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL7>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even odd frame/Endpoint data PID

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPTSIZ5>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`impl R<u32, Reg<u32, _OTG_HS_DOEPTSIZ6>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`impl R<u32, Reg<u32, _OTG_HS_DOEPTSIZ7>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`impl R<bool, WDGA_A>`[src]

`pub fn variant(&self) -> WDGA_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn wdga(&self) -> WDGA_R`[src]

Bit 7 - Activation bit

`pub fn t(&self) -> T_R`[src]

Bits 0:6 - 7-bit counter (MSB to LSB)

`impl R<bool, EWI_A>`[src]

`pub fn variant(&self) -> Variant<bool, EWI_A>`[src]

Get enumerated values variant

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u8, WDGTB_A>`[src]

`pub fn variant(&self) -> WDGTB_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u32, Reg<u32, _CFR>>`[src]

`pub fn ewi(&self) -> EWI_R`[src]

Bit 9 - Early wakeup interrupt

`pub fn w(&self) -> W_R`[src]

Bits 0:6 - 7-bit window value

`pub fn wdgtb(&self) -> WDGTB_R`[src]

Bits 7:8 - Timer base

`impl R<bool, EWIF_A>`[src]

`pub fn variant(&self) -> EWIF_A`[src]

Get enumerated values variant

`pub fn is_pending(&self) -> bool`[src]

Checks if the value of the field is PENDING

`pub fn is_finished(&self) -> bool`[src]

Checks if the value of the field is FINISHED

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn ewif(&self) -> EWIF_R`[src]

Bit 0 - Early wakeup interrupt flag

`impl R<u32, Reg<u32, _CSR>>`[src]

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 0 - Counter enable

`pub fn tickint(&self) -> TICKINT_R`[src]

Bit 1 - SysTick exception request enable

`pub fn clksource(&self) -> CLKSOURCE_R`[src]

Bit 2 - Clock source selection

`pub fn countflag(&self) -> COUNTFLAG_R`[src]

Bit 16 - COUNTFLAG

`impl R<u32, Reg<u32, _RVR>>`[src]

`pub fn reload(&self) -> RELOAD_R`[src]

Bits 0:23 - RELOAD value

`impl R<u32, Reg<u32, _CVR>>`[src]

`pub fn current(&self) -> CURRENT_R`[src]

Bits 0:23 - Current counter value

`impl R<u32, Reg<u32, _CALIB>>`[src]

`pub fn tenms(&self) -> TENMS_R`[src]

Bits 0:23 - Calibration value

`pub fn skew(&self) -> SKEW_R`[src]

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

`pub fn noref(&self) -> NOREF_R`[src]

Bit 31 - NOREF flag. Reads as zero

`impl R<u32, Reg<u32, _STIR>>`[src]

`pub fn intid(&self) -> INTID_R`[src]

Bits 0:8 - Software generated interrupt ID

`impl R<u32, Reg<u32, _CPACR>>`[src]

`pub fn cp(&self) -> CP_R`[src]

Bits 20:23 - CP

`impl R<u32, Reg<u32, _ACTRL>>`[src]

`pub fn disfold(&self) -> DISFOLD_R`[src]

Bit 2 - DISFOLD

`pub fn fpexcodis(&self) -> FPEXCODIS_R`[src]

Bit 10 - FPEXCODIS

`pub fn disramode(&self) -> DISRAMODE_R`[src]

Bit 11 - DISRAMODE

`pub fn disitmatbflush(&self) -> DISITMATBFLUSH_R`[src]

Bit 12 - DISITMATBFLUSH

`impl R<u32, Reg<u32, _CLIDR>>`[src]

`pub fn cl1(&self) -> CL1_R`[src]

Bits 0:2 - CL1

`pub fn cl2(&self) -> CL2_R`[src]

Bits 3:5 - CL2

`pub fn cl3(&self) -> CL3_R`[src]

Bits 6:8 - CL3

`pub fn cl4(&self) -> CL4_R`[src]

Bits 9:11 - CL4

`pub fn cl5(&self) -> CL5_R`[src]

Bits 12:14 - CL5

`pub fn cl6(&self) -> CL6_R`[src]

Bits 15:17 - CL6

`pub fn cl7(&self) -> CL7_R`[src]

Bits 18:20 - CL7

`pub fn lo_uis(&self) -> LOUIS_R`[src]

Bits 21:23 - LoUIS

`pub fn lo_c(&self) -> LOC_R`[src]

Bits 24:26 - LoC

`pub fn lo_u(&self) -> LOU_R`[src]

Bits 27:29 - LoU

`impl R<u32, Reg<u32, _CTR>>`[src]

`pub fn _imin_line(&self) -> _IMINLINE_R`[src]

Bits 0:3 - IminLine

`pub fn dmin_line(&self) -> DMINLINE_R`[src]

Bits 16:19 - DMinLine

`pub fn erg(&self) -> ERG_R`[src]

Bits 20:23 - ERG

`pub fn cwg(&self) -> CWG_R`[src]

Bits 24:27 - CWG

`pub fn format(&self) -> FORMAT_R`[src]

Bits 29:31 - Format

`impl R<u32, Reg<u32, _CCSIDR>>`[src]

`pub fn line_size(&self) -> LINESIZE_R`[src]

Bits 0:2 - LineSize

`pub fn associativity(&self) -> ASSOCIATIVITY_R`[src]

Bits 3:12 - Associativity

`pub fn num_sets(&self) -> NUMSETS_R`[src]

Bits 13:27 - NumSets

`pub fn wa(&self) -> WA_R`[src]

Bit 28 - WA

`pub fn ra(&self) -> RA_R`[src]

Bit 29 - RA

`pub fn wb(&self) -> WB_R`[src]

Bit 30 - WB

`pub fn wt(&self) -> WT_R`[src]

Bit 31 - WT

`impl R<u32, Reg<u32, _ITCMCR>>`[src]

`pub fn en(&self) -> EN_R`[src]

Bit 0 - EN

`pub fn rmw(&self) -> RMW_R`[src]

Bit 1 - RMW

`pub fn reten(&self) -> RETEN_R`[src]

Bit 2 - RETEN

`pub fn sz(&self) -> SZ_R`[src]

Bits 3:6 - SZ

`impl R<u32, Reg<u32, _DTCMCR>>`[src]

`pub fn en(&self) -> EN_R`[src]

Bit 0 - EN

`pub fn rmw(&self) -> RMW_R`[src]

Bit 1 - RMW

`pub fn reten(&self) -> RETEN_R`[src]

Bit 2 - RETEN

`pub fn sz(&self) -> SZ_R`[src]

Bits 3:6 - SZ

`impl R<u32, Reg<u32, _AHBPCR>>`[src]

`pub fn en(&self) -> EN_R`[src]

Bit 0 - EN

`pub fn sz(&self) -> SZ_R`[src]

Bits 1:3 - SZ

`impl R<u32, Reg<u32, _CACR>>`[src]

`pub fn siwt(&self) -> SIWT_R`[src]

Bit 0 - SIWT

`pub fn eccen(&self) -> ECCEN_R`[src]

Bit 1 - ECCEN

`pub fn forcewt(&self) -> FORCEWT_R`[src]

Bit 2 - FORCEWT

`impl R<u32, Reg<u32, _AHBSCR>>`[src]

`pub fn ctl(&self) -> CTL_R`[src]

Bits 0:1 - CTL

`pub fn tpri(&self) -> TPRI_R`[src]

Bits 2:10 - TPRI

`pub fn initcount(&self) -> INITCOUNT_R`[src]

Bits 11:15 - INITCOUNT

`impl R<u32, Reg<u32, _ABFSR>>`[src]

`pub fn itcm(&self) -> ITCM_R`[src]

Bit 0 - ITCM

`pub fn dtcm(&self) -> DTCM_R`[src]

Bit 1 - DTCM

`pub fn ahbp(&self) -> AHBP_R`[src]

Bit 2 - AHBP

`pub fn axim(&self) -> AXIM_R`[src]

Bit 3 - AXIM

`pub fn eppb(&self) -> EPPB_R`[src]

Bit 4 - EPPB

`pub fn aximtype(&self) -> AXIMTYPE_R`[src]

Bits 8:9 - AXIMTYPE

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn keysize(&self) -> KEYSIZE_R`[src]

Bit 18 - Key size selection

`pub fn chmod2(&self) -> CHMOD2_R`[src]

Bit 16 - AES chaining mode Bit2

`pub fn gcmph(&self) -> GCMPH_R`[src]

Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected

`pub fn dmaouten(&self) -> DMAOUTEN_R`[src]

Bit 12 - Enable DMA management of data output phase

`pub fn dmainen(&self) -> DMAINEN_R`[src]

Bit 11 - Enable DMA management of data input phase

`pub fn errie(&self) -> ERRIE_R`[src]

Bit 10 - Error interrupt enable

`pub fn ccfie(&self) -> CCFIE_R`[src]

Bit 9 - CCF flag interrupt enable

`pub fn errc(&self) -> ERRC_R`[src]

Bit 8 - Error clear

`pub fn ccfc(&self) -> CCFC_R`[src]

Bit 7 - Computation Complete Flag Clear

`pub fn chmod10(&self) -> CHMOD10_R`[src]

Bits 5:6 - AES chaining mode Bit1 Bit0

`pub fn mode(&self) -> MODE_R`[src]

Bits 3:4 - AES operating mode

`pub fn datatype(&self) -> DATATYPE_R`[src]

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

`pub fn en(&self) -> EN_R`[src]

Bit 0 - AES enable

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn busy(&self) -> BUSY_R`[src]

Bit 3 - Busy flag

`pub fn wrerr(&self) -> WRERR_R`[src]

Bit 2 - Write error flag

`pub fn rderr(&self) -> RDERR_R`[src]

Bit 1 - Read error flag

`pub fn ccf(&self) -> CCF_R`[src]

Bit 0 - Computation complete flag

`impl R<u32, Reg<u32, _DINR>>`[src]

`pub fn aes_dinr(&self) -> AES_DINR_R`[src]

Bits 0:31 - Data Input Register

`impl R<u32, Reg<u32, _DOUTR>>`[src]

`pub fn aes_doutr(&self) -> AES_DOUTR_R`[src]

Bits 0:31 - Data output register

`impl R<u32, Reg<u32, _KEYR0>>`[src]

`pub fn aes_keyr0(&self) -> AES_KEYR0_R`[src]

Bits 0:31 - Data Output Register (LSB key [31:0])

`impl R<u32, Reg<u32, _KEYR1>>`[src]

`pub fn aes_keyr1(&self) -> AES_KEYR1_R`[src]

Bits 0:31 - AES key register (key [63:32])

`impl R<u32, Reg<u32, _KEYR2>>`[src]

`pub fn aes_keyr2(&self) -> AES_KEYR2_R`[src]

Bits 0:31 - AES key register (key [95:64])

`impl R<u32, Reg<u32, _KEYR3>>`[src]

`pub fn aes_keyr3(&self) -> AES_KEYR3_R`[src]

Bits 0:31 - AES key register (MSB key [127:96])

`impl R<u32, Reg<u32, _IVR0>>`[src]

`pub fn aes_ivr0(&self) -> AES_IVR0_R`[src]

Bits 0:31 - initialization vector register (LSB IVR [31:0])

`impl R<u32, Reg<u32, _IVR1>>`[src]

`pub fn aes_ivr1(&self) -> AES_IVR1_R`[src]

Bits 0:31 - Initialization Vector Register (IVR [63:32])

`impl R<u32, Reg<u32, _IVR2>>`[src]

`pub fn aes_ivr2(&self) -> AES_IVR2_R`[src]

Bits 0:31 - Initialization Vector Register (IVR [95:64])

`impl R<u32, Reg<u32, _IVR3>>`[src]

`pub fn aes_ivr3(&self) -> AES_IVR3_R`[src]

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

`impl R<u32, Reg<u32, _KEYR4>>`[src]

`pub fn aes_keyr4(&self) -> AES_KEYR4_R`[src]

Bits 0:31 - AES key register (MSB key [159:128])

`impl R<u32, Reg<u32, _KEYR5>>`[src]

`pub fn aes_keyr5(&self) -> AES_KEYR5_R`[src]

Bits 0:31 - AES key register (MSB key [191:160])

`impl R<u32, Reg<u32, _KEYR6>>`[src]

`pub fn aes_keyr6(&self) -> AES_KEYR6_R`[src]

Bits 0:31 - AES key register (MSB key [223:192])

`impl R<u32, Reg<u32, _KEYR7>>`[src]

`pub fn aes_keyr7(&self) -> AES_KEYR7_R`[src]

Bits 0:31 - AES key register (MSB key [255:224])

`impl R<u32, Reg<u32, _SUSP0R>>`[src]

`pub fn aes_susp0r(&self) -> AES_SUSP0R_R`[src]

Bits 0:31 - AES suspend register 0

`impl R<u32, Reg<u32, _SUSP1R>>`[src]

`pub fn aes_susp1r(&self) -> AES_SUSP1R_R`[src]

Bits 0:31 - AES suspend register 1

`impl R<u32, Reg<u32, _SUSP2R>>`[src]

`pub fn aes_susp2r(&self) -> AES_SUSP2R_R`[src]

Bits 0:31 - AES suspend register 2

`impl R<u32, Reg<u32, _SUSP3R>>`[src]

`pub fn aes_susp3r(&self) -> AES_SUSP3R_R`[src]

Bits 0:31 - AES suspend register 3

`impl R<u32, Reg<u32, _SUSP4R>>`[src]

`pub fn aes_susp4r(&self) -> AES_SUSP4R_R`[src]

Bits 0:31 - AES suspend register 4

`impl R<u32, Reg<u32, _SUSP5R>>`[src]

`pub fn aes_susp5r(&self) -> AES_SUSP5R_R`[src]

Bits 0:31 - AES suspend register 5

`impl R<u32, Reg<u32, _SUSP6R>>`[src]

`pub fn aes_susp6r(&self) -> AES_SUSP6R_R`[src]

Bits 0:31 - AES suspend register 6

`impl R<u32, Reg<u32, _SUSP7R>>`[src]

`pub fn aes_susp7r(&self) -> AES_SUSP7R_R`[src]

Bits 0:31 - AES suspend register 7

`impl R<u32, Reg<u32, _PLL1>>`[src]

`pub fn pll1en(&self) -> PLL1EN_R`[src]

Bit 0 - Enable the PLL1 inside PHY

`pub fn pll1sel(&self) -> PLL1SEL_R`[src]

Bits 1:3 - : Controls the PHY PLL1 input clock frequency selection

`impl R<u32, Reg<u32, _TUNE>>`[src]

`pub fn incurren(&self) -> INCURREN_R`[src]

Bit 0 - Controls the current boosting function

`pub fn incurrint(&self) -> INCURRINT_R`[src]

Bit 1 - Controls PHY current boosting

`pub fn lfscapen(&self) -> LFSCAPEN_R`[src]

Bit 2 - : Enables the Low Full Speed feedback capacitor

`pub fn hsdrvslew(&self) -> HSDRVSLEW_R`[src]

Bit 3 - Controls the HS driver slew rate

`pub fn hsdrvdccur(&self) -> HSDRVDCCUR_R`[src]

Bit 4 - Decreases the HS driver DC level

`pub fn hsdrvdclev(&self) -> HSDRVDCLEV_R`[src]

Bit 5 - Increases the HS Driver DC level. Not applicable during the HS Test J and Test K data transfer

`pub fn hsdrvcurincr(&self) -> HSDRVCURINCR_R`[src]

Bit 6 - Enable the HS driver current increase feature

`pub fn fsdrvrfadj(&self) -> FSDRVRFADJ_R`[src]

Bit 7 - Tuning pin to adjust the full speed rise/fall time

`pub fn hsdrvrfred(&self) -> HSDRVRFRED_R`[src]

Bit 8 - High Speed rise-fall reduction enable

`pub fn hsdrvchkitrm(&self) -> HSDRVCHKITRM_R`[src]

Bits 9:12 - HS Driver current trimming pins for choke compensation

`pub fn hsdrvchkztrm(&self) -> HSDRVCHKZTRM_R`[src]

Bits 13:14 - Controls the PHY bus HS driver impedance tuning for choke compensation

`pub fn sqlchctl(&self) -> SQLCHCTL_R`[src]

Bits 15:16 - Adjust the squelch DC threshold value

`pub fn hdrxgneqen(&self) -> HDRXGNEQEN_R`[src]

Bit 17 - Enables the HS Rx Gain Equalizer

`pub fn stagsel(&self) -> STAGSEL_R`[src]

Bit 18 - HS Tx staggering enable

`pub fn hsfallpreem(&self) -> HSFALLPREEM_R`[src]

Bit 19 - HS Fall time control of single ended signals during pre-emphasis

`pub fn hsrxoff(&self) -> HSRXOFF_R`[src]

Bits 20:21 - : HS Receiver Offset adjustment

`pub fn shtcctctlprot(&self) -> SHTCCTCTLPROT_R`[src]

Bit 22 - Enables the short circuit protection circuitry in LS/FS driver

`pub fn sqlbyp(&self) -> SQLBYP_R`[src]

Bit 23 - This pin is used to bypass the squelch inter-locking circuitry

`impl R<u32, Reg<u32, _LDO>>`[src]

`pub fn ldo_used(&self) -> LDO_USED_R`[src]

Bit 0 - Indicates the presence of the LDO in the chip

`pub fn ldo_status(&self) -> LDO_STATUS_R`[src]

Bit 1 - Monitors the status of the PHY's LDO

`pub fn ldo_disable(&self) -> LDO_DISABLE_R`[src]

Bit 2 - Controls disable of the High Speed PHY's LDO

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn ie(&self) -> IE_R`[src]

Bit 3 - Interrupt enable

`pub fn rngen(&self) -> RNGEN_R`[src]

Bit 2 - Random number generator enable

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn seis(&self) -> SEIS_R`[src]

Bit 6 - Seed error interrupt status

`pub fn ceis(&self) -> CEIS_R`[src]

Bit 5 - Clock error interrupt status

`pub fn secs(&self) -> SECS_R`[src]

Bit 2 - Seed error current status

`pub fn cecs(&self) -> CECS_R`[src]

Bit 1 - Clock error current status

`pub fn drdy(&self) -> DRDY_R`[src]

Bit 0 - Data ready

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn rndata(&self) -> RNDATA_R`[src]

Bits 0:31 - Random data

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn dmae(&self) -> DMAE_R`[src]

Bit 3 - DMA enable

`pub fn datatype(&self) -> DATATYPE_R`[src]

Bits 4:5 - Data type selection

`pub fn mode(&self) -> MODE_R`[src]

Bit 6 - Mode selection

`pub fn algo0(&self) -> ALGO0_R`[src]

Bit 7 - Algorithm selection

`pub fn nbw(&self) -> NBW_R`[src]

Bits 8:11 - Number of words already pushed

`pub fn dinne(&self) -> DINNE_R`[src]

Bit 12 - DIN not empty

`pub fn mdmat(&self) -> MDMAT_R`[src]

Bit 13 - Multiple DMA Transfers

`pub fn lkey(&self) -> LKEY_R`[src]

Bit 16 - Long key selection

`pub fn algo1(&self) -> ALGO1_R`[src]

Bit 18 - ALGO

`impl R<u32, Reg<u32, _DIN>>`[src]

`pub fn datain(&self) -> DATAIN_R`[src]

Bits 0:31 - Data input

`impl R<u32, Reg<u32, _STR>>`[src]

`pub fn nblw(&self) -> NBLW_R`[src]

Bits 0:4 - Number of valid bits in the last word of the message

`impl R<u32, Reg<u32, _HR>>`[src]

`pub fn h(&self) -> H_R`[src]

Bits 0:31 - H0

`impl R<u32, Reg<u32, _IMR>>`[src]

`pub fn dcie(&self) -> DCIE_R`[src]

Bit 1 - Digest calculation completion interrupt enable

`pub fn dinie(&self) -> DINIE_R`[src]

Bit 0 - Data input interrupt enable

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn busy(&self) -> BUSY_R`[src]

Bit 3 - Busy bit

`pub fn dmas(&self) -> DMAS_R`[src]

Bit 2 - DMA Status

`pub fn dcis(&self) -> DCIS_R`[src]

Bit 1 - Digest calculation completion interrupt status

`pub fn dinis(&self) -> DINIS_R`[src]

Bit 0 - Data input interrupt status

`impl R<u32, Reg<u32, _CSR>>`[src]

`pub fn csr(&self) -> CSR_R`[src]

Bits 0:31 - CSR0

`impl R<u32, Reg<u32, _HASH_HR>>`[src]

`pub fn h(&self) -> H_R`[src]

Bits 0:31 - H0

`impl R<u32, Reg<u32, _IVLR>>`[src]

`pub fn iv(&self) -> IV_R`[src]

Bits 0:31 - IV31

`impl R<u32, Reg<u32, _IVRR>>`[src]

`pub fn iv(&self) -> IV_R`[src]

Bits 0:31 - IV63

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn algodir(&self) -> ALGODIR_R`[src]

Bit 2 - Algorithm direction

`pub fn algomode0(&self) -> ALGOMODE0_R`[src]

Bits 3:5 - Algorithm mode

`pub fn datatype(&self) -> DATATYPE_R`[src]

Bits 6:7 - Data type selection

`pub fn keysize(&self) -> KEYSIZE_R`[src]

Bits 8:9 - Key size selection (AES mode only)

`pub fn crypen(&self) -> CRYPEN_R`[src]

Bit 15 - Cryptographic processor enable

`pub fn gcm_ccmph(&self) -> GCM_CCMPH_R`[src]

Bits 16:17 - GCM_CCMPH

`pub fn algomode3(&self) -> ALGOMODE3_R`[src]

Bit 19 - ALGOMODE

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn busy(&self) -> BUSY_R`[src]

Bit 4 - Busy bit

`pub fn offu(&self) -> OFFU_R`[src]

Bit 3 - Output FIFO full

`pub fn ofne(&self) -> OFNE_R`[src]

Bit 2 - Output FIFO not empty

`pub fn ifnf(&self) -> IFNF_R`[src]

Bit 1 - Input FIFO not full

`pub fn ifem(&self) -> IFEM_R`[src]

Bit 0 - Input FIFO empty

`impl R<u32, Reg<u32, _DIN>>`[src]

`pub fn datain(&self) -> DATAIN_R`[src]

Bits 0:31 - Data input

`impl R<u32, Reg<u32, _DOUT>>`[src]

`pub fn dataout(&self) -> DATAOUT_R`[src]

Bits 0:31 - Data output

`impl R<u32, Reg<u32, _DMACR>>`[src]

`pub fn doen(&self) -> DOEN_R`[src]

Bit 1 - DMA output enable

`pub fn dien(&self) -> DIEN_R`[src]

Bit 0 - DMA input enable

`impl R<u32, Reg<u32, _IMSCR>>`[src]

`pub fn outim(&self) -> OUTIM_R`[src]

Bit 1 - Output FIFO service interrupt mask

`pub fn inim(&self) -> INIM_R`[src]

Bit 0 - Input FIFO service interrupt mask

`impl R<u32, Reg<u32, _RISR>>`[src]

`pub fn outris(&self) -> OUTRIS_R`[src]

Bit 1 - Output FIFO service raw interrupt status

`pub fn inris(&self) -> INRIS_R`[src]

Bit 0 - Input FIFO service raw interrupt status

`impl R<u32, Reg<u32, _MISR>>`[src]

`pub fn outmis(&self) -> OUTMIS_R`[src]

Bit 1 - Output FIFO service masked interrupt status

`pub fn inmis(&self) -> INMIS_R`[src]

Bit 0 - Input FIFO service masked interrupt status

`impl R<u32, Reg<u32, _CSGCMCCMR>>`[src]

`pub fn csgcmccm0r(&self) -> CSGCMCCM0R_R`[src]

Bits 0:31 - CSGCMCCM0R

`impl R<u32, Reg<u32, _CSGCMR>>`[src]

`pub fn csgcmr(&self) -> CSGCMR_R`[src]

Bits 0:31 - CSGCM0R

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 14 - DCMI enable

`pub fn edm(&self) -> EDM_R`[src]

Bits 10:11 - Extended data mode

`pub fn fcrc(&self) -> FCRC_R`[src]

Bits 8:9 - Frame capture rate control

`pub fn vspol(&self) -> VSPOL_R`[src]

Bit 7 - Vertical synchronization polarity

`pub fn hspol(&self) -> HSPOL_R`[src]

Bit 6 - Horizontal synchronization polarity

`pub fn pckpol(&self) -> PCKPOL_R`[src]

Bit 5 - Pixel clock polarity

`pub fn ess(&self) -> ESS_R`[src]

Bit 4 - Embedded synchronization select

`pub fn jpeg(&self) -> JPEG_R`[src]

Bit 3 - JPEG format

`pub fn crop(&self) -> CROP_R`[src]

Bit 2 - Crop feature

`pub fn cm(&self) -> CM_R`[src]

Bit 1 - Capture mode

`pub fn capture(&self) -> CAPTURE_R`[src]

Bit 0 - Capture enable

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn fne(&self) -> FNE_R`[src]

Bit 2 - FIFO not empty

`pub fn vsync(&self) -> VSYNC_R`[src]

Bit 1 - VSYNC

`pub fn hsync(&self) -> HSYNC_R`[src]

Bit 0 - HSYNC

`impl R<u32, Reg<u32, _RIS>>`[src]

`pub fn line_ris(&self) -> LINE_RIS_R`[src]

Bit 4 - Line raw interrupt status

`pub fn vsync_ris(&self) -> VSYNC_RIS_R`[src]

Bit 3 - VSYNC raw interrupt status

`pub fn err_ris(&self) -> ERR_RIS_R`[src]

Bit 2 - Synchronization error raw interrupt status

`pub fn ovr_ris(&self) -> OVR_RIS_R`[src]

Bit 1 - Overrun raw interrupt status

`pub fn frame_ris(&self) -> FRAME_RIS_R`[src]

Bit 0 - Capture complete raw interrupt status

`impl R<u32, Reg<u32, _IER>>`[src]

`pub fn line_ie(&self) -> LINE_IE_R`[src]

Bit 4 - Line interrupt enable

`pub fn vsync_ie(&self) -> VSYNC_IE_R`[src]

Bit 3 - VSYNC interrupt enable

`pub fn err_ie(&self) -> ERR_IE_R`[src]

Bit 2 - Synchronization error interrupt enable

`pub fn ovr_ie(&self) -> OVR_IE_R`[src]

Bit 1 - Overrun interrupt enable

`pub fn frame_ie(&self) -> FRAME_IE_R`[src]

Bit 0 - Capture complete interrupt enable

`impl R<u32, Reg<u32, _MIS>>`[src]

`pub fn line_mis(&self) -> LINE_MIS_R`[src]

Bit 4 - Line masked interrupt status

`pub fn vsync_mis(&self) -> VSYNC_MIS_R`[src]

Bit 3 - VSYNC masked interrupt status

`pub fn err_mis(&self) -> ERR_MIS_R`[src]

Bit 2 - Synchronization error masked interrupt status

`pub fn ovr_mis(&self) -> OVR_MIS_R`[src]

Bit 1 - Overrun masked interrupt status

`pub fn frame_mis(&self) -> FRAME_MIS_R`[src]

Bit 0 - Capture complete masked interrupt status

`impl R<u32, Reg<u32, _ESCR>>`[src]

`pub fn fec(&self) -> FEC_R`[src]

Bits 24:31 - Frame end delimiter code

`pub fn lec(&self) -> LEC_R`[src]

Bits 16:23 - Line end delimiter code

`pub fn lsc(&self) -> LSC_R`[src]

Bits 8:15 - Line start delimiter code

`pub fn fsc(&self) -> FSC_R`[src]

Bits 0:7 - Frame start delimiter code

`impl R<u32, Reg<u32, _ESUR>>`[src]

`pub fn feu(&self) -> FEU_R`[src]

Bits 24:31 - Frame end delimiter unmask

`pub fn leu(&self) -> LEU_R`[src]

Bits 16:23 - Line end delimiter unmask

`pub fn lsu(&self) -> LSU_R`[src]

Bits 8:15 - Line start delimiter unmask

`pub fn fsu(&self) -> FSU_R`[src]

Bits 0:7 - Frame start delimiter unmask

`impl R<u32, Reg<u32, _CWSTRT>>`[src]

`pub fn vst(&self) -> VST_R`[src]

Bits 16:28 - Vertical start line count

`pub fn hoffcnt(&self) -> HOFFCNT_R`[src]

Bits 0:13 - Horizontal offset count

`impl R<u32, Reg<u32, _CWSIZE>>`[src]

`pub fn vline(&self) -> VLINE_R`[src]

Bits 16:29 - Vertical line count

`pub fn capcnt(&self) -> CAPCNT_R`[src]

Bits 0:13 - Capture count

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn byte3(&self) -> BYTE3_R`[src]

`pub fn is_bits32(&self) -> bool`[src]

Checks if the value of the field is BITS32

`impl R<u8, MTYP_A>`[src]

`pub fn variant(&self) -> Variant<u8, MTYP_A>`[src]

`pub fn is_bytes256(&self) -> bool`[src]

Checks if the value of the field is BYTES256

`pub fn is_bytes512(&self) -> bool`[src]

Checks if the value of the field is BYTES512

`pub fn is_bytes1024(&self) -> bool`[src]

Checks if the value of the field is BYTES1024

`impl R<u32, Reg<u32, _BCR1>>`[src]

`pub fn cclken(&self) -> CCLKEN_R`[src]

Bit 20 - CCLKEN

`pub fn cburstrw(&self) -> CBURSTRW_R`[src]

Bit 19 - CBURSTRW

`pub fn asyncwait(&self) -> ASYNCWAIT_R`[src]

Bit 15 - ASYNCWAIT

`pub fn extmod(&self) -> EXTMOD_R`[src]

Bit 14 - EXTMOD

`pub fn waiten(&self) -> WAITEN_R`[src]

Bit 13 - WAITEN

`pub fn wren(&self) -> WREN_R`[src]

Bit 12 - WREN

`pub fn waitcfg(&self) -> WAITCFG_R`[src]

Bit 11 - WAITCFG

`pub fn waitpol(&self) -> WAITPOL_R`[src]

Bit 9 - WAITPOL

`pub fn bursten(&self) -> BURSTEN_R`[src]

Bit 8 - BURSTEN

`pub fn faccen(&self) -> FACCEN_R`[src]

Bit 6 - FACCEN

`pub fn mwid(&self) -> MWID_R`[src]

Bits 4:5 - MWID

`pub fn mtyp(&self) -> MTYP_R`[src]

Bits 2:3 - MTYP

`pub fn muxen(&self) -> MUXEN_R`[src]

Bit 1 - MUXEN

`pub fn mbken(&self) -> MBKEN_R`[src]

Bit 0 - MBKEN

`pub fn wrapmod(&self) -> WRAPMOD_R`[src]

Bit 10 - WRAPMOD

`pub fn wfdis(&self) -> WFDIS_R`[src]

Bit 21 - Write FIFO disable

`pub fn cpsize(&self) -> CPSIZE_R`[src]

Bits 16:18 - CRAM page size

`impl R<u8, ACCMOD_A>`[src]

`pub fn variant(&self) -> ACCMOD_A`[src]

Get enumerated values variant

`pub fn is_a(&self) -> bool`[src]

Checks if the value of the field is A

`pub fn is_b(&self) -> bool`[src]

Checks if the value of the field is B

`pub fn is_c(&self) -> bool`[src]

Checks if the value of the field is C

`pub fn is_d(&self) -> bool`[src]

Checks if the value of the field is D

`impl R<u32, Reg<u32, _BTR>>`[src]

`pub fn accmod(&self) -> ACCMOD_R`[src]

Bits 28:29 - ACCMOD

`pub fn datlat(&self) -> DATLAT_R`[src]

Bits 24:27 - DATLAT

`pub fn clkdiv(&self) -> CLKDIV_R`[src]

Bits 20:23 - CLKDIV

`pub fn busturn(&self) -> BUSTURN_R`[src]

`impl R<u8, MWID_A>`[src]

`pub fn variant(&self) -> Variant<u8, MWID_A>`[src]

Get enumerated values variant

`pub fn is_bits8(&self) -> bool`[src]

Checks if the value of the field is BITS8

`pub fn is_bits16(&self) -> bool`[src]

Checks if the value of the field is BITS16

`pub fn is_bits32(&self) -> bool`[src]

Checks if the value of the field is BITS32

`impl R<u8, MTYP_A>`[src]

`pub fn variant(&self) -> Variant<u8, MTYP_A>`[src]

`pub fn is_bytes256(&self) -> bool`[src]

Checks if the value of the field is BYTES256

`pub fn is_bytes512(&self) -> bool`[src]

Checks if the value of the field is BYTES512

`pub fn is_bytes1024(&self) -> bool`[src]

Checks if the value of the field is BYTES1024

`impl R<u32, Reg<u32, _BCR>>`[src]

`pub fn cburstrw(&self) -> CBURSTRW_R`[src]

Bit 19 - CBURSTRW

`pub fn asyncwait(&self) -> ASYNCWAIT_R`[src]

Bit 15 - ASYNCWAIT

`pub fn extmod(&self) -> EXTMOD_R`[src]

Bit 14 - EXTMOD

`pub fn waiten(&self) -> WAITEN_R`[src]

Bit 13 - WAITEN

`pub fn wren(&self) -> WREN_R`[src]

Bit 12 - WREN

`pub fn waitcfg(&self) -> WAITCFG_R`[src]

Bit 11 - WAITCFG

`pub fn wrapmod(&self) -> WRAPMOD_R`[src]

Bit 10 - WRAPMOD

`pub fn waitpol(&self) -> WAITPOL_R`[src]

Bit 9 - WAITPOL

`pub fn bursten(&self) -> BURSTEN_R`[src]

Bit 8 - BURSTEN

`pub fn faccen(&self) -> FACCEN_R`[src]

Bit 6 - FACCEN

`pub fn mwid(&self) -> MWID_R`[src]

Bits 4:5 - MWID

`pub fn mtyp(&self) -> MTYP_R`[src]

Bits 2:3 - MTYP

`pub fn muxen(&self) -> MUXEN_R`[src]

Bit 1 - MUXEN

`pub fn mbken(&self) -> MBKEN_R`[src]

Bit 0 - MBKEN

`pub fn cpsize(&self) -> CPSIZE_R`[src]

Bits 16:18 - CRAM page size

`impl R<u8, ECCPS_A>`[src]

`pub fn variant(&self) -> Variant<u8, ECCPS_A>`[src]

Get enumerated values variant

`pub fn is_bytes256(&self) -> bool`[src]

Checks if the value of the field is BYTES256

`pub fn is_bytes512(&self) -> bool`[src]

Checks if the value of the field is BYTES512

`pub fn is_bytes1024(&self) -> bool`[src]

Checks if the value of the field is BYTES1024

`pub fn is_bytes2048(&self) -> bool`[src]

Checks if the value of the field is BYTES2048

`pub fn is_bytes4096(&self) -> bool`[src]

Checks if the value of the field is BYTES4096

`pub fn is_bytes8192(&self) -> bool`[src]

Checks if the value of the field is BYTES8192

`impl R<bool, ECCEN_A>`[src]

`pub fn variant(&self) -> ECCEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, PWID_A>`[src]

`pub fn variant(&self) -> Variant<u8, PWID_A>`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, PWAITEN_A>`[src]

`pub fn variant(&self) -> PWAITEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _PCR>>`[src]

`pub fn eccps(&self) -> ECCPS_R`[src]

Bits 17:19 - ECCPS

`pub fn tar(&self) -> TAR_R`[src]

Bits 13:16 - TAR

`pub fn tclr(&self) -> TCLR_R`[src]

Bits 9:12 - TCLR

`pub fn eccen(&self) -> ECCEN_R`[src]

Bit 6 - ECCEN

`pub fn pwid(&self) -> PWID_R`[src]

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn fempt(&self) -> FEMPT_R`[src]

Bit 6 - FEMPT

`pub fn ifen(&self) -> IFEN_R`[src]

Bit 5 - IFEN

`pub fn ilen(&self) -> ILEN_R`[src]

Bit 4 - ILEN

`pub fn iren(&self) -> IREN_R`[src]

Bit 3 - IREN

`pub fn ifs(&self) -> IFS_R`[src]

Bit 2 - IFS

`pub fn ils(&self) -> ILS_R`[src]

Bit 1 - ILS

`pub fn irs(&self) -> IRS_R`[src]

Bit 0 - IRS

`impl R<u32, Reg<u32, _PMEM>>`[src]

`pub fn memhiz(&self) -> MEMHIZ_R`[src]

Bits 24:31 - MEMHIZx

`pub fn memhold(&self) -> MEMHOLD_R`[src]

Bits 16:23 - MEMHOLDx

`pub fn memwait(&self) -> MEMWAIT_R`[src]

Bits 8:15 - MEMWAITx

`pub fn memset(&self) -> MEMSET_R`[src]

Bits 0:7 - MEMSETx

`impl R<u32, Reg<u32, _PATT>>`[src]

`pub fn atthiz(&self) -> ATTHIZ_R`[src]

Bits 24:31 - ATTHIZx

`pub fn atthold(&self) -> ATTHOLD_R`[src]

Bits 16:23 - ATTHOLDx

`pub fn attwait(&self) -> ATTWAIT_R`[src]

Bits 8:15 - ATTWAITx

`pub fn attset(&self) -> ATTSET_R`[src]

Bits 0:7 - ATTSETx

`impl R<u32, Reg<u32, _ECCR>>`[src]

`pub fn ecc(&self) -> ECC_R`[src]

Bits 0:31 - ECCx

`impl R<u8, ACCMOD_A>`[src]

`pub fn variant(&self) -> ACCMOD_A`[src]

Get enumerated values variant

`pub fn is_a(&self) -> bool`[src]

Checks if the value of the field is A

`pub fn is_b(&self) -> bool`[src]

Checks if the value of the field is B

`pub fn is_c(&self) -> bool`[src]

Checks if the value of the field is C

`pub fn is_d(&self) -> bool`[src]

Checks if the value of the field is D

`impl R<u32, Reg<u32, _BWTR>>`[src]

`pub fn accmod(&self) -> ACCMOD_R`[src]

Bits 28:29 - ACCMOD

`pub fn datlat(&self) -> DATLAT_R`[src]

Bits 24:27 - DATLAT

`pub fn clkdiv(&self) -> CLKDIV_R`[src]

Bits 20:23 - CLKDIV

`pub fn datast(&self) -> DATAST_R`[src]

Bits 8:15 - DATAST

`pub fn addhld(&self) -> ADDHLD_R`[src]

Bits 4:7 - ADDHLD

`pub fn addset(&self) -> ADDSET_R`[src]

Bits 0:3 - ADDSET

`pub fn busturn(&self) -> BUSTURN_R`[src]

Bits 16:19 - Bus turnaround phase duration

`impl R<u8, NC_A>`[src]

`pub fn variant(&self) -> NC_A`[src]

`pub fn is_clocks3(&self) -> bool`[src]

Checks if the value of the field is CLOCKS3

`impl R<bool, WP_A>`[src]

`pub fn variant(&self) -> WP_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, SDCLK_A>`[src]

`pub fn variant(&self) -> Variant<u8, SDCLK_A>`[src]

`pub fn is_clocks2(&self) -> bool`[src]

Checks if the value of the field is CLOCKS2

`impl R<u32, Reg<u32, _SDCR>>`[src]

`pub fn nc(&self) -> NC_R`[src]

Bits 0:1 - Number of column address bits

`pub fn nr(&self) -> NR_R`[src]

Bits 2:3 - Number of row address bits

`pub fn mwid(&self) -> MWID_R`[src]

Bits 4:5 - Memory data bus width

`pub fn nb(&self) -> NB_R`[src]

Bit 6 - Number of internal banks

`pub fn cas(&self) -> CAS_R`[src]

Bits 7:8 - CAS latency

`pub fn wp(&self) -> WP_R`[src]

Bit 9 - Write protection

`pub fn sdclk(&self) -> SDCLK_R`[src]

Bits 10:11 - SDRAM clock configuration

`pub fn rburst(&self) -> RBURST_R`[src]

Bit 12 - Burst read

`pub fn rpipe(&self) -> RPIPE_R`[src]

Bits 13:14 - Read pipe

`impl R<u32, Reg<u32, _SDTR>>`[src]

`pub fn tmrd(&self) -> TMRD_R`[src]

Bits 0:3 - Load Mode Register to Active

`pub fn txsr(&self) -> TXSR_R`[src]

Bits 4:7 - Exit self-refresh delay

`pub fn tras(&self) -> TRAS_R`[src]

Bits 8:11 - Self refresh time

`pub fn trc(&self) -> TRC_R`[src]

`pub fn is_self_refresh(&self) -> bool`[src]

Checks if the value of the field is SELFREFRESH

`pub fn is_power_down(&self) -> bool`[src]

Checks if the value of the field is POWERDOWN

`impl R<bool, BUSY_A>`[src]

`pub fn variant(&self) -> BUSY_A`[src]

Get enumerated values variant

`pub fn is_not_busy(&self) -> bool`[src]

Checks if the value of the field is NOTBUSY

`pub fn is_busy(&self) -> bool`[src]

Checks if the value of the field is BUSY

`impl R<u32, Reg<u32, _SDSR>>`[src]

`pub fn re(&self) -> RE_R`[src]

Bit 0 - Refresh error flag

`pub fn modes1(&self) -> MODES1_R`[src]

Bits 1:2 - Status Mode for Bank 1

`pub fn modes2(&self) -> MODES2_R`[src]

Bits 3:4 - Status Mode for Bank 2

`pub fn busy(&self) -> BUSY_R`[src]

Bit 5 - Busy status

`impl R<u8, MBURST_A>`[src]

`pub fn variant(&self) -> MBURST_A`[src]

Get enumerated values variant

`pub fn is_single(&self) -> bool`[src]

Checks if the value of the field is SINGLE

`pub fn is_incr4(&self) -> bool`[src]

Checks if the value of the field is INCR4

`pub fn is_incr8(&self) -> bool`[src]

Checks if the value of the field is INCR8

`pub fn is_incr16(&self) -> bool`[src]

Checks if the value of the field is INCR16

`impl R<bool, CT_A>`[src]

`pub fn variant(&self) -> CT_A`[src]

Get enumerated values variant

`pub fn is_memory0(&self) -> bool`[src]

Checks if the value of the field is MEMORY0

`pub fn is_memory1(&self) -> bool`[src]

Checks if the value of the field is MEMORY1

`impl R<bool, DBM_A>`[src]

`pub fn variant(&self) -> DBM_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, PL_A>`[src]

`pub fn variant(&self) -> PL_A`[src]

Get enumerated values variant

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`pub fn is_medium(&self) -> bool`[src]

Checks if the value of the field is MEDIUM

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_very_high(&self) -> bool`[src]

Checks if the value of the field is VERYHIGH

`impl R<bool, PINCOS_A>`[src]

`pub fn variant(&self) -> PINCOS_A`[src]

Get enumerated values variant

`pub fn is_psize(&self) -> bool`[src]

Checks if the value of the field is PSIZE

`pub fn is_fixed4(&self) -> bool`[src]

Checks if the value of the field is FIXED4

`impl R<u8, MSIZE_A>`[src]

`pub fn variant(&self) -> Variant<u8, MSIZE_A>`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn chsel(&self) -> CHSEL_R`[src]

Bits 25:28 - Channel selection

`pub fn mburst(&self) -> MBURST_R`[src]

Bits 23:24 - Memory burst transfer configuration

`pub fn pburst(&self) -> PBURST_R`[src]

Bits 21:22 - Peripheral burst transfer configuration

`pub fn ct(&self) -> CT_R`[src]

Bit 19 - Current target (only in double buffer mode)

`pub fn dbm(&self) -> DBM_R`[src]

Bit 18 - Double buffer mode

`pub fn pl(&self) -> PL_R`[src]

Bits 16:17 - Priority level

`pub fn pincos(&self) -> PINCOS_R`[src]

Bit 15 - Peripheral increment offset size

`pub fn msize(&self) -> MSIZE_R`[src]

Bits 13:14 - Memory data size

`pub fn psize(&self) -> PSIZE_R`[src]

Bits 11:12 - Peripheral data size

`pub fn minc(&self) -> MINC_R`[src]

Bit 10 - Memory increment mode

`pub fn pinc(&self) -> PINC_R`[src]

Bit 9 - Peripheral increment mode

`pub fn circ(&self) -> CIRC_R`[src]

Bit 8 - Circular mode

`pub fn dir(&self) -> DIR_R`[src]

Bits 6:7 - Data transfer direction

`pub fn pfctrl(&self) -> PFCTRL_R`[src]

Bit 5 - Peripheral flow controller

`pub fn tcie(&self) -> TCIE_R`[src]

Bit 4 - Transfer complete interrupt enable

`pub fn htie(&self) -> HTIE_R`[src]

Bit 3 - Half transfer interrupt enable

`pub fn teie(&self) -> TEIE_R`[src]

Bit 2 - Transfer error interrupt enable

`pub fn dmeie(&self) -> DMEIE_R`[src]

Bit 1 - Direct mode error interrupt enable

`pub fn en(&self) -> EN_R`[src]

Bit 0 - Stream enable / flag stream ready when read low

`impl R<u32, Reg<u32, _NDTR>>`[src]

`pub fn ndt(&self) -> NDT_R`[src]

Bits 0:15 - Number of data items to transfer

`impl R<u32, Reg<u32, _PAR>>`[src]

`pub fn pa(&self) -> PA_R`[src]

Bits 0:31 - Peripheral address

`impl R<u32, Reg<u32, _M0AR>>`[src]

`pub fn m0a(&self) -> M0A_R`[src]

Bits 0:31 - Memory 0 address

`impl R<u32, Reg<u32, _M1AR>>`[src]

`pub fn m1a(&self) -> M1A_R`[src]

Bits 0:31 - Memory 1 address (used in case of Double buffer mode)

`impl R<bool, FEIE_A>`[src]

`pub fn variant(&self) -> FEIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, FS_A>`[src]

`pub fn variant(&self) -> Variant<u8, FS_A>`[src]

Get enumerated values variant

`pub fn is_quarter1(&self) -> bool`[src]

Checks if the value of the field is QUARTER1

`pub fn is_quarter2(&self) -> bool`[src]

Checks if the value of the field is QUARTER2

`pub fn is_quarter3(&self) -> bool`[src]

Checks if the value of the field is QUARTER3

`pub fn is_quarter4(&self) -> bool`[src]

Checks if the value of the field is QUARTER4

`pub fn is_empty(&self) -> bool`[src]

Checks if the value of the field is EMPTY

`pub fn is_full(&self) -> bool`[src]

Checks if the value of the field is FULL

`impl R<bool, DMDIS_A>`[src]

`pub fn variant(&self) -> DMDIS_A`[src]

Get enumerated values variant

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`impl R<u8, FTH_A>`[src]

`pub fn variant(&self) -> FTH_A`[src]

Get enumerated values variant

`pub fn is_quarter(&self) -> bool`[src]

Checks if the value of the field is QUARTER

`pub fn is_half(&self) -> bool`[src]

Checks if the value of the field is HALF

`pub fn is_three_quarters(&self) -> bool`[src]

Checks if the value of the field is THREEQUARTERS

`pub fn is_full(&self) -> bool`[src]

Checks if the value of the field is FULL

`impl R<u32, Reg<u32, _FCR>>`[src]

`pub fn feie(&self) -> FEIE_R`[src]

`impl R<u32, Reg<u32, _LISR>>`[src]

`pub fn tcif3(&self) -> TCIF3_R`[src]

Bit 27 - Stream x transfer complete interrupt flag (x = 3..0)

`pub fn htif3(&self) -> HTIF3_R`[src]

Bit 26 - Stream x half transfer interrupt flag (x=3..0)

`pub fn teif3(&self) -> TEIF3_R`[src]

Bit 25 - Stream x transfer error interrupt flag (x=3..0)

`pub fn dmeif3(&self) -> DMEIF3_R`[src]

Bit 24 - Stream x direct mode error interrupt flag (x=3..0)

`pub fn feif3(&self) -> FEIF3_R`[src]

Bit 22 - Stream x FIFO error interrupt flag (x=3..0)

`pub fn tcif2(&self) -> TCIF2_R`[src]

Bit 21 - Stream x transfer complete interrupt flag (x = 3..0)

`pub fn htif2(&self) -> HTIF2_R`[src]

Bit 20 - Stream x half transfer interrupt flag (x=3..0)

`pub fn teif2(&self) -> TEIF2_R`[src]

Bit 19 - Stream x transfer error interrupt flag (x=3..0)

`pub fn dmeif2(&self) -> DMEIF2_R`[src]

Bit 18 - Stream x direct mode error interrupt flag (x=3..0)

`pub fn feif2(&self) -> FEIF2_R`[src]

Bit 16 - Stream x FIFO error interrupt flag (x=3..0)

`pub fn tcif1(&self) -> TCIF1_R`[src]

Bit 11 - Stream x transfer complete interrupt flag (x = 3..0)

`pub fn htif1(&self) -> HTIF1_R`[src]

Bit 10 - Stream x half transfer interrupt flag (x=3..0)

`pub fn teif1(&self) -> TEIF1_R`[src]

Bit 9 - Stream x transfer error interrupt flag (x=3..0)

`pub fn dmeif1(&self) -> DMEIF1_R`[src]

Bit 8 - Stream x direct mode error interrupt flag (x=3..0)

`pub fn feif1(&self) -> FEIF1_R`[src]

Bit 6 - Stream x FIFO error interrupt flag (x=3..0)

`pub fn tcif0(&self) -> TCIF0_R`[src]

Bit 5 - Stream x transfer complete interrupt flag (x = 3..0)

`pub fn htif0(&self) -> HTIF0_R`[src]

Bit 4 - Stream x half transfer interrupt flag (x=3..0)

`pub fn teif0(&self) -> TEIF0_R`[src]

Bit 3 - Stream x transfer error interrupt flag (x=3..0)

`pub fn dmeif0(&self) -> DMEIF0_R`[src]

Bit 2 - Stream x direct mode error interrupt flag (x=3..0)

`pub fn feif0(&self) -> FEIF0_R`[src]

Bit 0 - Stream x FIFO error interrupt flag (x=3..0)

`impl R<bool, TCIF7_A>`[src]

Bit 24 - Stream x direct mode error interrupt flag (x=7..4)

`pub fn feif7(&self) -> FEIF7_R`[src]

Bit 22 - Stream x FIFO error interrupt flag (x=7..4)

`pub fn tcif6(&self) -> TCIF6_R`[src]

Bit 21 - Stream x transfer complete interrupt flag (x=7..4)

`pub fn htif6(&self) -> HTIF6_R`[src]

Bit 20 - Stream x half transfer interrupt flag (x=7..4)

`pub fn teif6(&self) -> TEIF6_R`[src]

Bit 19 - Stream x transfer error interrupt flag (x=7..4)

`pub fn dmeif6(&self) -> DMEIF6_R`[src]

Bit 18 - Stream x direct mode error interrupt flag (x=7..4)

`pub fn feif6(&self) -> FEIF6_R`[src]

Bit 16 - Stream x FIFO error interrupt flag (x=7..4)

`pub fn tcif5(&self) -> TCIF5_R`[src]

Bit 11 - Stream x transfer complete interrupt flag (x=7..4)

`pub fn htif5(&self) -> HTIF5_R`[src]

Bit 10 - Stream x half transfer interrupt flag (x=7..4)

`pub fn teif5(&self) -> TEIF5_R`[src]

Bit 9 - Stream x transfer error interrupt flag (x=7..4)

`pub fn dmeif5(&self) -> DMEIF5_R`[src]

Bit 8 - Stream x direct mode error interrupt flag (x=7..4)

`pub fn feif5(&self) -> FEIF5_R`[src]

Bit 6 - Stream x FIFO error interrupt flag (x=7..4)

`pub fn tcif4(&self) -> TCIF4_R`[src]

Bit 5 - Stream x transfer complete interrupt flag (x=7..4)

`pub fn htif4(&self) -> HTIF4_R`[src]

`pub fn pllon(&self) -> PLLON_R`[src]

Bit 24 - Main PLL (PLL) enable

`pub fn csson(&self) -> CSSON_R`[src]

Bit 19 - Clock security system enable

`pub fn hsebyp(&self) -> HSEBYP_R`[src]

Bit 18 - HSE clock bypass

`pub fn hserdy(&self) -> HSERDY_R`[src]

Bit 17 - HSE clock ready flag

`pub fn hseon(&self) -> HSEON_R`[src]

Bit 16 - HSE clock enable

`pub fn hsical(&self) -> HSICAL_R`[src]

Bits 8:15 - Internal high-speed clock calibration

`pub fn hsitrim(&self) -> HSITRIM_R`[src]

Bits 3:7 - Internal high-speed clock trimming

`pub fn hsirdy(&self) -> HSIRDY_R`[src]

Bit 1 - Internal high-speed clock ready flag

`pub fn hsion(&self) -> HSION_R`[src]

Bit 0 - Internal high-speed clock enable

`pub fn pllsairdy(&self) -> PLLSAIRDY_R`[src]

Bit 29 - PLLSAI clock ready flag

`pub fn pllsaion(&self) -> PLLSAION_R`[src]

Bit 28 - PLLSAI enable

`impl R<bool, PLLSRC_A>`[src]

`pub fn variant(&self) -> PLLSRC_A`[src]

Get enumerated values variant

`pub fn is_hsi(&self) -> bool`[src]

Checks if the value of the field is HSI

`pub fn is_hse(&self) -> bool`[src]

Checks if the value of the field is HSE

`impl R<u8, PLLP_A>`[src]

`pub fn variant(&self) -> PLLP_A`[src]

Get enumerated values variant

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div6(&self) -> bool`[src]

Checks if the value of the field is DIV6

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u32, Reg<u32, _PLLCFGR>>`[src]

`pub fn pllsrc(&self) -> PLLSRC_R`[src]

Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source

`pub fn pllr(&self) -> PLLR_R`[src]

Bits 28:30 - PLL division factor for DSI clock

`pub fn pllm(&self) -> PLLM_R`[src]

Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock

`pub fn plln(&self) -> PLLN_R`[src]

Bits 6:14 - Main PLL (PLL) multiplication factor for VCO

`pub fn pllp(&self) -> PLLP_R`[src]

Bits 16:17 - Main PLL (PLL) division factor for main system clock

`pub fn pllq(&self) -> PLLQ_R`[src]

Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks

`impl R<u8, MCO2_A>`[src]

`pub fn variant(&self) -> MCO2_A`[src]

Get enumerated values variant

`pub fn is_sysclk(&self) -> bool`[src]

Checks if the value of the field is SYSCLK

`pub fn is_plli2s(&self) -> bool`[src]

Checks if the value of the field is PLLI2S

`pub fn is_hse(&self) -> bool`[src]

Checks if the value of the field is HSE

`pub fn is_pll(&self) -> bool`[src]

Checks if the value of the field is PLL

`impl R<u8, MCO2PRE_A>`[src]

`pub fn variant(&self) -> Variant<u8, MCO2PRE_A>`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div3(&self) -> bool`[src]

Checks if the value of the field is DIV3

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div5(&self) -> bool`[src]

Checks if the value of the field is DIV5

`impl R<bool, I2SSRC_A>`[src]

`pub fn variant(&self) -> I2SSRC_A`[src]

Get enumerated values variant

`pub fn is_plli2s(&self) -> bool`[src]

Checks if the value of the field is PLLI2S

`pub fn is_ckin(&self) -> bool`[src]

Checks if the value of the field is CKIN

`impl R<u8, MCO1_A>`[src]

`pub fn variant(&self) -> MCO1_A`[src]

Get enumerated values variant

`pub fn is_hsi(&self) -> bool`[src]

Checks if the value of the field is HSI

`pub fn is_lse(&self) -> bool`[src]

Checks if the value of the field is LSE

`pub fn is_hse(&self) -> bool`[src]

Checks if the value of the field is HSE

`pub fn is_pll(&self) -> bool`[src]

Checks if the value of the field is PLL

`impl R<u8, PPRE2_A>`[src]

`pub fn variant(&self) -> Variant<u8, PPRE2_A>`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`impl R<u8, HPRE_A>`[src]

`pub fn variant(&self) -> Variant<u8, HPRE_A>`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`pub fn is_div64(&self) -> bool`[src]

Checks if the value of the field is DIV64

`pub fn is_div128(&self) -> bool`[src]

Checks if the value of the field is DIV128

`pub fn is_div256(&self) -> bool`[src]

Checks if the value of the field is DIV256

`pub fn is_div512(&self) -> bool`[src]

Checks if the value of the field is DIV512

`impl R<u8, SW_A>`[src]

`pub fn variant(&self) -> Variant<u8, SW_A>`[src]

Get enumerated values variant

`pub fn is_hsi(&self) -> bool`[src]

Checks if the value of the field is HSI

`pub fn is_hse(&self) -> bool`[src]

Checks if the value of the field is HSE

`pub fn is_pll(&self) -> bool`[src]

Checks if the value of the field is PLL

`impl R<u8, SWS_A>`[src]

`pub fn variant(&self) -> Variant<u8, SWS_A>`[src]

Get enumerated values variant

`pub fn is_hsi(&self) -> bool`[src]

Checks if the value of the field is HSI

`pub fn is_hse(&self) -> bool`[src]

Checks if the value of the field is HSE

`pub fn is_pll(&self) -> bool`[src]

Checks if the value of the field is PLL

`impl R<u32, Reg<u32, _CFGR>>`[src]

`pub fn mco2(&self) -> MCO2_R`[src]

Bits 30:31 - Microcontroller clock output 2

`pub fn mco2pre(&self) -> MCO2PRE_R`[src]

Bits 27:29 - MCO2 prescaler

`pub fn mco1pre(&self) -> MCO1PRE_R`[src]

Bits 24:26 - MCO1 prescaler

`pub fn i2ssrc(&self) -> I2SSRC_R`[src]

Bit 23 - I2S clock selection

`pub fn mco1(&self) -> MCO1_R`[src]

Bits 21:22 - Microcontroller clock output 1

`pub fn rtcpre(&self) -> RTCPRE_R`[src]

Bits 16:20 - HSE division factor for RTC clock

`pub fn ppre2(&self) -> PPRE2_R`[src]

Bits 13:15 - APB high-speed prescaler (APB2)

`pub fn ppre1(&self) -> PPRE1_R`[src]

Bits 10:12 - APB Low speed prescaler (APB1)

`pub fn hpre(&self) -> HPRE_R`[src]

Bits 4:7 - AHB prescaler

`pub fn sw(&self) -> SW_R`[src]

Bits 0:1 - System clock switch

`pub fn sws(&self) -> SWS_R`[src]

Bits 2:3 - System clock switch status

`impl R<bool, PLLSAIRDYIE_A>`[src]

`pub fn variant(&self) -> PLLSAIRDYIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, CSSF_A>`[src]

`pub fn variant(&self) -> CSSF_A`[src]

Get enumerated values variant

`pub fn is_not_interrupted(&self) -> bool`[src]

Checks if the value of the field is NOTINTERRUPTED

`pub fn is_interrupted(&self) -> bool`[src]

Checks if the value of the field is INTERRUPTED

`impl R<bool, PLLSAIRDYF_A>`[src]

`pub fn variant(&self) -> PLLSAIRDYF_A`[src]

Get enumerated values variant

`pub fn is_not_interrupted(&self) -> bool`[src]

Checks if the value of the field is NOTINTERRUPTED

`pub fn is_interrupted(&self) -> bool`[src]

Checks if the value of the field is INTERRUPTED

`impl R<u32, Reg<u32, _CIR>>`[src]

`pub fn pllsairdyie(&self) -> PLLSAIRDYIE_R`[src]

Bit 14 - PLLSAI Ready Interrupt Enable

`pub fn plli2srdyie(&self) -> PLLI2SRDYIE_R`[src]

Bit 13 - PLLI2S ready interrupt enable

`pub fn pllrdyie(&self) -> PLLRDYIE_R`[src]

Bit 12 - Main PLL (PLL) ready interrupt enable

`pub fn hserdyie(&self) -> HSERDYIE_R`[src]

Bit 11 - HSE ready interrupt enable

`pub fn hsirdyie(&self) -> HSIRDYIE_R`[src]

Bit 10 - HSI ready interrupt enable

`pub fn lserdyie(&self) -> LSERDYIE_R`[src]

Bit 9 - LSE ready interrupt enable

`pub fn lsirdyie(&self) -> LSIRDYIE_R`[src]

Bit 8 - LSI ready interrupt enable

`pub fn cssf(&self) -> CSSF_R`[src]

Bit 7 - Clock security system interrupt flag

`pub fn pllsairdyf(&self) -> PLLSAIRDYF_R`[src]

Bit 6 - PLLSAI ready interrupt flag

`pub fn plli2srdyf(&self) -> PLLI2SRDYF_R`[src]

Bit 5 - PLLI2S ready interrupt flag

`pub fn pllrdyf(&self) -> PLLRDYF_R`[src]

Bit 4 - Main PLL (PLL) ready interrupt flag

`pub fn hserdyf(&self) -> HSERDYF_R`[src]

Bit 3 - HSE ready interrupt flag

`pub fn hsirdyf(&self) -> HSIRDYF_R`[src]

Bit 2 - HSI ready interrupt flag

`pub fn lserdyf(&self) -> LSERDYF_R`[src]

Bit 1 - LSE ready interrupt flag

`pub fn lsirdyf(&self) -> LSIRDYF_R`[src]

Bit 0 - LSI ready interrupt flag

`impl R<bool, OTGHSRST_A>`[src]

`pub fn variant(&self) -> Variant<bool, OTGHSRST_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _AHB1RSTR>>`[src]

`pub fn otghsrst(&self) -> OTGHSRST_R`[src]

Bit 29 - USB OTG HS module reset

`pub fn ethmacrst(&self) -> ETHMACRST_R`[src]

Bit 25 - Ethernet MAC reset

`pub fn dma2drst(&self) -> DMA2DRST_R`[src]

Bit 23 - DMA2D reset

`pub fn dma2rst(&self) -> DMA2RST_R`[src]

Bit 22 - DMA2 reset

`pub fn dma1rst(&self) -> DMA1RST_R`[src]

Bit 21 - DMA2 reset

`pub fn crcrst(&self) -> CRCRST_R`[src]

Bit 12 - CRC reset

`pub fn gpiokrst(&self) -> GPIOKRST_R`[src]

Bit 10 - IO port K reset

`pub fn gpiojrst(&self) -> GPIOJRST_R`[src]

Bit 9 - IO port J reset

`pub fn gpioirst(&self) -> GPIOIRST_R`[src]

Bit 8 - IO port I reset

`pub fn gpiohrst(&self) -> GPIOHRST_R`[src]

Bit 7 - IO port H reset

`pub fn gpiogrst(&self) -> GPIOGRST_R`[src]

Bit 6 - IO port G reset

`pub fn gpiofrst(&self) -> GPIOFRST_R`[src]

Bit 5 - IO port F reset

`pub fn gpioerst(&self) -> GPIOERST_R`[src]

Bit 4 - IO port E reset

`pub fn gpiodrst(&self) -> GPIODRST_R`[src]

Bit 3 - IO port D reset

`pub fn gpiocrst(&self) -> GPIOCRST_R`[src]

Bit 2 - IO port C reset

`pub fn gpiobrst(&self) -> GPIOBRST_R`[src]

Bit 1 - IO port B reset

`pub fn gpioarst(&self) -> GPIOARST_R`[src]

Bit 0 - IO port A reset

`impl R<bool, OTGFSRST_A>`[src]

`pub fn variant(&self) -> Variant<bool, OTGFSRST_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _AHB2RSTR>>`[src]

`pub fn otgfsrst(&self) -> OTGFSRST_R`[src]

Bit 7 - USB OTG FS module reset

`pub fn rngrst(&self) -> RNGRST_R`[src]

Bit 6 - Random number generator module reset

`pub fn hsahrst(&self) -> HSAHRST_R`[src]

Bit 5 - Hash module reset

`pub fn cryprst(&self) -> CRYPRST_R`[src]

Bit 4 - Cryptographic module reset

`pub fn dcmirst(&self) -> DCMIRST_R`[src]

Bit 0 - Camera interface reset

`impl R<bool, FMCRST_A>`[src]

`pub fn variant(&self) -> Variant<bool, FMCRST_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _AHB3RSTR>>`[src]

`pub fn fmcrst(&self) -> FMCRST_R`[src]

Bit 0 - Flexible memory controller module reset

`pub fn qspirst(&self) -> QSPIRST_R`[src]

Bit 1 - Quad SPI memory controller reset

`impl R<bool, TIM2RST_A>`[src]

`pub fn variant(&self) -> Variant<bool, TIM2RST_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _APB1RSTR>>`[src]

`pub fn tim2rst(&self) -> TIM2RST_R`[src]

Bit 0 - TIM2 reset

`pub fn tim3rst(&self) -> TIM3RST_R`[src]

Bit 1 - TIM3 reset

`pub fn tim4rst(&self) -> TIM4RST_R`[src]

Bit 2 - TIM4 reset

`pub fn tim5rst(&self) -> TIM5RST_R`[src]

Bit 3 - TIM5 reset

`pub fn tim6rst(&self) -> TIM6RST_R`[src]

Bit 4 - TIM6 reset

`pub fn tim7rst(&self) -> TIM7RST_R`[src]

Bit 5 - TIM7 reset

`pub fn tim12rst(&self) -> TIM12RST_R`[src]

Bit 6 - TIM12 reset

`pub fn tim13rst(&self) -> TIM13RST_R`[src]

Bit 7 - TIM13 reset

`pub fn tim14rst(&self) -> TIM14RST_R`[src]

Bit 8 - TIM14 reset

`pub fn wwdgrst(&self) -> WWDGRST_R`[src]

Bit 11 - Window watchdog reset

`pub fn spi2rst(&self) -> SPI2RST_R`[src]

Bit 14 - SPI 2 reset

`pub fn spi3rst(&self) -> SPI3RST_R`[src]

Bit 15 - SPI 3 reset

`pub fn uart2rst(&self) -> UART2RST_R`[src]

Bit 17 - USART 2 reset

`pub fn uart3rst(&self) -> UART3RST_R`[src]

Bit 18 - USART 3 reset

`pub fn uart4rst(&self) -> UART4RST_R`[src]

Bit 19 - USART 4 reset

`pub fn uart5rst(&self) -> UART5RST_R`[src]

Bit 20 - USART 5 reset

`pub fn i2c1rst(&self) -> I2C1RST_R`[src]

Bit 21 - I2C 1 reset

`pub fn i2c2rst(&self) -> I2C2RST_R`[src]

Bit 22 - I2C 2 reset

`pub fn i2c3rst(&self) -> I2C3RST_R`[src]

Bit 23 - I2C3 reset

`pub fn can1rst(&self) -> CAN1RST_R`[src]

Bit 25 - CAN1 reset

`pub fn can2rst(&self) -> CAN2RST_R`[src]

Bit 26 - CAN2 reset

`pub fn pwrrst(&self) -> PWRRST_R`[src]

Bit 28 - Power interface reset

`pub fn dacrst(&self) -> DACRST_R`[src]

Bit 29 - DAC reset

`pub fn uart7rst(&self) -> UART7RST_R`[src]

Bit 30 - UART7 reset

`pub fn uart8rst(&self) -> UART8RST_R`[src]

Bit 31 - UART8 reset

`pub fn spdifrxrst(&self) -> SPDIFRXRST_R`[src]

Bit 16 - SPDIF-RX reset

`pub fn cecrst(&self) -> CECRST_R`[src]

Bit 27 - HDMI-CEC reset

`pub fn lptim1rst(&self) -> LPTIM1RST_R`[src]

Bit 9 - Low power timer 1 reset

`pub fn i2c4rst(&self) -> I2C4RST_R`[src]

Bit 24 - I2C 4 reset

`impl R<bool, TIM1RST_A>`[src]

`pub fn variant(&self) -> Variant<bool, TIM1RST_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _APB2RSTR>>`[src]

`pub fn tim1rst(&self) -> TIM1RST_R`[src]

Bit 0 - TIM1 reset

`pub fn tim8rst(&self) -> TIM8RST_R`[src]

Bit 1 - TIM8 reset

`pub fn usart1rst(&self) -> USART1RST_R`[src]

Bit 4 - USART1 reset

`pub fn usart6rst(&self) -> USART6RST_R`[src]

Bit 5 - USART6 reset

`pub fn adcrst(&self) -> ADCRST_R`[src]

Bit 8 - ADC interface reset (common to all ADCs)

`pub fn spi1rst(&self) -> SPI1RST_R`[src]

Bit 12 - SPI 1 reset

`pub fn spi4rst(&self) -> SPI4RST_R`[src]

Bit 13 - SPI4 reset

`pub fn syscfgrst(&self) -> SYSCFGRST_R`[src]

Bit 14 - System configuration controller reset

`pub fn tim9rst(&self) -> TIM9RST_R`[src]

Bit 16 - TIM9 reset

`pub fn tim10rst(&self) -> TIM10RST_R`[src]

Bit 17 - TIM10 reset

`pub fn tim11rst(&self) -> TIM11RST_R`[src]

Bit 18 - TIM11 reset

`pub fn spi5rst(&self) -> SPI5RST_R`[src]

Bit 20 - SPI5 reset

`pub fn spi6rst(&self) -> SPI6RST_R`[src]

Bit 21 - SPI6 reset

`pub fn sai1rst(&self) -> SAI1RST_R`[src]

Bit 22 - SAI1 reset

`pub fn ltdcrst(&self) -> LTDCRST_R`[src]

Bit 26 - LTDC reset

`pub fn sai2rst(&self) -> SAI2RST_R`[src]

Bit 23 - SAI2 reset

`pub fn sdmmc1rst(&self) -> SDMMC1RST_R`[src]

Bit 11 - SDMMC1 reset

`impl R<bool, OTGHSULPIEN_A>`[src]

`pub fn variant(&self) -> OTGHSULPIEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _AHB1ENR>>`[src]

`pub fn otghsulpien(&self) -> OTGHSULPIEN_R`[src]

Bit 30 - USB OTG HSULPI clock enable

`pub fn otghsen(&self) -> OTGHSEN_R`[src]

Bit 29 - USB OTG HS clock enable

`pub fn ethmacptpen(&self) -> ETHMACPTPEN_R`[src]

Bit 28 - Ethernet PTP clock enable

`pub fn ethmacrxen(&self) -> ETHMACRXEN_R`[src]

Bit 27 - Ethernet Reception clock enable

`pub fn ethmactxen(&self) -> ETHMACTXEN_R`[src]

Bit 26 - Ethernet Transmission clock enable

`pub fn ethmacen(&self) -> ETHMACEN_R`[src]

Bit 25 - Ethernet MAC clock enable

`pub fn dma2den(&self) -> DMA2DEN_R`[src]

Bit 23 - DMA2D clock enable

`pub fn dma2en(&self) -> DMA2EN_R`[src]

Bit 22 - DMA2 clock enable

`pub fn dma1en(&self) -> DMA1EN_R`[src]

Bit 21 - DMA1 clock enable

`pub fn ccmdataramen(&self) -> CCMDATARAMEN_R`[src]

Bit 20 - CCM data RAM clock enable

`pub fn bkpsramen(&self) -> BKPSRAMEN_R`[src]

Bit 18 - Backup SRAM interface clock enable

`pub fn crcen(&self) -> CRCEN_R`[src]

Bit 12 - CRC clock enable

`pub fn gpioken(&self) -> GPIOKEN_R`[src]

Bit 10 - IO port K clock enable

`pub fn gpiojen(&self) -> GPIOJEN_R`[src]

Bit 9 - IO port J clock enable

`pub fn gpioien(&self) -> GPIOIEN_R`[src]

Bit 8 - IO port I clock enable

`pub fn gpiohen(&self) -> GPIOHEN_R`[src]

Bit 7 - IO port H clock enable

`pub fn gpiogen(&self) -> GPIOGEN_R`[src]

Bit 6 - IO port G clock enable

`pub fn gpiofen(&self) -> GPIOFEN_R`[src]

Bit 5 - IO port F clock enable

`pub fn gpioeen(&self) -> GPIOEEN_R`[src]

Bit 4 - IO port E clock enable

`pub fn gpioden(&self) -> GPIODEN_R`[src]

Bit 3 - IO port D clock enable

`pub fn gpiocen(&self) -> GPIOCEN_R`[src]

Bit 2 - IO port C clock enable

`pub fn gpioben(&self) -> GPIOBEN_R`[src]

Bit 1 - IO port B clock enable

`pub fn gpioaen(&self) -> GPIOAEN_R`[src]

Bit 0 - IO port A clock enable

`impl R<bool, OTGFSEN_A>`[src]

`pub fn variant(&self) -> OTGFSEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _AHB2ENR>>`[src]

`pub fn otgfsen(&self) -> OTGFSEN_R`[src]

Bit 7 - USB OTG FS clock enable

`pub fn rngen(&self) -> RNGEN_R`[src]

Bit 6 - Random number generator clock enable

`pub fn hashen(&self) -> HASHEN_R`[src]

Bit 5 - Hash modules clock enable

`pub fn crypen(&self) -> CRYPEN_R`[src]

Bit 4 - Cryptographic modules clock enable

`pub fn dcmien(&self) -> DCMIEN_R`[src]

Bit 0 - Camera interface enable

`impl R<bool, FMCEN_A>`[src]

`pub fn variant(&self) -> FMCEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _AHB3ENR>>`[src]

`pub fn fmcen(&self) -> FMCEN_R`[src]

Bit 0 - Flexible memory controller module clock enable

`pub fn qspien(&self) -> QSPIEN_R`[src]

Bit 1 - Quad SPI memory controller clock enable

`impl R<bool, TIM2EN_A>`[src]

`pub fn variant(&self) -> TIM2EN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _APB1ENR>>`[src]

`pub fn tim2en(&self) -> TIM2EN_R`[src]

Bit 0 - TIM2 clock enable

`pub fn tim3en(&self) -> TIM3EN_R`[src]

Bit 1 - TIM3 clock enable

`pub fn tim4en(&self) -> TIM4EN_R`[src]

Bit 2 - TIM4 clock enable

`pub fn tim5en(&self) -> TIM5EN_R`[src]

Bit 3 - TIM5 clock enable

`pub fn tim6en(&self) -> TIM6EN_R`[src]

Bit 4 - TIM6 clock enable

`pub fn tim7en(&self) -> TIM7EN_R`[src]

Bit 5 - TIM7 clock enable

`pub fn tim12en(&self) -> TIM12EN_R`[src]

Bit 6 - TIM12 clock enable

`pub fn tim13en(&self) -> TIM13EN_R`[src]

Bit 7 - TIM13 clock enable

`pub fn tim14en(&self) -> TIM14EN_R`[src]

Bit 8 - TIM14 clock enable

`pub fn wwdgen(&self) -> WWDGEN_R`[src]

Bit 11 - Window watchdog clock enable

`pub fn spi2en(&self) -> SPI2EN_R`[src]

Bit 14 - SPI2 clock enable

`pub fn spi3en(&self) -> SPI3EN_R`[src]

Bit 15 - SPI3 clock enable

`pub fn usart2en(&self) -> USART2EN_R`[src]

Bit 17 - USART 2 clock enable

`pub fn usart3en(&self) -> USART3EN_R`[src]

Bit 18 - USART3 clock enable

`pub fn uart4en(&self) -> UART4EN_R`[src]

Bit 19 - UART4 clock enable

`pub fn uart5en(&self) -> UART5EN_R`[src]

Bit 20 - UART5 clock enable

`pub fn i2c1en(&self) -> I2C1EN_R`[src]

Bit 21 - I2C1 clock enable

`pub fn i2c2en(&self) -> I2C2EN_R`[src]

Bit 22 - I2C2 clock enable

`pub fn i2c3en(&self) -> I2C3EN_R`[src]

Bit 23 - I2C3 clock enable

`pub fn can1en(&self) -> CAN1EN_R`[src]

Bit 25 - CAN 1 clock enable

`pub fn can2en(&self) -> CAN2EN_R`[src]

Bit 26 - CAN 2 clock enable

`pub fn pwren(&self) -> PWREN_R`[src]

Bit 28 - Power interface clock enable

`pub fn dacen(&self) -> DACEN_R`[src]

Bit 29 - DAC interface clock enable

`pub fn uart7en(&self) -> UART7EN_R`[src]

Bit 30 - UART7 clock enable

`pub fn uart8en(&self) -> UART8EN_R`[src]

Bit 31 - UART8 clock enable

`pub fn spdifrxen(&self) -> SPDIFRXEN_R`[src]

Bit 16 - SPDIF-RX clock enable

`pub fn cecen(&self) -> CECEN_R`[src]

Bit 27 - HDMI-CEN clock enable

`pub fn lptmi1en(&self) -> LPTMI1EN_R`[src]

Bit 9 - Low power timer 1 clock enable

`pub fn i2c4en(&self) -> I2C4EN_R`[src]

Bit 24 - I2C4 clock enable

`impl R<bool, TIM1EN_A>`[src]

`pub fn variant(&self) -> TIM1EN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _APB2ENR>>`[src]

`pub fn tim1en(&self) -> TIM1EN_R`[src]

Bit 0 - TIM1 clock enable

`pub fn tim8en(&self) -> TIM8EN_R`[src]

Bit 1 - TIM8 clock enable

`pub fn usart1en(&self) -> USART1EN_R`[src]

Bit 4 - USART1 clock enable

`pub fn usart6en(&self) -> USART6EN_R`[src]

Bit 5 - USART6 clock enable

`pub fn adc1en(&self) -> ADC1EN_R`[src]

Bit 8 - ADC1 clock enable

`pub fn adc2en(&self) -> ADC2EN_R`[src]

Bit 9 - ADC2 clock enable

`pub fn adc3en(&self) -> ADC3EN_R`[src]

Bit 10 - ADC3 clock enable

`pub fn spi1en(&self) -> SPI1EN_R`[src]

Bit 12 - SPI1 clock enable

`pub fn spi4en(&self) -> SPI4EN_R`[src]

Bit 13 - SPI4 clock enable

`pub fn syscfgen(&self) -> SYSCFGEN_R`[src]

Bit 14 - System configuration controller clock enable

`pub fn tim9en(&self) -> TIM9EN_R`[src]

Bit 16 - TIM9 clock enable

`pub fn tim10en(&self) -> TIM10EN_R`[src]

Bit 17 - TIM10 clock enable

`pub fn tim11en(&self) -> TIM11EN_R`[src]

Bit 18 - TIM11 clock enable

`pub fn spi5en(&self) -> SPI5EN_R`[src]

Bit 20 - SPI5 clock enable

`pub fn spi6en(&self) -> SPI6EN_R`[src]

Bit 21 - SPI6 clock enable

`pub fn sai1en(&self) -> SAI1EN_R`[src]

Bit 22 - SAI1 clock enable

`pub fn ltdcen(&self) -> LTDCEN_R`[src]

Bit 26 - LTDC clock enable

`pub fn sai2en(&self) -> SAI2EN_R`[src]

Bit 23 - SAI2 clock enable

`pub fn sdmmc1en(&self) -> SDMMC1EN_R`[src]

Bit 11 - SDMMC1 clock enable

`impl R<bool, GPIOALPEN_A>`[src]

`pub fn variant(&self) -> GPIOALPEN_A`[src]

Get enumerated values variant

`pub fn is_disabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is DISABLEDINSLEEP

`pub fn is_enabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is ENABLEDINSLEEP

`impl R<u32, Reg<u32, _AHB1LPENR>>`[src]

`pub fn gpioalpen(&self) -> GPIOALPEN_R`[src]

Bit 0 - IO port A clock enable during sleep mode

`pub fn gpioblpen(&self) -> GPIOBLPEN_R`[src]

Bit 1 - IO port B clock enable during Sleep mode

`pub fn gpioclpen(&self) -> GPIOCLPEN_R`[src]

Bit 2 - IO port C clock enable during Sleep mode

`pub fn gpiodlpen(&self) -> GPIODLPEN_R`[src]

Bit 3 - IO port D clock enable during Sleep mode

`pub fn gpioelpen(&self) -> GPIOELPEN_R`[src]

Bit 4 - IO port E clock enable during Sleep mode

`pub fn gpioflpen(&self) -> GPIOFLPEN_R`[src]

Bit 5 - IO port F clock enable during Sleep mode

`pub fn gpioglpen(&self) -> GPIOGLPEN_R`[src]

Bit 6 - IO port G clock enable during Sleep mode

`pub fn gpiohlpen(&self) -> GPIOHLPEN_R`[src]

Bit 7 - IO port H clock enable during Sleep mode

`pub fn gpioilpen(&self) -> GPIOILPEN_R`[src]

Bit 8 - IO port I clock enable during Sleep mode

`pub fn gpiojlpen(&self) -> GPIOJLPEN_R`[src]

Bit 9 - IO port J clock enable during Sleep mode

`pub fn gpioklpen(&self) -> GPIOKLPEN_R`[src]

Bit 10 - IO port K clock enable during Sleep mode

`pub fn crclpen(&self) -> CRCLPEN_R`[src]

Bit 12 - CRC clock enable during Sleep mode

`pub fn flitflpen(&self) -> FLITFLPEN_R`[src]

Bit 15 - Flash interface clock enable during Sleep mode

`pub fn sram1lpen(&self) -> SRAM1LPEN_R`[src]

Bit 16 - SRAM 1interface clock enable during Sleep mode

`pub fn sram2lpen(&self) -> SRAM2LPEN_R`[src]

Bit 17 - SRAM 2 interface clock enable during Sleep mode

`pub fn bkpsramlpen(&self) -> BKPSRAMLPEN_R`[src]

Bit 18 - Backup SRAM interface clock enable during Sleep mode

`pub fn sram3lpen(&self) -> SRAM3LPEN_R`[src]

Bit 19 - SRAM 3 interface clock enable during Sleep mode

`pub fn dma1lpen(&self) -> DMA1LPEN_R`[src]

Bit 21 - DMA1 clock enable during Sleep mode

`pub fn dma2lpen(&self) -> DMA2LPEN_R`[src]

Bit 22 - DMA2 clock enable during Sleep mode

`pub fn dma2dlpen(&self) -> DMA2DLPEN_R`[src]

Bit 23 - DMA2D clock enable during Sleep mode

`pub fn ethmaclpen(&self) -> ETHMACLPEN_R`[src]

Bit 25 - Ethernet MAC clock enable during Sleep mode

`pub fn ethmactxlpen(&self) -> ETHMACTXLPEN_R`[src]

Bit 26 - Ethernet transmission clock enable during Sleep mode

`pub fn ethmacrxlpen(&self) -> ETHMACRXLPEN_R`[src]

Bit 27 - Ethernet reception clock enable during Sleep mode

`pub fn ethmacptplpen(&self) -> ETHMACPTPLPEN_R`[src]

Bit 28 - Ethernet PTP clock enable during Sleep mode

`pub fn otghslpen(&self) -> OTGHSLPEN_R`[src]

Bit 29 - USB OTG HS clock enable during Sleep mode

`pub fn otghsulpilpen(&self) -> OTGHSULPILPEN_R`[src]

Bit 30 - USB OTG HS ULPI clock enable during Sleep mode

`impl R<bool, OTGFSLPEN_A>`[src]

`pub fn variant(&self) -> OTGFSLPEN_A`[src]

Get enumerated values variant

`pub fn is_disabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is DISABLEDINSLEEP

`pub fn is_enabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is ENABLEDINSLEEP

`impl R<u32, Reg<u32, _AHB2LPENR>>`[src]

`pub fn otgfslpen(&self) -> OTGFSLPEN_R`[src]

Bit 7 - USB OTG FS clock enable during Sleep mode

`pub fn rnglpen(&self) -> RNGLPEN_R`[src]

Bit 6 - Random number generator clock enable during Sleep mode

`pub fn hashlpen(&self) -> HASHLPEN_R`[src]

Bit 5 - Hash modules clock enable during Sleep mode

`pub fn cryplpen(&self) -> CRYPLPEN_R`[src]

Bit 4 - Cryptography modules clock enable during Sleep mode

`pub fn dcmilpen(&self) -> DCMILPEN_R`[src]

Bit 0 - Camera interface enable during Sleep mode

`impl R<bool, FMCLPEN_A>`[src]

`pub fn variant(&self) -> FMCLPEN_A`[src]

Get enumerated values variant

`pub fn is_disabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is DISABLEDINSLEEP

`pub fn is_enabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is ENABLEDINSLEEP

`impl R<u32, Reg<u32, _AHB3LPENR>>`[src]

`pub fn fmclpen(&self) -> FMCLPEN_R`[src]

Bit 0 - Flexible memory controller module clock enable during Sleep mode

`pub fn qspilpen(&self) -> QSPILPEN_R`[src]

Bit 1 - Quand SPI memory controller clock enable during Sleep mode

`impl R<bool, TIM2LPEN_A>`[src]

`pub fn variant(&self) -> TIM2LPEN_A`[src]

Get enumerated values variant

`pub fn is_disabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is DISABLEDINSLEEP

`pub fn is_enabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is ENABLEDINSLEEP

`impl R<u32, Reg<u32, _APB1LPENR>>`[src]

`pub fn tim2lpen(&self) -> TIM2LPEN_R`[src]

Bit 0 - TIM2 clock enable during Sleep mode

`pub fn tim3lpen(&self) -> TIM3LPEN_R`[src]

Bit 1 - TIM3 clock enable during Sleep mode

`pub fn tim4lpen(&self) -> TIM4LPEN_R`[src]

Bit 2 - TIM4 clock enable during Sleep mode

`pub fn tim5lpen(&self) -> TIM5LPEN_R`[src]

Bit 3 - TIM5 clock enable during Sleep mode

`pub fn tim6lpen(&self) -> TIM6LPEN_R`[src]

Bit 4 - TIM6 clock enable during Sleep mode

`pub fn tim7lpen(&self) -> TIM7LPEN_R`[src]

Bit 5 - TIM7 clock enable during Sleep mode

`pub fn tim12lpen(&self) -> TIM12LPEN_R`[src]

Bit 6 - TIM12 clock enable during Sleep mode

`pub fn tim13lpen(&self) -> TIM13LPEN_R`[src]

Bit 7 - TIM13 clock enable during Sleep mode

`pub fn tim14lpen(&self) -> TIM14LPEN_R`[src]

Bit 8 - TIM14 clock enable during Sleep mode

`pub fn wwdglpen(&self) -> WWDGLPEN_R`[src]

Bit 11 - Window watchdog clock enable during Sleep mode

`pub fn spi2lpen(&self) -> SPI2LPEN_R`[src]

Bit 14 - SPI2 clock enable during Sleep mode

`pub fn spi3lpen(&self) -> SPI3LPEN_R`[src]

Bit 15 - SPI3 clock enable during Sleep mode

`pub fn usart2lpen(&self) -> USART2LPEN_R`[src]

Bit 17 - USART2 clock enable during Sleep mode

`pub fn usart3lpen(&self) -> USART3LPEN_R`[src]

Bit 18 - USART3 clock enable during Sleep mode

`pub fn uart4lpen(&self) -> UART4LPEN_R`[src]

Bit 19 - UART4 clock enable during Sleep mode

`pub fn uart5lpen(&self) -> UART5LPEN_R`[src]

Bit 20 - UART5 clock enable during Sleep mode

`pub fn i2c1lpen(&self) -> I2C1LPEN_R`[src]

Bit 21 - I2C1 clock enable during Sleep mode

`pub fn i2c2lpen(&self) -> I2C2LPEN_R`[src]

Bit 22 - I2C2 clock enable during Sleep mode

`pub fn i2c3lpen(&self) -> I2C3LPEN_R`[src]

Bit 23 - I2C3 clock enable during Sleep mode

`pub fn can1lpen(&self) -> CAN1LPEN_R`[src]

Bit 25 - CAN 1 clock enable during Sleep mode

`pub fn can2lpen(&self) -> CAN2LPEN_R`[src]

Bit 26 - CAN 2 clock enable during Sleep mode

`pub fn pwrlpen(&self) -> PWRLPEN_R`[src]

Bit 28 - Power interface clock enable during Sleep mode

`pub fn daclpen(&self) -> DACLPEN_R`[src]

Bit 29 - DAC interface clock enable during Sleep mode

`pub fn uart7lpen(&self) -> UART7LPEN_R`[src]

Bit 30 - UART7 clock enable during Sleep mode

`pub fn uart8lpen(&self) -> UART8LPEN_R`[src]

Bit 31 - UART8 clock enable during Sleep mode

`pub fn spdifrxlpen(&self) -> SPDIFRXLPEN_R`[src]

Bit 16 - SPDIF-RX clock enable during sleep mode

`pub fn ceclpen(&self) -> CECLPEN_R`[src]

Bit 27 - HDMI-CEN clock enable during Sleep mode

`pub fn lptim1lpen(&self) -> LPTIM1LPEN_R`[src]

Bit 9 - low power timer 1 clock enable during Sleep mode

`pub fn i2c4lpen(&self) -> I2C4LPEN_R`[src]

Bit 24 - I2C4 clock enable during Sleep mode

`impl R<bool, TIM1LPEN_A>`[src]

`pub fn variant(&self) -> TIM1LPEN_A`[src]

Get enumerated values variant

`pub fn is_disabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is DISABLEDINSLEEP

`pub fn is_enabled_in_sleep(&self) -> bool`[src]

Checks if the value of the field is ENABLEDINSLEEP

`impl R<u32, Reg<u32, _APB2LPENR>>`[src]

`pub fn tim1lpen(&self) -> TIM1LPEN_R`[src]

Bit 0 - TIM1 clock enable during Sleep mode

`pub fn tim8lpen(&self) -> TIM8LPEN_R`[src]

Bit 1 - TIM8 clock enable during Sleep mode

`pub fn usart1lpen(&self) -> USART1LPEN_R`[src]

Bit 4 - USART1 clock enable during Sleep mode

`pub fn usart6lpen(&self) -> USART6LPEN_R`[src]

Bit 5 - USART6 clock enable during Sleep mode

`pub fn adc1lpen(&self) -> ADC1LPEN_R`[src]

Bit 8 - ADC1 clock enable during Sleep mode

`pub fn adc2lpen(&self) -> ADC2LPEN_R`[src]

Bit 9 - ADC2 clock enable during Sleep mode

`pub fn adc3lpen(&self) -> ADC3LPEN_R`[src]

Bit 10 - ADC 3 clock enable during Sleep mode

`pub fn spi1lpen(&self) -> SPI1LPEN_R`[src]

Bit 12 - SPI 1 clock enable during Sleep mode

`pub fn spi4lpen(&self) -> SPI4LPEN_R`[src]

Bit 13 - SPI 4 clock enable during Sleep mode

`pub fn syscfglpen(&self) -> SYSCFGLPEN_R`[src]

Bit 14 - System configuration controller clock enable during Sleep mode

`pub fn tim9lpen(&self) -> TIM9LPEN_R`[src]

Bit 16 - TIM9 clock enable during sleep mode

`pub fn tim10lpen(&self) -> TIM10LPEN_R`[src]

Bit 17 - TIM10 clock enable during Sleep mode

`pub fn tim11lpen(&self) -> TIM11LPEN_R`[src]

Bit 18 - TIM11 clock enable during Sleep mode

`pub fn spi5lpen(&self) -> SPI5LPEN_R`[src]

Bit 20 - SPI 5 clock enable during Sleep mode

`pub fn spi6lpen(&self) -> SPI6LPEN_R`[src]

Bit 21 - SPI 6 clock enable during Sleep mode

`pub fn sai1lpen(&self) -> SAI1LPEN_R`[src]

Bit 15 - RTC clock enable

`pub fn lsebyp(&self) -> LSEBYP_R`[src]

Bit 2 - External low-speed oscillator bypass

`pub fn lserdy(&self) -> LSERDY_R`[src]

Bit 1 - External low-speed oscillator ready

`pub fn lseon(&self) -> LSEON_R`[src]

Bit 0 - External low-speed oscillator enable

`pub fn lsedrv(&self) -> LSEDRV_R`[src]

Bits 3:4 - LSE oscillator drive capability

`pub fn rtcsel(&self) -> RTCSEL_R`[src]

Bits 8:9 - RTC clock source selection

`impl R<bool, LPWRRSTF_A>`[src]

`pub fn variant(&self) -> LPWRRSTF_A`[src]

`pub fn is_ready(&self) -> bool`[src]

Checks if the value of the field is READY

`impl R<bool, LSION_A>`[src]

`pub fn variant(&self) -> LSION_A`[src]

Get enumerated values variant

`pub fn is_off(&self) -> bool`[src]

Checks if the value of the field is OFF

`pub fn is_on(&self) -> bool`[src]

Checks if the value of the field is ON

`impl R<u32, Reg<u32, _CSR>>`[src]

`pub fn lpwrrstf(&self) -> LPWRRSTF_R`[src]

Bit 31 - Low-power reset flag

`pub fn wwdgrstf(&self) -> WWDGRSTF_R`[src]

Bit 30 - Window watchdog reset flag

`pub fn wdgrstf(&self) -> WDGRSTF_R`[src]

Bit 29 - Independent watchdog reset flag

`pub fn sftrstf(&self) -> SFTRSTF_R`[src]

Bit 28 - Software reset flag

`pub fn porrstf(&self) -> PORRSTF_R`[src]

Bit 27 - POR/PDR reset flag

`pub fn padrstf(&self) -> PADRSTF_R`[src]

Bit 26 - PIN reset flag

`pub fn borrstf(&self) -> BORRSTF_R`[src]

Bit 25 - BOR reset flag

`pub fn rmvf(&self) -> RMVF_R`[src]

Bit 24 - Remove reset flag

`pub fn lsirdy(&self) -> LSIRDY_R`[src]

Bit 1 - Internal low-speed oscillator ready

`pub fn lsion(&self) -> LSION_R`[src]

Bit 0 - Internal low-speed oscillator enable

`impl R<bool, SSCGEN_A>`[src]

`pub fn variant(&self) -> SSCGEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, SPREADSEL_A>`[src]

`pub fn variant(&self) -> SPREADSEL_A`[src]

Get enumerated values variant

`pub fn is_center(&self) -> bool`[src]

Checks if the value of the field is CENTER

`pub fn is_down(&self) -> bool`[src]

Checks if the value of the field is DOWN

`impl R<u32, Reg<u32, _SSCGR>>`[src]

`pub fn sscgen(&self) -> SSCGEN_R`[src]

Bit 31 - Spread spectrum modulation enable

`pub fn spreadsel(&self) -> SPREADSEL_R`[src]

Bit 30 - Spread Select

`pub fn incstep(&self) -> INCSTEP_R`[src]

Bits 13:27 - Incrementation step

`pub fn modper(&self) -> MODPER_R`[src]

Bits 0:12 - Modulation period

`impl R<u8, PLLI2SP_A>`[src]

`pub fn variant(&self) -> PLLI2SP_A`[src]

Get enumerated values variant

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div6(&self) -> bool`[src]

Checks if the value of the field is DIV6

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u32, Reg<u32, _PLLI2SCFGR>>`[src]

`pub fn plli2sr(&self) -> PLLI2SR_R`[src]

Bits 28:30 - PLLI2S division factor for I2S clocks

`pub fn plli2sq(&self) -> PLLI2SQ_R`[src]

Bits 24:27 - PLLI2S division factor for SAI1 clock

`pub fn plli2sn(&self) -> PLLI2SN_R`[src]

Bits 6:14 - PLLI2S multiplication factor for VCO

`pub fn plli2sp(&self) -> PLLI2SP_R`[src]

Bits 16:17 - PLLI2S division factor for SPDIFRX clock

`impl R<u8, PLLSAIP_A>`[src]

`pub fn variant(&self) -> PLLSAIP_A`[src]

Get enumerated values variant

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div6(&self) -> bool`[src]

Checks if the value of the field is DIV6

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u32, Reg<u32, _PLLSAICFGR>>`[src]

`pub fn pllsain(&self) -> PLLSAIN_R`[src]

Bits 6:14 - PLLSAI division factor for VCO

`pub fn pllsaip(&self) -> PLLSAIP_R`[src]

Bits 16:17 - PLLSAI division factor for 48MHz clock

`pub fn pllsaiq(&self) -> PLLSAIQ_R`[src]

Bits 24:27 - PLLSAI division factor for SAI clock

`pub fn pllsair(&self) -> PLLSAIR_R`[src]

Bits 28:30 - PLLSAI division factor for LCD clock

`impl R<u8, PLLI2SDIVQ_A>`[src]

`pub fn variant(&self) -> PLLI2SDIVQ_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div3(&self) -> bool`[src]

Checks if the value of the field is DIV3

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div5(&self) -> bool`[src]

Checks if the value of the field is DIV5

`pub fn is_div6(&self) -> bool`[src]

Checks if the value of the field is DIV6

`pub fn is_div7(&self) -> bool`[src]

Checks if the value of the field is DIV7

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div9(&self) -> bool`[src]

Checks if the value of the field is DIV9

`pub fn is_div10(&self) -> bool`[src]

Checks if the value of the field is DIV10

`pub fn is_div11(&self) -> bool`[src]

Checks if the value of the field is DIV11

`pub fn is_div12(&self) -> bool`[src]

Checks if the value of the field is DIV12

`pub fn is_div13(&self) -> bool`[src]

Checks if the value of the field is DIV13

`pub fn is_div14(&self) -> bool`[src]

Checks if the value of the field is DIV14

`pub fn is_div15(&self) -> bool`[src]

Checks if the value of the field is DIV15

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`pub fn is_div17(&self) -> bool`[src]

Checks if the value of the field is DIV17

`pub fn is_div18(&self) -> bool`[src]

Checks if the value of the field is DIV18

`pub fn is_div19(&self) -> bool`[src]

Checks if the value of the field is DIV19

`pub fn is_div20(&self) -> bool`[src]

Checks if the value of the field is DIV20

`pub fn is_div21(&self) -> bool`[src]

Checks if the value of the field is DIV21

`pub fn is_div22(&self) -> bool`[src]

Checks if the value of the field is DIV22

`pub fn is_div23(&self) -> bool`[src]

Checks if the value of the field is DIV23

`pub fn is_div24(&self) -> bool`[src]

Checks if the value of the field is DIV24

`pub fn is_div25(&self) -> bool`[src]

Checks if the value of the field is DIV25

`pub fn is_div26(&self) -> bool`[src]

Checks if the value of the field is DIV26

`pub fn is_div27(&self) -> bool`[src]

Checks if the value of the field is DIV27

`pub fn is_div28(&self) -> bool`[src]

Checks if the value of the field is DIV28

`pub fn is_div29(&self) -> bool`[src]

Checks if the value of the field is DIV29

`pub fn is_div30(&self) -> bool`[src]

Checks if the value of the field is DIV30

`pub fn is_div31(&self) -> bool`[src]

Checks if the value of the field is DIV31

`pub fn is_div32(&self) -> bool`[src]

Checks if the value of the field is DIV32

`impl R<u8, PLLSAIDIVQ_A>`[src]

`pub fn variant(&self) -> PLLSAIDIVQ_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div3(&self) -> bool`[src]

Checks if the value of the field is DIV3

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div5(&self) -> bool`[src]

Checks if the value of the field is DIV5

`pub fn is_div6(&self) -> bool`[src]

Checks if the value of the field is DIV6

`pub fn is_div7(&self) -> bool`[src]

Checks if the value of the field is DIV7

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div9(&self) -> bool`[src]

Checks if the value of the field is DIV9

`pub fn is_div10(&self) -> bool`[src]

Checks if the value of the field is DIV10

`pub fn is_div11(&self) -> bool`[src]

Checks if the value of the field is DIV11

`pub fn is_div12(&self) -> bool`[src]

Checks if the value of the field is DIV12

`pub fn is_div13(&self) -> bool`[src]

Checks if the value of the field is DIV13

`pub fn is_div14(&self) -> bool`[src]

Checks if the value of the field is DIV14

`pub fn is_div15(&self) -> bool`[src]

Checks if the value of the field is DIV15

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`pub fn is_div17(&self) -> bool`[src]

Checks if the value of the field is DIV17

`pub fn is_div18(&self) -> bool`[src]

Checks if the value of the field is DIV18

`pub fn is_div19(&self) -> bool`[src]

Checks if the value of the field is DIV19

`pub fn is_div20(&self) -> bool`[src]

Checks if the value of the field is DIV20

`pub fn is_div21(&self) -> bool`[src]

Checks if the value of the field is DIV21

`pub fn is_div22(&self) -> bool`[src]

Checks if the value of the field is DIV22

`pub fn is_div23(&self) -> bool`[src]

Checks if the value of the field is DIV23

`pub fn is_div24(&self) -> bool`[src]

Checks if the value of the field is DIV24

`pub fn is_div25(&self) -> bool`[src]

Checks if the value of the field is DIV25

`pub fn is_div26(&self) -> bool`[src]

Checks if the value of the field is DIV26

`pub fn is_div27(&self) -> bool`[src]

Checks if the value of the field is DIV27

`pub fn is_div28(&self) -> bool`[src]

Checks if the value of the field is DIV28

`pub fn is_div29(&self) -> bool`[src]

Checks if the value of the field is DIV29

`pub fn is_div30(&self) -> bool`[src]

Checks if the value of the field is DIV30

`pub fn is_div31(&self) -> bool`[src]

Checks if the value of the field is DIV31

`pub fn is_div32(&self) -> bool`[src]

Checks if the value of the field is DIV32

`impl R<u8, PLLSAIDIVR_A>`[src]

`pub fn variant(&self) -> PLLSAIDIVR_A`[src]

Get enumerated values variant

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`impl R<u8, SAI1SEL_A>`[src]

`pub fn variant(&self) -> SAI1SEL_A`[src]

Get enumerated values variant

`pub fn is_pllsai(&self) -> bool`[src]

Checks if the value of the field is PLLSAI

`pub fn is_plli2s(&self) -> bool`[src]

Checks if the value of the field is PLLI2S

`pub fn is_afif(&self) -> bool`[src]

Checks if the value of the field is AFIF

`pub fn is_hsi_hse(&self) -> bool`[src]

Checks if the value of the field is HSI_HSE

`impl R<u8, SAI2SEL_A>`[src]

`pub fn variant(&self) -> SAI2SEL_A`[src]

Get enumerated values variant

`pub fn is_pllsai(&self) -> bool`[src]

Checks if the value of the field is PLLSAI

`pub fn is_plli2s(&self) -> bool`[src]

Checks if the value of the field is PLLI2S

`pub fn is_afif(&self) -> bool`[src]

Checks if the value of the field is AFIF

`pub fn is_hsi_hse(&self) -> bool`[src]

Checks if the value of the field is HSI_HSE

`impl R<bool, TIMPRE_A>`[src]

`pub fn variant(&self) -> TIMPRE_A`[src]

Get enumerated values variant

`pub fn is_mul2(&self) -> bool`[src]

Checks if the value of the field is MUL2

`pub fn is_mul4(&self) -> bool`[src]

Checks if the value of the field is MUL4

`impl R<bool, DFSDM1SEL_A>`[src]

`pub fn variant(&self) -> DFSDM1SEL_A`[src]

Get enumerated values variant

`pub fn is_apb2(&self) -> bool`[src]

Checks if the value of the field is APB2

`pub fn is_sysclk(&self) -> bool`[src]

Checks if the value of the field is SYSCLK

`impl R<bool, ADFSDM1SEL_A>`[src]

`pub fn variant(&self) -> ADFSDM1SEL_A`[src]

Get enumerated values variant

`pub fn is_sai1(&self) -> bool`[src]

Checks if the value of the field is SAI1

`pub fn is_sai2(&self) -> bool`[src]

Checks if the value of the field is SAI2

`impl R<u32, Reg<u32, _DCKCFGR1>>`[src]

`pub fn plli2sdivq(&self) -> PLLI2SDIVQ_R`[src]

Bits 0:4 - PLLI2S division factor for SAI1 clock

`pub fn pllsaidivq(&self) -> PLLSAIDIVQ_R`[src]

Bits 8:12 - PLLSAI division factor for SAI1 clock

`pub fn pllsaidivr(&self) -> PLLSAIDIVR_R`[src]

Bits 16:17 - division factor for LCD_CLK

`pub fn sai1sel(&self) -> SAI1SEL_R`[src]

Bits 20:21 - SAI1 clock source selection

`pub fn sai2sel(&self) -> SAI2SEL_R`[src]

Bits 22:23 - SAI2 clock source selection

`pub fn timpre(&self) -> TIMPRE_R`[src]

Bit 24 - Timers clocks prescalers selection

`pub fn dfsdm1sel(&self) -> DFSDM1SEL_R`[src]

Bit 25 - DFSDM1 clock source selection

`pub fn adfsdm1sel(&self) -> ADFSDM1SEL_R`[src]

Bit 26 - DFSDM1 AUDIO clock source selection

`impl R<u8, USART1SEL_A>`[src]

`pub fn variant(&self) -> USART1SEL_A`[src]

Get enumerated values variant

`pub fn is_apb2(&self) -> bool`[src]

Checks if the value of the field is APB2

`pub fn is_sysclk(&self) -> bool`[src]

Checks if the value of the field is SYSCLK

`pub fn is_hsi(&self) -> bool`[src]

Checks if the value of the field is HSI

`pub fn is_lse(&self) -> bool`[src]

Checks if the value of the field is LSE

`impl R<u8, USART2SEL_A>`[src]

`pub fn variant(&self) -> USART2SEL_A`[src]

`pub fn is_lse(&self) -> bool`[src]

Checks if the value of the field is LSE

`impl R<bool, CECSEL_A>`[src]

`pub fn variant(&self) -> CECSEL_A`[src]

Get enumerated values variant

`pub fn is_lse(&self) -> bool`[src]

Checks if the value of the field is LSE

`pub fn is_hsi_div488(&self) -> bool`[src]

Checks if the value of the field is HSI_DIV488

`impl R<bool, CK48MSEL_A>`[src]

`pub fn variant(&self) -> CK48MSEL_A`[src]

Get enumerated values variant

`pub fn is_pll(&self) -> bool`[src]

Checks if the value of the field is PLL

`pub fn is_pllsai(&self) -> bool`[src]

Checks if the value of the field is PLLSAI

`impl R<bool, SDMMC1SEL_A>`[src]

`pub fn variant(&self) -> SDMMC1SEL_A`[src]

Get enumerated values variant

`pub fn is_ck48m(&self) -> bool`[src]

Checks if the value of the field is CK48M

`pub fn is_sysclk(&self) -> bool`[src]

Checks if the value of the field is SYSCLK

`impl R<bool, DSISEL_A>`[src]

`pub fn variant(&self) -> DSISEL_A`[src]

Get enumerated values variant

`pub fn is_dsi_phy(&self) -> bool`[src]

Checks if the value of the field is DSI_PHY

`pub fn is_pllr(&self) -> bool`[src]

Checks if the value of the field is PLLR

`impl R<u32, Reg<u32, _DCKCFGR2>>`[src]

`pub fn usart1sel(&self) -> USART1SEL_R`[src]

Bits 0:1 - USART 1 clock source selection

`pub fn usart2sel(&self) -> USART2SEL_R`[src]

Bits 2:3 - USART 2 clock source selection

`pub fn usart3sel(&self) -> USART3SEL_R`[src]

Bits 4:5 - USART 3 clock source selection

`pub fn uart4sel(&self) -> UART4SEL_R`[src]

Bits 6:7 - UART 4 clock source selection

`pub fn uart5sel(&self) -> UART5SEL_R`[src]

Bits 8:9 - UART 5 clock source selection

`pub fn usart6sel(&self) -> USART6SEL_R`[src]

Bits 10:11 - USART 6 clock source selection

`pub fn uart7sel(&self) -> UART7SEL_R`[src]

Bits 12:13 - UART 7 clock source selection

`pub fn uart8sel(&self) -> UART8SEL_R`[src]

Bits 14:15 - UART 8 clock source selection

`pub fn i2c1sel(&self) -> I2C1SEL_R`[src]

Bits 16:17 - I2C1 clock source selection

`pub fn i2c2sel(&self) -> I2C2SEL_R`[src]

Bits 18:19 - I2C2 clock source selection

`pub fn i2c3sel(&self) -> I2C3SEL_R`[src]

Bits 20:21 - I2C3 clock source selection

`pub fn i2c4sel(&self) -> I2C4SEL_R`[src]

Bits 22:23 - I2C4 clock source selection

`pub fn lptim1sel(&self) -> LPTIM1SEL_R`[src]

Bits 24:25 - Low power timer 1 clock source selection

`pub fn cecsel(&self) -> CECSEL_R`[src]

Bit 26 - HDMI-CEC clock source selection

`pub fn ck48msel(&self) -> CK48MSEL_R`[src]

Bit 27 - 48MHz clock source selection

`pub fn sdmmc1sel(&self) -> SDMMC1SEL_R`[src]

Bit 28 - SDMMC clock source selection

`pub fn sdmmc2sel(&self) -> SDMMC2SEL_R`[src]

Bit 29 - SDMMC2 clock source selection

`pub fn dsisel(&self) -> DSISEL_R`[src]

Bit 30 - DSI clock source selection

`impl R<u8, MODER15_A>`[src]

`pub fn variant(&self) -> MODER15_A`[src]

Get enumerated values variant

`pub fn is_input(&self) -> bool`[src]

Checks if the value of the field is INPUT

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`pub fn is_alternate(&self) -> bool`[src]

Checks if the value of the field is ALTERNATE

`pub fn is_analog(&self) -> bool`[src]

Checks if the value of the field is ANALOG

`impl R<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&self) -> MODER15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&self) -> MODER14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&self) -> MODER13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&self) -> MODER12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&self) -> MODER11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&self) -> MODER10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&self) -> MODER9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&self) -> MODER8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&self) -> MODER7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&self) -> MODER6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&self) -> MODER5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&self) -> MODER4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&self) -> MODER3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&self) -> MODER2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&self) -> MODER1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&self) -> MODER0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, OT15_A>`[src]

`pub fn variant(&self) -> OT15_A`[src]

Get enumerated values variant

`pub fn is_push_pull(&self) -> bool`[src]

Checks if the value of the field is PUSHPULL

`pub fn is_open_drain(&self) -> bool`[src]

Checks if the value of the field is OPENDRAIN

`impl R<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&self) -> OT15_R`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&self) -> OT14_R`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&self) -> OT13_R`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&self) -> OT12_R`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&self) -> OT11_R`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&self) -> OT10_R`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&self) -> OT9_R`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&self) -> OT8_R`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&self) -> OT7_R`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&self) -> OT6_R`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&self) -> OT5_R`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&self) -> OT4_R`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&self) -> OT3_R`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&self) -> OT2_R`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&self) -> OT1_R`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&self) -> OT0_R`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl R<u8, OSPEEDR15_A>`[src]

`pub fn variant(&self) -> OSPEEDR15_A`[src]

Get enumerated values variant

`pub fn is_low_speed(&self) -> bool`[src]

Checks if the value of the field is LOWSPEED

`pub fn is_medium_speed(&self) -> bool`[src]

Checks if the value of the field is MEDIUMSPEED

`pub fn is_high_speed(&self) -> bool`[src]

Checks if the value of the field is HIGHSPEED

`pub fn is_very_high_speed(&self) -> bool`[src]

Checks if the value of the field is VERYHIGHSPEED

`impl R<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&self) -> OSPEEDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn ospeedr14(&self) -> OSPEEDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn ospeedr13(&self) -> OSPEEDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn ospeedr12(&self) -> OSPEEDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn ospeedr11(&self) -> OSPEEDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn ospeedr10(&self) -> OSPEEDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn ospeedr9(&self) -> OSPEEDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn ospeedr8(&self) -> OSPEEDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn ospeedr7(&self) -> OSPEEDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn ospeedr6(&self) -> OSPEEDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn ospeedr5(&self) -> OSPEEDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn ospeedr4(&self) -> OSPEEDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn ospeedr3(&self) -> OSPEEDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn ospeedr2(&self) -> OSPEEDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn ospeedr1(&self) -> OSPEEDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn ospeedr0(&self) -> OSPEEDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<u8, PUPDR15_A>`[src]

`pub fn variant(&self) -> Variant<u8, PUPDR15_A>`[src]

Get enumerated values variant

`pub fn is_floating(&self) -> bool`[src]

Checks if the value of the field is FLOATING

`pub fn is_pull_up(&self) -> bool`[src]

Checks if the value of the field is PULLUP

`pub fn is_pull_down(&self) -> bool`[src]

Checks if the value of the field is PULLDOWN

`impl R<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&self) -> PUPDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&self) -> PUPDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&self) -> PUPDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&self) -> PUPDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&self) -> PUPDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&self) -> PUPDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&self) -> PUPDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&self) -> PUPDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&self) -> PUPDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&self) -> PUPDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&self) -> PUPDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&self) -> PUPDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&self) -> PUPDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&self) -> PUPDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&self) -> PUPDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&self) -> PUPDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, IDR15_A>`[src]

`pub fn variant(&self) -> IDR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _IDR>>`[src]

`pub fn idr15(&self) -> IDR15_R`[src]

Bit 15 - Port input data (y = 0..15)

`pub fn idr14(&self) -> IDR14_R`[src]

Bit 14 - Port input data (y = 0..15)

`pub fn idr13(&self) -> IDR13_R`[src]

Bit 13 - Port input data (y = 0..15)

`pub fn idr12(&self) -> IDR12_R`[src]

Bit 12 - Port input data (y = 0..15)

`pub fn idr11(&self) -> IDR11_R`[src]

Bit 11 - Port input data (y = 0..15)

`pub fn idr10(&self) -> IDR10_R`[src]

Bit 10 - Port input data (y = 0..15)

`pub fn idr9(&self) -> IDR9_R`[src]

Bit 9 - Port input data (y = 0..15)

`pub fn idr8(&self) -> IDR8_R`[src]

Bit 8 - Port input data (y = 0..15)

`pub fn idr7(&self) -> IDR7_R`[src]

Bit 7 - Port input data (y = 0..15)

`pub fn idr6(&self) -> IDR6_R`[src]

Bit 6 - Port input data (y = 0..15)

`pub fn idr5(&self) -> IDR5_R`[src]

Bit 5 - Port input data (y = 0..15)

`pub fn idr4(&self) -> IDR4_R`[src]

Bit 4 - Port input data (y = 0..15)

`pub fn idr3(&self) -> IDR3_R`[src]

Bit 3 - Port input data (y = 0..15)

`pub fn idr2(&self) -> IDR2_R`[src]

Bit 2 - Port input data (y = 0..15)

`pub fn idr1(&self) -> IDR1_R`[src]

Bit 1 - Port input data (y = 0..15)

`pub fn idr0(&self) -> IDR0_R`[src]

Bit 0 - Port input data (y = 0..15)

`impl R<bool, ODR15_A>`[src]

`pub fn variant(&self) -> ODR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&self) -> ODR15_R`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&self) -> ODR14_R`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&self) -> ODR13_R`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&self) -> ODR12_R`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&self) -> ODR11_R`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&self) -> ODR10_R`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&self) -> ODR9_R`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&self) -> ODR8_R`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&self) -> ODR7_R`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&self) -> ODR6_R`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&self) -> ODR5_R`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&self) -> ODR4_R`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&self) -> ODR3_R`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&self) -> ODR2_R`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&self) -> ODR1_R`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&self) -> ODR0_R`[src]

Bit 0 - Port output data (y = 0..15)

`impl R<bool, LCKK_A>`[src]

`pub fn variant(&self) -> LCKK_A`[src]

Get enumerated values variant

`pub fn is_not_active(&self) -> bool`[src]

Checks if the value of the field is NOTACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<bool, LCK15_A>`[src]

`pub fn variant(&self) -> LCK15_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<bool, LCK9_A>`[src]

`pub fn variant(&self) -> LCK9_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&self) -> LCKK_R`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&self) -> LCK15_R`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&self) -> LCK14_R`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&self) -> LCK13_R`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&self) -> LCK12_R`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&self) -> LCK11_R`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&self) -> LCK10_R`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&self) -> LCK9_R`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&self) -> LCK8_R`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&self) -> LCK7_R`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&self) -> LCK6_R`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&self) -> LCK5_R`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&self) -> LCK4_R`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&self) -> LCK3_R`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&self) -> LCK2_R`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&self) -> LCK1_R`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&self) -> LCK0_R`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl R<u8, AFRL7_A>`[src]

`pub fn variant(&self) -> AFRL7_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&self) -> AFRL7_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&self) -> AFRL6_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&self) -> AFRL5_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&self) -> AFRL4_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&self) -> AFRL3_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&self) -> AFRL2_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&self) -> AFRL1_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&self) -> AFRL0_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl R<u8, AFRH15_A>`[src]

`pub fn variant(&self) -> AFRH15_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&self) -> AFRH15_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&self) -> AFRH14_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&self) -> AFRH13_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&self) -> AFRH12_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&self) -> AFRH11_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&self) -> AFRH10_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&self) -> AFRH9_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&self) -> AFRH8_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl R<u32, Reg<u32, _BRR>>`[src]

`pub fn br0(&self) -> BR0_R`[src]

Bit 0 - Port D Reset bit 0

`pub fn br1(&self) -> BR1_R`[src]

Bit 1 - Port D Reset bit 1

`pub fn br2(&self) -> BR2_R`[src]

Bit 2 - Port D Reset bit 2

`pub fn br3(&self) -> BR3_R`[src]

Bit 3 - Port D Reset bit 3

`pub fn br4(&self) -> BR4_R`[src]

Bit 4 - Port D Reset bit 4

`pub fn br5(&self) -> BR5_R`[src]

Bit 5 - Port D Reset bit 5

`pub fn br6(&self) -> BR6_R`[src]

Bit 6 - Port D Reset bit 6

`pub fn br7(&self) -> BR7_R`[src]

Bit 7 - Port D Reset bit 7

`pub fn br8(&self) -> BR8_R`[src]

Bit 8 - Port D Reset bit 8

`pub fn br9(&self) -> BR9_R`[src]

Bit 9 - Port D Reset bit 9

`pub fn br10(&self) -> BR10_R`[src]

Bit 10 - Port D Reset bit 10

`pub fn br11(&self) -> BR11_R`[src]

Bit 11 - Port D Reset bit 11

`pub fn br12(&self) -> BR12_R`[src]

Bit 12 - Port D Reset bit 12

`pub fn br13(&self) -> BR13_R`[src]

Bit 13 - Port D Reset bit 13

`pub fn br14(&self) -> BR14_R`[src]

Bit 14 - Port D Reset bit 14

`pub fn br15(&self) -> BR15_R`[src]

Bit 15 - Port D Reset bit 15

`impl R<u8, MODER15_A>`[src]

`pub fn variant(&self) -> MODER15_A`[src]

Get enumerated values variant

`pub fn is_input(&self) -> bool`[src]

Checks if the value of the field is INPUT

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`pub fn is_alternate(&self) -> bool`[src]

Checks if the value of the field is ALTERNATE

`pub fn is_analog(&self) -> bool`[src]

Checks if the value of the field is ANALOG

`impl R<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&self) -> MODER15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&self) -> MODER14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&self) -> MODER13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&self) -> MODER12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&self) -> MODER11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&self) -> MODER10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&self) -> MODER9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&self) -> MODER8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&self) -> MODER7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&self) -> MODER6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&self) -> MODER5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&self) -> MODER4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&self) -> MODER3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&self) -> MODER2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&self) -> MODER1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&self) -> MODER0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, OT15_A>`[src]

`pub fn variant(&self) -> OT15_A`[src]

Get enumerated values variant

`pub fn is_push_pull(&self) -> bool`[src]

Checks if the value of the field is PUSHPULL

`pub fn is_open_drain(&self) -> bool`[src]

Checks if the value of the field is OPENDRAIN

`impl R<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&self) -> OT15_R`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&self) -> OT14_R`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&self) -> OT13_R`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&self) -> OT12_R`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&self) -> OT11_R`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&self) -> OT10_R`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&self) -> OT9_R`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&self) -> OT8_R`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&self) -> OT7_R`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&self) -> OT6_R`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&self) -> OT5_R`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&self) -> OT4_R`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&self) -> OT3_R`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&self) -> OT2_R`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&self) -> OT1_R`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&self) -> OT0_R`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl R<u8, OSPEEDR15_A>`[src]

`pub fn variant(&self) -> OSPEEDR15_A`[src]

Get enumerated values variant

`pub fn is_low_speed(&self) -> bool`[src]

Checks if the value of the field is LOWSPEED

`pub fn is_medium_speed(&self) -> bool`[src]

Checks if the value of the field is MEDIUMSPEED

`pub fn is_high_speed(&self) -> bool`[src]

Checks if the value of the field is HIGHSPEED

`pub fn is_very_high_speed(&self) -> bool`[src]

Checks if the value of the field is VERYHIGHSPEED

`impl R<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&self) -> OSPEEDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn ospeedr14(&self) -> OSPEEDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn ospeedr13(&self) -> OSPEEDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn ospeedr12(&self) -> OSPEEDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn ospeedr11(&self) -> OSPEEDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn ospeedr10(&self) -> OSPEEDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn ospeedr9(&self) -> OSPEEDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn ospeedr8(&self) -> OSPEEDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn ospeedr7(&self) -> OSPEEDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn ospeedr6(&self) -> OSPEEDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn ospeedr5(&self) -> OSPEEDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn ospeedr4(&self) -> OSPEEDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn ospeedr3(&self) -> OSPEEDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn ospeedr2(&self) -> OSPEEDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn ospeedr1(&self) -> OSPEEDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn ospeedr0(&self) -> OSPEEDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<u8, PUPDR15_A>`[src]

`pub fn variant(&self) -> Variant<u8, PUPDR15_A>`[src]

Get enumerated values variant

`pub fn is_floating(&self) -> bool`[src]

Checks if the value of the field is FLOATING

`pub fn is_pull_up(&self) -> bool`[src]

Checks if the value of the field is PULLUP

`pub fn is_pull_down(&self) -> bool`[src]

Checks if the value of the field is PULLDOWN

`impl R<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&self) -> PUPDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&self) -> PUPDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&self) -> PUPDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&self) -> PUPDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&self) -> PUPDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&self) -> PUPDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&self) -> PUPDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&self) -> PUPDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&self) -> PUPDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&self) -> PUPDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&self) -> PUPDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&self) -> PUPDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&self) -> PUPDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&self) -> PUPDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&self) -> PUPDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&self) -> PUPDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, IDR15_A>`[src]

`pub fn variant(&self) -> IDR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _IDR>>`[src]

`pub fn idr15(&self) -> IDR15_R`[src]

Bit 15 - Port input data (y = 0..15)

`pub fn idr14(&self) -> IDR14_R`[src]

Bit 14 - Port input data (y = 0..15)

`pub fn idr13(&self) -> IDR13_R`[src]

Bit 13 - Port input data (y = 0..15)

`pub fn idr12(&self) -> IDR12_R`[src]

Bit 12 - Port input data (y = 0..15)

`pub fn idr11(&self) -> IDR11_R`[src]

Bit 11 - Port input data (y = 0..15)

`pub fn idr10(&self) -> IDR10_R`[src]

Bit 10 - Port input data (y = 0..15)

`pub fn idr9(&self) -> IDR9_R`[src]

Bit 9 - Port input data (y = 0..15)

`pub fn idr8(&self) -> IDR8_R`[src]

Bit 8 - Port input data (y = 0..15)

`pub fn idr7(&self) -> IDR7_R`[src]

Bit 7 - Port input data (y = 0..15)

`pub fn idr6(&self) -> IDR6_R`[src]

Bit 6 - Port input data (y = 0..15)

`pub fn idr5(&self) -> IDR5_R`[src]

Bit 5 - Port input data (y = 0..15)

`pub fn idr4(&self) -> IDR4_R`[src]

Bit 4 - Port input data (y = 0..15)

`pub fn idr3(&self) -> IDR3_R`[src]

Bit 3 - Port input data (y = 0..15)

`pub fn idr2(&self) -> IDR2_R`[src]

Bit 2 - Port input data (y = 0..15)

`pub fn idr1(&self) -> IDR1_R`[src]

Bit 1 - Port input data (y = 0..15)

`pub fn idr0(&self) -> IDR0_R`[src]

Bit 0 - Port input data (y = 0..15)

`impl R<bool, ODR15_A>`[src]

`pub fn variant(&self) -> ODR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&self) -> ODR15_R`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&self) -> ODR14_R`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&self) -> ODR13_R`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&self) -> ODR12_R`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&self) -> ODR11_R`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&self) -> ODR10_R`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&self) -> ODR9_R`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&self) -> ODR8_R`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&self) -> ODR7_R`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&self) -> ODR6_R`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&self) -> ODR5_R`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&self) -> ODR4_R`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&self) -> ODR3_R`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&self) -> ODR2_R`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&self) -> ODR1_R`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&self) -> ODR0_R`[src]

Bit 0 - Port output data (y = 0..15)

`impl R<bool, LCKK_A>`[src]

`pub fn variant(&self) -> LCKK_A`[src]

Get enumerated values variant

`pub fn is_not_active(&self) -> bool`[src]

Checks if the value of the field is NOTACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<bool, LCK15_A>`[src]

`pub fn variant(&self) -> LCK15_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<bool, LCK9_A>`[src]

`pub fn variant(&self) -> LCK9_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&self) -> LCKK_R`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&self) -> LCK15_R`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&self) -> LCK14_R`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&self) -> LCK13_R`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&self) -> LCK12_R`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&self) -> LCK11_R`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&self) -> LCK10_R`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&self) -> LCK9_R`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&self) -> LCK8_R`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&self) -> LCK7_R`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&self) -> LCK6_R`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&self) -> LCK5_R`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&self) -> LCK4_R`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&self) -> LCK3_R`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&self) -> LCK2_R`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&self) -> LCK1_R`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&self) -> LCK0_R`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl R<u8, AFRL7_A>`[src]

`pub fn variant(&self) -> AFRL7_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&self) -> AFRL7_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&self) -> AFRL6_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&self) -> AFRL5_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&self) -> AFRL4_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&self) -> AFRL3_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&self) -> AFRL2_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&self) -> AFRL1_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&self) -> AFRL0_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl R<u8, AFRH15_A>`[src]

`pub fn variant(&self) -> AFRH15_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&self) -> AFRH15_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&self) -> AFRH14_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&self) -> AFRH13_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&self) -> AFRH12_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&self) -> AFRH11_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&self) -> AFRH10_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&self) -> AFRH9_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&self) -> AFRH8_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl R<u32, Reg<u32, _BRR>>`[src]

`pub fn br0(&self) -> BR0_R`[src]

Bit 0 - Port B Reset bit 0

`pub fn br1(&self) -> BR1_R`[src]

Bit 1 - Port B Reset bit 1

`pub fn br2(&self) -> BR2_R`[src]

Bit 2 - Port B Reset bit 2

`pub fn br3(&self) -> BR3_R`[src]

Bit 3 - Port B Reset bit 3

`pub fn br4(&self) -> BR4_R`[src]

Bit 4 - Port B Reset bit 4

`pub fn br5(&self) -> BR5_R`[src]

Bit 5 - Port B Reset bit 5

`pub fn br6(&self) -> BR6_R`[src]

Bit 6 - Port B Reset bit 6

`pub fn br7(&self) -> BR7_R`[src]

Bit 7 - Port B Reset bit 7

`pub fn br8(&self) -> BR8_R`[src]

Bit 8 - Port B Reset bit 8

`pub fn br9(&self) -> BR9_R`[src]

Bit 9 - Port B Reset bit 9

`pub fn br10(&self) -> BR10_R`[src]

Bit 10 - Port B Reset bit 10

`pub fn br11(&self) -> BR11_R`[src]

Bit 11 - Port B Reset bit 11

`pub fn br12(&self) -> BR12_R`[src]

Bit 12 - Port B Reset bit 12

`pub fn br13(&self) -> BR13_R`[src]

Bit 13 - Port B Reset bit 13

`pub fn br14(&self) -> BR14_R`[src]

Bit 14 - Port B Reset bit 14

`pub fn br15(&self) -> BR15_R`[src]

Bit 15 - Port B Reset bit 15

`impl R<u8, MODER15_A>`[src]

`pub fn variant(&self) -> MODER15_A`[src]

Get enumerated values variant

`pub fn is_input(&self) -> bool`[src]

Checks if the value of the field is INPUT

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`pub fn is_alternate(&self) -> bool`[src]

Checks if the value of the field is ALTERNATE

`pub fn is_analog(&self) -> bool`[src]

Checks if the value of the field is ANALOG

`impl R<u32, Reg<u32, _MODER>>`[src]

`pub fn moder15(&self) -> MODER15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn moder14(&self) -> MODER14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn moder13(&self) -> MODER13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn moder12(&self) -> MODER12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn moder11(&self) -> MODER11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn moder10(&self) -> MODER10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn moder9(&self) -> MODER9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn moder8(&self) -> MODER8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn moder7(&self) -> MODER7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn moder6(&self) -> MODER6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn moder5(&self) -> MODER5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn moder4(&self) -> MODER4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn moder3(&self) -> MODER3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn moder2(&self) -> MODER2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn moder1(&self) -> MODER1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn moder0(&self) -> MODER0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, OT15_A>`[src]

`pub fn variant(&self) -> OT15_A`[src]

Get enumerated values variant

`pub fn is_push_pull(&self) -> bool`[src]

Checks if the value of the field is PUSHPULL

`pub fn is_open_drain(&self) -> bool`[src]

Checks if the value of the field is OPENDRAIN

`impl R<u32, Reg<u32, _OTYPER>>`[src]

`pub fn ot15(&self) -> OT15_R`[src]

Bit 15 - Port x configuration bits (y = 0..15)

`pub fn ot14(&self) -> OT14_R`[src]

Bit 14 - Port x configuration bits (y = 0..15)

`pub fn ot13(&self) -> OT13_R`[src]

Bit 13 - Port x configuration bits (y = 0..15)

`pub fn ot12(&self) -> OT12_R`[src]

Bit 12 - Port x configuration bits (y = 0..15)

`pub fn ot11(&self) -> OT11_R`[src]

Bit 11 - Port x configuration bits (y = 0..15)

`pub fn ot10(&self) -> OT10_R`[src]

Bit 10 - Port x configuration bits (y = 0..15)

`pub fn ot9(&self) -> OT9_R`[src]

Bit 9 - Port x configuration bits (y = 0..15)

`pub fn ot8(&self) -> OT8_R`[src]

Bit 8 - Port x configuration bits (y = 0..15)

`pub fn ot7(&self) -> OT7_R`[src]

Bit 7 - Port x configuration bits (y = 0..15)

`pub fn ot6(&self) -> OT6_R`[src]

Bit 6 - Port x configuration bits (y = 0..15)

`pub fn ot5(&self) -> OT5_R`[src]

Bit 5 - Port x configuration bits (y = 0..15)

`pub fn ot4(&self) -> OT4_R`[src]

Bit 4 - Port x configuration bits (y = 0..15)

`pub fn ot3(&self) -> OT3_R`[src]

Bit 3 - Port x configuration bits (y = 0..15)

`pub fn ot2(&self) -> OT2_R`[src]

Bit 2 - Port x configuration bits (y = 0..15)

`pub fn ot1(&self) -> OT1_R`[src]

Bit 1 - Port x configuration bits (y = 0..15)

`pub fn ot0(&self) -> OT0_R`[src]

Bit 0 - Port x configuration bits (y = 0..15)

`impl R<u8, OSPEEDR15_A>`[src]

`pub fn variant(&self) -> OSPEEDR15_A`[src]

Get enumerated values variant

`pub fn is_low_speed(&self) -> bool`[src]

Checks if the value of the field is LOWSPEED

`pub fn is_medium_speed(&self) -> bool`[src]

Checks if the value of the field is MEDIUMSPEED

`pub fn is_high_speed(&self) -> bool`[src]

Checks if the value of the field is HIGHSPEED

`pub fn is_very_high_speed(&self) -> bool`[src]

Checks if the value of the field is VERYHIGHSPEED

`impl R<u32, Reg<u32, _OSPEEDR>>`[src]

`pub fn ospeedr15(&self) -> OSPEEDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn ospeedr14(&self) -> OSPEEDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn ospeedr13(&self) -> OSPEEDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn ospeedr12(&self) -> OSPEEDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn ospeedr11(&self) -> OSPEEDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn ospeedr10(&self) -> OSPEEDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn ospeedr9(&self) -> OSPEEDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn ospeedr8(&self) -> OSPEEDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn ospeedr7(&self) -> OSPEEDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn ospeedr6(&self) -> OSPEEDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn ospeedr5(&self) -> OSPEEDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn ospeedr4(&self) -> OSPEEDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn ospeedr3(&self) -> OSPEEDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn ospeedr2(&self) -> OSPEEDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn ospeedr1(&self) -> OSPEEDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn ospeedr0(&self) -> OSPEEDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<u8, PUPDR15_A>`[src]

`pub fn variant(&self) -> Variant<u8, PUPDR15_A>`[src]

Get enumerated values variant

`pub fn is_floating(&self) -> bool`[src]

Checks if the value of the field is FLOATING

`pub fn is_pull_up(&self) -> bool`[src]

Checks if the value of the field is PULLUP

`pub fn is_pull_down(&self) -> bool`[src]

Checks if the value of the field is PULLDOWN

`impl R<u32, Reg<u32, _PUPDR>>`[src]

`pub fn pupdr15(&self) -> PUPDR15_R`[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

`pub fn pupdr14(&self) -> PUPDR14_R`[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

`pub fn pupdr13(&self) -> PUPDR13_R`[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

`pub fn pupdr12(&self) -> PUPDR12_R`[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

`pub fn pupdr11(&self) -> PUPDR11_R`[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

`pub fn pupdr10(&self) -> PUPDR10_R`[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

`pub fn pupdr9(&self) -> PUPDR9_R`[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

`pub fn pupdr8(&self) -> PUPDR8_R`[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

`pub fn pupdr7(&self) -> PUPDR7_R`[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

`pub fn pupdr6(&self) -> PUPDR6_R`[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

`pub fn pupdr5(&self) -> PUPDR5_R`[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

`pub fn pupdr4(&self) -> PUPDR4_R`[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

`pub fn pupdr3(&self) -> PUPDR3_R`[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

`pub fn pupdr2(&self) -> PUPDR2_R`[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

`pub fn pupdr1(&self) -> PUPDR1_R`[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

`pub fn pupdr0(&self) -> PUPDR0_R`[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

`impl R<bool, IDR15_A>`[src]

`pub fn variant(&self) -> IDR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _IDR>>`[src]

`pub fn idr15(&self) -> IDR15_R`[src]

Bit 15 - Port input data (y = 0..15)

`pub fn idr14(&self) -> IDR14_R`[src]

Bit 14 - Port input data (y = 0..15)

`pub fn idr13(&self) -> IDR13_R`[src]

Bit 13 - Port input data (y = 0..15)

`pub fn idr12(&self) -> IDR12_R`[src]

Bit 12 - Port input data (y = 0..15)

`pub fn idr11(&self) -> IDR11_R`[src]

Bit 11 - Port input data (y = 0..15)

`pub fn idr10(&self) -> IDR10_R`[src]

Bit 10 - Port input data (y = 0..15)

`pub fn idr9(&self) -> IDR9_R`[src]

Bit 9 - Port input data (y = 0..15)

`pub fn idr8(&self) -> IDR8_R`[src]

Bit 8 - Port input data (y = 0..15)

`pub fn idr7(&self) -> IDR7_R`[src]

Bit 7 - Port input data (y = 0..15)

`pub fn idr6(&self) -> IDR6_R`[src]

Bit 6 - Port input data (y = 0..15)

`pub fn idr5(&self) -> IDR5_R`[src]

Bit 5 - Port input data (y = 0..15)

`pub fn idr4(&self) -> IDR4_R`[src]

Bit 4 - Port input data (y = 0..15)

`pub fn idr3(&self) -> IDR3_R`[src]

Bit 3 - Port input data (y = 0..15)

`pub fn idr2(&self) -> IDR2_R`[src]

Bit 2 - Port input data (y = 0..15)

`pub fn idr1(&self) -> IDR1_R`[src]

Bit 1 - Port input data (y = 0..15)

`pub fn idr0(&self) -> IDR0_R`[src]

Bit 0 - Port input data (y = 0..15)

`impl R<bool, ODR15_A>`[src]

`pub fn variant(&self) -> ODR15_A`[src]

Get enumerated values variant

`pub fn is_high(&self) -> bool`[src]

Checks if the value of the field is HIGH

`pub fn is_low(&self) -> bool`[src]

Checks if the value of the field is LOW

`impl R<u32, Reg<u32, _ODR>>`[src]

`pub fn odr15(&self) -> ODR15_R`[src]

Bit 15 - Port output data (y = 0..15)

`pub fn odr14(&self) -> ODR14_R`[src]

Bit 14 - Port output data (y = 0..15)

`pub fn odr13(&self) -> ODR13_R`[src]

Bit 13 - Port output data (y = 0..15)

`pub fn odr12(&self) -> ODR12_R`[src]

Bit 12 - Port output data (y = 0..15)

`pub fn odr11(&self) -> ODR11_R`[src]

Bit 11 - Port output data (y = 0..15)

`pub fn odr10(&self) -> ODR10_R`[src]

Bit 10 - Port output data (y = 0..15)

`pub fn odr9(&self) -> ODR9_R`[src]

Bit 9 - Port output data (y = 0..15)

`pub fn odr8(&self) -> ODR8_R`[src]

Bit 8 - Port output data (y = 0..15)

`pub fn odr7(&self) -> ODR7_R`[src]

Bit 7 - Port output data (y = 0..15)

`pub fn odr6(&self) -> ODR6_R`[src]

Bit 6 - Port output data (y = 0..15)

`pub fn odr5(&self) -> ODR5_R`[src]

Bit 5 - Port output data (y = 0..15)

`pub fn odr4(&self) -> ODR4_R`[src]

Bit 4 - Port output data (y = 0..15)

`pub fn odr3(&self) -> ODR3_R`[src]

Bit 3 - Port output data (y = 0..15)

`pub fn odr2(&self) -> ODR2_R`[src]

Bit 2 - Port output data (y = 0..15)

`pub fn odr1(&self) -> ODR1_R`[src]

Bit 1 - Port output data (y = 0..15)

`pub fn odr0(&self) -> ODR0_R`[src]

Bit 0 - Port output data (y = 0..15)

`impl R<bool, LCKK_A>`[src]

`pub fn variant(&self) -> LCKK_A`[src]

Get enumerated values variant

`pub fn is_not_active(&self) -> bool`[src]

Checks if the value of the field is NOTACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<bool, LCK15_A>`[src]

`pub fn variant(&self) -> LCK15_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<bool, LCK9_A>`[src]

`pub fn variant(&self) -> LCK9_A`[src]

Get enumerated values variant

`pub fn is_unlocked(&self) -> bool`[src]

Checks if the value of the field is UNLOCKED

`pub fn is_locked(&self) -> bool`[src]

Checks if the value of the field is LOCKED

`impl R<u32, Reg<u32, _LCKR>>`[src]

`pub fn lckk(&self) -> LCKK_R`[src]

Bit 16 - Port x lock bit y (y= 0..15)

`pub fn lck15(&self) -> LCK15_R`[src]

Bit 15 - Port x lock bit y (y= 0..15)

`pub fn lck14(&self) -> LCK14_R`[src]

Bit 14 - Port x lock bit y (y= 0..15)

`pub fn lck13(&self) -> LCK13_R`[src]

Bit 13 - Port x lock bit y (y= 0..15)

`pub fn lck12(&self) -> LCK12_R`[src]

Bit 12 - Port x lock bit y (y= 0..15)

`pub fn lck11(&self) -> LCK11_R`[src]

Bit 11 - Port x lock bit y (y= 0..15)

`pub fn lck10(&self) -> LCK10_R`[src]

Bit 10 - Port x lock bit y (y= 0..15)

`pub fn lck9(&self) -> LCK9_R`[src]

Bit 9 - Port x lock bit y (y= 0..15)

`pub fn lck8(&self) -> LCK8_R`[src]

Bit 8 - Port x lock bit y (y= 0..15)

`pub fn lck7(&self) -> LCK7_R`[src]

Bit 7 - Port x lock bit y (y= 0..15)

`pub fn lck6(&self) -> LCK6_R`[src]

Bit 6 - Port x lock bit y (y= 0..15)

`pub fn lck5(&self) -> LCK5_R`[src]

Bit 5 - Port x lock bit y (y= 0..15)

`pub fn lck4(&self) -> LCK4_R`[src]

Bit 4 - Port x lock bit y (y= 0..15)

`pub fn lck3(&self) -> LCK3_R`[src]

Bit 3 - Port x lock bit y (y= 0..15)

`pub fn lck2(&self) -> LCK2_R`[src]

Bit 2 - Port x lock bit y (y= 0..15)

`pub fn lck1(&self) -> LCK1_R`[src]

Bit 1 - Port x lock bit y (y= 0..15)

`pub fn lck0(&self) -> LCK0_R`[src]

Bit 0 - Port x lock bit y (y= 0..15)

`impl R<u8, AFRL7_A>`[src]

`pub fn variant(&self) -> AFRL7_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRL>>`[src]

`pub fn afrl7(&self) -> AFRL7_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl6(&self) -> AFRL6_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl5(&self) -> AFRL5_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl4(&self) -> AFRL4_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl3(&self) -> AFRL3_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl2(&self) -> AFRL2_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl1(&self) -> AFRL1_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

`pub fn afrl0(&self) -> AFRL0_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

`impl R<u8, AFRH15_A>`[src]

`pub fn variant(&self) -> AFRH15_A`[src]

Get enumerated values variant

`pub fn is_af0(&self) -> bool`[src]

Checks if the value of the field is AF0

`pub fn is_af1(&self) -> bool`[src]

Checks if the value of the field is AF1

`pub fn is_af2(&self) -> bool`[src]

Checks if the value of the field is AF2

`pub fn is_af3(&self) -> bool`[src]

Checks if the value of the field is AF3

`pub fn is_af4(&self) -> bool`[src]

Checks if the value of the field is AF4

`pub fn is_af5(&self) -> bool`[src]

Checks if the value of the field is AF5

`pub fn is_af6(&self) -> bool`[src]

Checks if the value of the field is AF6

`pub fn is_af7(&self) -> bool`[src]

Checks if the value of the field is AF7

`pub fn is_af8(&self) -> bool`[src]

Checks if the value of the field is AF8

`pub fn is_af9(&self) -> bool`[src]

Checks if the value of the field is AF9

`pub fn is_af10(&self) -> bool`[src]

Checks if the value of the field is AF10

`pub fn is_af11(&self) -> bool`[src]

Checks if the value of the field is AF11

`pub fn is_af12(&self) -> bool`[src]

Checks if the value of the field is AF12

`pub fn is_af13(&self) -> bool`[src]

Checks if the value of the field is AF13

`pub fn is_af14(&self) -> bool`[src]

Checks if the value of the field is AF14

`pub fn is_af15(&self) -> bool`[src]

Checks if the value of the field is AF15

`impl R<u32, Reg<u32, _AFRH>>`[src]

`pub fn afrh15(&self) -> AFRH15_R`[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh14(&self) -> AFRH14_R`[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh13(&self) -> AFRH13_R`[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh12(&self) -> AFRH12_R`[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh11(&self) -> AFRH11_R`[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh10(&self) -> AFRH10_R`[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh9(&self) -> AFRH9_R`[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

`pub fn afrh8(&self) -> AFRH8_R`[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

`impl R<u32, Reg<u32, _BRR>>`[src]

`pub fn br0(&self) -> BR0_R`[src]

Bit 0 - Port A Reset bit 0

`pub fn br1(&self) -> BR1_R`[src]

Bit 1 - Port A Reset bit 1

`pub fn br2(&self) -> BR2_R`[src]

Bit 2 - Port A Reset bit 2

`pub fn br3(&self) -> BR3_R`[src]

Bit 3 - Port A Reset bit 3

`pub fn br4(&self) -> BR4_R`[src]

Bit 4 - Port A Reset bit 4

`pub fn br5(&self) -> BR5_R`[src]

Bit 5 - Port A Reset bit 5

`pub fn br6(&self) -> BR6_R`[src]

Bit 6 - Port A Reset bit 6

`pub fn br7(&self) -> BR7_R`[src]

Bit 7 - Port A Reset bit 7

`pub fn br8(&self) -> BR8_R`[src]

Bit 8 - Port A Reset bit 8

`pub fn br9(&self) -> BR9_R`[src]

Bit 9 - Port A Reset bit 9

`pub fn br10(&self) -> BR10_R`[src]

Bit 10 - Port A Reset bit 10

`pub fn br11(&self) -> BR11_R`[src]

Bit 11 - Port A Reset bit 11

`pub fn br12(&self) -> BR12_R`[src]

Bit 12 - Port A Reset bit 12

`pub fn br13(&self) -> BR13_R`[src]

Bit 13 - Port A Reset bit 13

`pub fn br14(&self) -> BR14_R`[src]

Bit 14 - Port A Reset bit 14

`pub fn br15(&self) -> BR15_R`[src]

Bit 15 - Port A Reset bit 15

`impl R<u32, Reg<u32, _MEMRM>>`[src]

`pub fn mem_mode(&self) -> MEM_MODE_R`[src]

Bits 0:2 - Memory mapping selection

`pub fn fb_mode(&self) -> FB_MODE_R`[src]

Bit 8 - Flash bank mode selection

`pub fn swp_fmc(&self) -> SWP_FMC_R`[src]

Bits 10:11 - FMC memory mapping swap

`impl R<u32, Reg<u32, _PMC>>`[src]

`pub fn mii_rmii_sel(&self) -> MII_RMII_SEL_R`[src]

Bit 23 - Ethernet PHY interface selection

`pub fn adc1dc2(&self) -> ADC1DC2_R`[src]

Bit 16 - ADC1DC2

`pub fn adc2dc2(&self) -> ADC2DC2_R`[src]

Bit 17 - ADC2DC2

`pub fn adc3dc2(&self) -> ADC3DC2_R`[src]

Bit 18 - ADC3DC2

`impl R<u32, Reg<u32, _EXTICR1>>`[src]

`pub fn exti3(&self) -> EXTI3_R`[src]

Bits 12:15 - EXTI x configuration (x = 0 to 3)

`pub fn exti2(&self) -> EXTI2_R`[src]

Bits 8:11 - EXTI x configuration (x = 0 to 3)

`pub fn exti1(&self) -> EXTI1_R`[src]

Bits 4:7 - EXTI x configuration (x = 0 to 3)

`pub fn exti0(&self) -> EXTI0_R`[src]

Bits 0:3 - EXTI x configuration (x = 0 to 3)

`impl R<u32, Reg<u32, _EXTICR2>>`[src]

`pub fn exti7(&self) -> EXTI7_R`[src]

Bits 12:15 - EXTI x configuration (x = 4 to 7)

`pub fn exti6(&self) -> EXTI6_R`[src]

Bits 8:11 - EXTI x configuration (x = 4 to 7)

`pub fn exti5(&self) -> EXTI5_R`[src]

Bits 4:7 - EXTI x configuration (x = 4 to 7)

`pub fn exti4(&self) -> EXTI4_R`[src]

Bits 0:3 - EXTI x configuration (x = 4 to 7)

`impl R<u32, Reg<u32, _EXTICR3>>`[src]

`pub fn exti11(&self) -> EXTI11_R`[src]

Bits 12:15 - EXTI x configuration (x = 8 to 11)

`pub fn exti10(&self) -> EXTI10_R`[src]

Bits 8:11 - EXTI10

`pub fn exti9(&self) -> EXTI9_R`[src]

Bits 4:7 - EXTI x configuration (x = 8 to 11)

`pub fn exti8(&self) -> EXTI8_R`[src]

Bits 0:3 - EXTI x configuration (x = 8 to 11)

`impl R<u32, Reg<u32, _EXTICR4>>`[src]

`pub fn exti15(&self) -> EXTI15_R`[src]

Bits 12:15 - EXTI x configuration (x = 12 to 15)

`pub fn exti14(&self) -> EXTI14_R`[src]

Bits 8:11 - EXTI x configuration (x = 12 to 15)

`pub fn exti13(&self) -> EXTI13_R`[src]

Bits 4:7 - EXTI x configuration (x = 12 to 15)

`pub fn exti12(&self) -> EXTI12_R`[src]

Bits 0:3 - EXTI x configuration (x = 12 to 15)

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, BR_A>`[src]

`pub fn variant(&self) -> BR_A`[src]

Get enumerated values variant

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`pub fn is_div16(&self) -> bool`[src]

Checks if the value of the field is DIV16

`pub fn is_div32(&self) -> bool`[src]

Checks if the value of the field is DIV32

`pub fn is_div64(&self) -> bool`[src]

Checks if the value of the field is DIV64

`pub fn is_div128(&self) -> bool`[src]

Checks if the value of the field is DIV128

`pub fn is_div256(&self) -> bool`[src]

Checks if the value of the field is DIV256

`impl R<bool, MSTR_A>`[src]

`pub fn variant(&self) -> MSTR_A`[src]

Get enumerated values variant

`pub fn is_slave(&self) -> bool`[src]

Checks if the value of the field is SLAVE

`pub fn is_master(&self) -> bool`[src]

Checks if the value of the field is MASTER

`impl R<bool, CPOL_A>`[src]

`pub fn variant(&self) -> CPOL_A`[src]

Get enumerated values variant

`pub fn is_idle_low(&self) -> bool`[src]

Checks if the value of the field is IDLELOW

`pub fn is_idle_high(&self) -> bool`[src]

Checks if the value of the field is IDLEHIGH

`impl R<bool, CPHA_A>`[src]

`pub fn variant(&self) -> CPHA_A`[src]

Get enumerated values variant

`pub fn is_first_edge(&self) -> bool`[src]

Checks if the value of the field is FIRSTEDGE

`pub fn is_second_edge(&self) -> bool`[src]

Checks if the value of the field is SECONDEDGE

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn bidimode(&self) -> BIDIMODE_R`[src]

Bit 15 - Bidirectional data mode enable

`pub fn bidioe(&self) -> BIDIOE_R`[src]

Bit 14 - Output enable in bidirectional mode

`pub fn crcen(&self) -> CRCEN_R`[src]

Bit 13 - Hardware CRC calculation enable

`pub fn crcnext(&self) -> CRCNEXT_R`[src]

Bit 12 - CRC transfer next

`pub fn crcl(&self) -> CRCL_R`[src]

Bit 11 - CRC length

`pub fn rxonly(&self) -> RXONLY_R`[src]

Bit 10 - Receive only

`pub fn ssm(&self) -> SSM_R`[src]

Bit 9 - Software slave management

`pub fn ssi(&self) -> SSI_R`[src]

Bit 8 - Internal slave select

`pub fn lsbfirst(&self) -> LSBFIRST_R`[src]

Bit 7 - Frame format

`pub fn spe(&self) -> SPE_R`[src]

Bit 6 - SPI enable

`pub fn br(&self) -> BR_R`[src]

`pub fn is_six_bit(&self) -> bool`[src]

Checks if the value of the field is SIXBIT

`pub fn is_seven_bit(&self) -> bool`[src]

Checks if the value of the field is SEVENBIT

`pub fn is_eight_bit(&self) -> bool`[src]

Checks if the value of the field is EIGHTBIT

`pub fn is_nine_bit(&self) -> bool`[src]

Checks if the value of the field is NINEBIT

`pub fn is_ten_bit(&self) -> bool`[src]

Checks if the value of the field is TENBIT

`pub fn is_eleven_bit(&self) -> bool`[src]

Checks if the value of the field is ELEVENBIT

`pub fn is_twelve_bit(&self) -> bool`[src]

Checks if the value of the field is TWELVEBIT

`pub fn is_thirteen_bit(&self) -> bool`[src]

Checks if the value of the field is THIRTEENBIT

`pub fn is_fourteen_bit(&self) -> bool`[src]

Checks if the value of the field is FOURTEENBIT

`pub fn is_fifteen_bit(&self) -> bool`[src]

Checks if the value of the field is FIFTEENBIT

`pub fn is_sixteen_bit(&self) -> bool`[src]

Checks if the value of the field is SIXTEENBIT

`impl R<bool, FRXTH_A>`[src]

`pub fn variant(&self) -> FRXTH_A`[src]

Get enumerated values variant

`pub fn is_half(&self) -> bool`[src]

Checks if the value of the field is HALF

`pub fn is_quarter(&self) -> bool`[src]

Checks if the value of the field is QUARTER

`impl R<bool, LDMA_RX_A>`[src]

`pub fn variant(&self) -> LDMA_RX_A`[src]

Get enumerated values variant

`pub fn is_even(&self) -> bool`[src]

Checks if the value of the field is EVEN

`pub fn is_odd(&self) -> bool`[src]

Checks if the value of the field is ODD

`impl R<bool, LDMA_TX_A>`[src]

`pub fn variant(&self) -> LDMA_TX_A`[src]

Get enumerated values variant

`pub fn is_even(&self) -> bool`[src]

Checks if the value of the field is EVEN

`pub fn is_odd(&self) -> bool`[src]

Checks if the value of the field is ODD

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn rxdmaen(&self) -> RXDMAEN_R`[src]

Bit 0 - Rx buffer DMA enable

`pub fn txdmaen(&self) -> TXDMAEN_R`[src]

Bit 1 - Tx buffer DMA enable

`pub fn ssoe(&self) -> SSOE_R`[src]

Bit 2 - SS output enable

`pub fn nssp(&self) -> NSSP_R`[src]

Bit 3 - NSS pulse management

`pub fn frf(&self) -> FRF_R`[src]

Bit 4 - Frame format

`pub fn errie(&self) -> ERRIE_R`[src]

Bit 5 - Error interrupt enable

`pub fn rxneie(&self) -> RXNEIE_R`[src]

Bit 6 - RX buffer not empty interrupt enable

`pub fn txeie(&self) -> TXEIE_R`[src]

Bit 7 - Tx buffer empty interrupt enable

`pub fn ds(&self) -> DS_R`[src]

Bit 7 - Busy flag

`pub fn ovr(&self) -> OVR_R`[src]

Bit 6 - Overrun flag

`pub fn modf(&self) -> MODF_R`[src]

Bit 5 - Mode fault

`pub fn crcerr(&self) -> CRCERR_R`[src]

Bit 4 - CRC error flag

`pub fn udr(&self) -> UDR_R`[src]

Bit 3 - Underrun flag

`pub fn chside(&self) -> CHSIDE_R`[src]

Bit 2 - Channel side

`pub fn txe(&self) -> TXE_R`[src]

Bit 1 - Transmit buffer empty

`pub fn rxne(&self) -> RXNE_R`[src]

Bit 0 - Receive buffer not empty

`pub fn frlvl(&self) -> FRLVL_R`[src]

Bits 9:10 - FIFO reception level

`pub fn ftlvl(&self) -> FTLVL_R`[src]

Bits 11:12 - FIFO Transmission Level

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&self) -> DR_R`[src]

Bits 0:15 - Data register

`impl R<u32, Reg<u32, _CRCPR>>`[src]

`pub fn crcpoly(&self) -> CRCPOLY_R`[src]

Bits 0:15 - CRC polynomial register

`impl R<u32, Reg<u32, _RXCRCR>>`[src]

`pub fn rx_crc(&self) -> RXCRC_R`[src]

Bits 0:15 - Rx CRC register

Checks if the value of the field is SLAVETX

`pub fn is_slave_rx(&self) -> bool`[src]

Checks if the value of the field is SLAVERX

`pub fn is_master_tx(&self) -> bool`[src]

Checks if the value of the field is MASTERTX

`pub fn is_master_rx(&self) -> bool`[src]

Checks if the value of the field is MASTERRX

`impl R<bool, PCMSYNC_A>`[src]

`pub fn variant(&self) -> PCMSYNC_A`[src]

Get enumerated values variant

`pub fn is_short(&self) -> bool`[src]

Checks if the value of the field is SHORT

`pub fn is_long(&self) -> bool`[src]

Checks if the value of the field is LONG

`impl R<u8, I2SSTD_A>`[src]

`pub fn variant(&self) -> I2SSTD_A`[src]

Get enumerated values variant

`pub fn is_philips(&self) -> bool`[src]

Checks if the value of the field is PHILIPS

`pub fn is_msb(&self) -> bool`[src]

Checks if the value of the field is MSB

`pub fn is_lsb(&self) -> bool`[src]

Checks if the value of the field is LSB

`pub fn is_pcm(&self) -> bool`[src]

Checks if the value of the field is PCM

`impl R<bool, CKPOL_A>`[src]

`pub fn variant(&self) -> CKPOL_A`[src]

Get enumerated values variant

`pub fn is_idle_low(&self) -> bool`[src]

Checks if the value of the field is IDLELOW

`pub fn is_idle_high(&self) -> bool`[src]

Checks if the value of the field is IDLEHIGH

`impl R<u8, DATLEN_A>`[src]

`pub fn variant(&self) -> Variant<u8, DATLEN_A>`[src]

Get enumerated values variant

`pub fn is_sixteen_bit(&self) -> bool`[src]

Checks if the value of the field is SIXTEENBIT

`pub fn is_twenty_four_bit(&self) -> bool`[src]

Checks if the value of the field is TWENTYFOURBIT

`pub fn is_thirty_two_bit(&self) -> bool`[src]

Checks if the value of the field is THIRTYTWOBIT

`impl R<bool, CHLEN_A>`[src]

`pub fn variant(&self) -> CHLEN_A`[src]

Get enumerated values variant

`pub fn is_sixteen_bit(&self) -> bool`[src]

Checks if the value of the field is SIXTEENBIT

`pub fn is_thirty_two_bit(&self) -> bool`[src]

Checks if the value of the field is THIRTYTWOBIT

`impl R<u32, Reg<u32, _I2SCFGR>>`[src]

`pub fn i2smod(&self) -> I2SMOD_R`[src]

Bit 11 - I2S mode selection

`pub fn i2se(&self) -> I2SE_R`[src]

Bit 10 - I2S Enable

`pub fn i2scfg(&self) -> I2SCFG_R`[src]

Bits 8:9 - I2S configuration mode

`pub fn pcmsync(&self) -> PCMSYNC_R`[src]

Bit 7 - PCM frame synchronization

`pub fn i2sstd(&self) -> I2SSTD_R`[src]

Bits 4:5 - I2S standard selection

`pub fn ckpol(&self) -> CKPOL_R`[src]

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn ovr(&self) -> OVR_R`[src]

Bit 5 - Overrun

`pub fn strt(&self) -> STRT_R`[src]

Bit 4 - Regular channel start flag

`pub fn jstrt(&self) -> JSTRT_R`[src]

Bit 3 - Injected channel start flag

`pub fn jeoc(&self) -> JEOC_R`[src]

Bit 2 - Injected channel end of conversion

`pub fn eoc(&self) -> EOC_R`[src]

Bit 1 - Regular channel end of conversion

`pub fn awd(&self) -> AWD_R`[src]

Bit 0 - Analog watchdog flag

`impl R<bool, OVRIE_A>`[src]

`pub fn variant(&self) -> OVRIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, RES_A>`[src]

`pub fn variant(&self) -> RES_A`[src]

Get enumerated values variant

`pub fn is_twelve_bit(&self) -> bool`[src]

`pub fn jawden(&self) -> JAWDEN_R`[src]

Bit 22 - Analog watchdog enable on injected channels

`pub fn discnum(&self) -> DISCNUM_R`[src]

Bits 13:15 - Discontinuous mode channel count

`pub fn jdiscen(&self) -> JDISCEN_R`[src]

Bit 12 - Discontinuous mode on injected channels

`pub fn discen(&self) -> DISCEN_R`[src]

Bit 11 - Discontinuous mode on regular channels

`pub fn jauto(&self) -> JAUTO_R`[src]

Bit 10 - Automatic injected group conversion

`pub fn awdsgl(&self) -> AWDSGL_R`[src]

Bit 9 - Enable the watchdog on a single channel in scan mode

`pub fn scan(&self) -> SCAN_R`[src]

Bit 8 - Scan mode

`pub fn jeocie(&self) -> JEOCIE_R`[src]

Bit 7 - Interrupt enable for injected channels

`pub fn awdie(&self) -> AWDIE_R`[src]

Bit 6 - Analog watchdog interrupt enable

`pub fn eocie(&self) -> EOCIE_R`[src]

Bit 5 - Interrupt enable for EOC

`pub fn awdch(&self) -> AWDCH_R`[src]

Bits 0:4 - Analog watchdog channel select bits

`impl R<bool, SWSTART_A>`[src]

`pub fn variant(&self) -> Variant<bool, SWSTART_A>`[src]

Get enumerated values variant

`pub fn is_start(&self) -> bool`[src]

Checks if the value of the field is START

`impl R<u8, EXTEN_A>`[src]

`pub fn variant(&self) -> EXTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_rising_edge(&self) -> bool`[src]

Checks if the value of the field is RISINGEDGE

`pub fn is_falling_edge(&self) -> bool`[src]

Checks if the value of the field is FALLINGEDGE

`pub fn is_both_edges(&self) -> bool`[src]

Checks if the value of the field is BOTHEDGES

`impl R<u8, EXTSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, EXTSEL_A>`[src]

Get enumerated values variant

`pub fn is_tim1cc1(&self) -> bool`[src]

Checks if the value of the field is TIM1CC1

`pub fn is_tim1cc2(&self) -> bool`[src]

Checks if the value of the field is TIM1CC2

`pub fn is_tim1cc3(&self) -> bool`[src]

Checks if the value of the field is TIM1CC3

`pub fn is_tim2cc2(&self) -> bool`[src]

Checks if the value of the field is TIM2CC2

`pub fn is_tim2cc3(&self) -> bool`[src]

Checks if the value of the field is TIM2CC3

`pub fn is_tim2cc4(&self) -> bool`[src]

Checks if the value of the field is TIM2CC4

`pub fn is_tim2trgo(&self) -> bool`[src]

Checks if the value of the field is TIM2TRGO

`impl R<bool, JSWSTART_A>`[src]

`pub fn variant(&self) -> Variant<bool, JSWSTART_A>`[src]

Get enumerated values variant

`pub fn is_start(&self) -> bool`[src]

Checks if the value of the field is START

`impl R<u8, JEXTEN_A>`[src]

`pub fn variant(&self) -> JEXTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_rising_edge(&self) -> bool`[src]

Checks if the value of the field is RISINGEDGE

`pub fn is_falling_edge(&self) -> bool`[src]

Checks if the value of the field is FALLINGEDGE

`pub fn is_both_edges(&self) -> bool`[src]

Checks if the value of the field is BOTHEDGES

`impl R<u8, JEXTSEL_A>`[src]

`pub fn variant(&self) -> Variant<u8, JEXTSEL_A>`[src]

Get enumerated values variant

`pub fn is_tim1trgo(&self) -> bool`[src]

Checks if the value of the field is TIM1TRGO

`pub fn is_tim1cc4(&self) -> bool`[src]

Checks if the value of the field is TIM1CC4

`pub fn is_tim2trgo(&self) -> bool`[src]

Checks if the value of the field is TIM2TRGO

`pub fn is_tim2cc1(&self) -> bool`[src]

Checks if the value of the field is TIM2CC1

`pub fn is_tim3cc4(&self) -> bool`[src]

Checks if the value of the field is TIM3CC4

`pub fn is_tim4trgo(&self) -> bool`[src]

Checks if the value of the field is TIM4TRGO

`pub fn is_tim8cc4(&self) -> bool`[src]

Checks if the value of the field is TIM8CC4

`pub fn is_tim1trgo2(&self) -> bool`[src]

Checks if the value of the field is TIM1TRGO2

`pub fn is_tim8trgo(&self) -> bool`[src]

Checks if the value of the field is TIM8TRGO

`pub fn is_tim8trgo2(&self) -> bool`[src]

Checks if the value of the field is TIM8TRGO2

`pub fn is_tim3cc3(&self) -> bool`[src]

`pub fn jswstart(&self) -> JSWSTART_R`[src]

Bit 22 - Start conversion of injected channels

`pub fn jexten(&self) -> JEXTEN_R`[src]

Bits 20:21 - External trigger enable for injected channels

`pub fn jextsel(&self) -> JEXTSEL_R`[src]

Bits 16:19 - External event select for injected group

`pub fn align(&self) -> ALIGN_R`[src]

Bit 11 - Data alignment

`pub fn eocs(&self) -> EOCS_R`[src]

Bit 10 - End of conversion selection

`pub fn dds(&self) -> DDS_R`[src]

Bit 9 - DMA disable selection (for single ADC mode)

`pub fn dma(&self) -> DMA_R`[src]

Bit 8 - Direct memory access mode (for single ADC mode)

`pub fn cont(&self) -> CONT_R`[src]

Bit 1 - Continuous conversion

`pub fn adon(&self) -> ADON_R`[src]

Bit 0 - A/D Converter ON / OFF

`impl R<u32, SMPX_X_A>`[src]

`pub fn variant(&self) -> Variant<u32, SMPX_X_A>`[src]

Get enumerated values variant

`pub fn is_cycles3(&self) -> bool`[src]

Checks if the value of the field is CYCLES3

`pub fn is_cycles15(&self) -> bool`[src]

Checks if the value of the field is CYCLES15

`pub fn is_cycles28(&self) -> bool`[src]

Checks if the value of the field is CYCLES28

`pub fn is_cycles56(&self) -> bool`[src]

Checks if the value of the field is CYCLES56

`pub fn is_cycles84(&self) -> bool`[src]

Checks if the value of the field is CYCLES84

`pub fn is_cycles112(&self) -> bool`[src]

Checks if the value of the field is CYCLES112

`pub fn is_cycles144(&self) -> bool`[src]

Checks if the value of the field is CYCLES144

`pub fn is_cycles480(&self) -> bool`[src]

Checks if the value of the field is CYCLES480

`impl R<u32, Reg<u32, _SMPR1>>`[src]

`pub fn smpx_x(&self) -> SMPX_X_R`[src]

Bits 0:31 - Sample time bits

`impl R<u32, SMPX_X_A>`[src]

`pub fn variant(&self) -> Variant<u32, SMPX_X_A>`[src]

Get enumerated values variant

`pub fn is_cycles3(&self) -> bool`[src]

Checks if the value of the field is CYCLES3

`pub fn is_cycles15(&self) -> bool`[src]

Checks if the value of the field is CYCLES15

`pub fn is_cycles28(&self) -> bool`[src]

Checks if the value of the field is CYCLES28

`pub fn is_cycles56(&self) -> bool`[src]

Checks if the value of the field is CYCLES56

`pub fn is_cycles84(&self) -> bool`[src]

Checks if the value of the field is CYCLES84

`pub fn is_cycles112(&self) -> bool`[src]

Checks if the value of the field is CYCLES112

`pub fn is_cycles144(&self) -> bool`[src]

Checks if the value of the field is CYCLES144

`pub fn is_cycles480(&self) -> bool`[src]

Checks if the value of the field is CYCLES480

`impl R<u32, Reg<u32, _SMPR2>>`[src]

`pub fn smpx_x(&self) -> SMPX_X_R`[src]

Bits 0:31 - Sample time bits

`impl R<u32, Reg<u32, _JOFR>>`[src]

`pub fn joffset(&self) -> JOFFSET_R`[src]

Bits 0:11 - Data offset for injected channel x

`impl R<u32, Reg<u32, _HTR>>`[src]

`pub fn ht(&self) -> HT_R`[src]

Bits 0:11 - Analog watchdog higher threshold

`impl R<u32, Reg<u32, _LTR>>`[src]

`pub fn lt(&self) -> LT_R`[src]

Bits 0:11 - Analog watchdog lower threshold

`impl R<u32, Reg<u32, _SQR1>>`[src]

`pub fn l(&self) -> L_R`[src]

Bits 20:23 - Regular channel sequence length

`pub fn sq16(&self) -> SQ16_R`[src]

Bits 15:19 - 16th conversion in regular sequence

`pub fn sq15(&self) -> SQ15_R`[src]

Bits 10:14 - 15th conversion in regular sequence

`pub fn sq14(&self) -> SQ14_R`[src]

Bits 5:9 - 14th conversion in regular sequence

`pub fn sq13(&self) -> SQ13_R`[src]

Bits 0:4 - 13th conversion in regular sequence

`impl R<u32, Reg<u32, _SQR2>>`[src]

`pub fn sq12(&self) -> SQ12_R`[src]

Bits 25:29 - 12th conversion in regular sequence

`pub fn sq11(&self) -> SQ11_R`[src]

Bits 20:24 - 11th conversion in regular sequence

`pub fn sq10(&self) -> SQ10_R`[src]

Bits 15:19 - 10th conversion in regular sequence

`pub fn sq9(&self) -> SQ9_R`[src]

Bits 10:14 - 9th conversion in regular sequence

`pub fn sq8(&self) -> SQ8_R`[src]

Bits 5:9 - 8th conversion in regular sequence

`pub fn sq7(&self) -> SQ7_R`[src]

Bits 0:4 - 7th conversion in regular sequence

`impl R<u32, Reg<u32, _SQR3>>`[src]

`pub fn sq6(&self) -> SQ6_R`[src]

Bits 25:29 - 6th conversion in regular sequence

`pub fn sq5(&self) -> SQ5_R`[src]

Bits 20:24 - 5th conversion in regular sequence

`pub fn sq4(&self) -> SQ4_R`[src]

Bits 15:19 - 4th conversion in regular sequence

`pub fn sq3(&self) -> SQ3_R`[src]

Bits 10:14 - 3rd conversion in regular sequence

`pub fn sq2(&self) -> SQ2_R`[src]

Bits 5:9 - 2nd conversion in regular sequence

`pub fn sq1(&self) -> SQ1_R`[src]

Bits 0:4 - 1st conversion in regular sequence

`impl R<u32, Reg<u32, _JSQR>>`[src]

`pub fn jl(&self) -> JL_R`[src]

Bits 20:21 - Injected sequence length

`pub fn jsq4(&self) -> JSQ4_R`[src]

Bits 15:19 - 4th conversion in injected sequence

`pub fn jsq3(&self) -> JSQ3_R`[src]

Bits 10:14 - 3rd conversion in injected sequence

`pub fn jsq2(&self) -> JSQ2_R`[src]

Bits 5:9 - 2nd conversion in injected sequence

`pub fn jsq1(&self) -> JSQ1_R`[src]

Bits 0:4 - 1st conversion in injected sequence

`impl R<u32, Reg<u32, _JDR>>`[src]

`pub fn jdata(&self) -> JDATA_R`[src]

Bits 0:15 - Injected data

Checks if the value of the field is DISABLED

`pub fn is_noise(&self) -> bool`[src]

Checks if the value of the field is NOISE

`pub fn is_triangle(&self) -> bool`[src]

Checks if the value of the field is TRIANGLE

`impl R<u8, TSEL2_A>`[src]

`pub fn variant(&self) -> TSEL2_A`[src]

Get enumerated values variant

`pub fn is_tim6_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM6_TRGO

`pub fn is_tim8_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM8_TRGO

`pub fn is_tim7_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM7_TRGO

`pub fn is_tim5_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM5_TRGO

`pub fn is_tim2_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM2_TRGO

`pub fn is_tim4_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM4_TRGO

`pub fn is_exti9(&self) -> bool`[src]

Checks if the value of the field is EXTI9

`pub fn is_software(&self) -> bool`[src]

Checks if the value of the field is SOFTWARE

`impl R<bool, TEN2_A>`[src]

`pub fn variant(&self) -> TEN2_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, BOFF2_A>`[src]

`pub fn variant(&self) -> BOFF2_A`[src]

Get enumerated values variant

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`impl R<bool, EN2_A>`[src]

`pub fn variant(&self) -> EN2_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, WAVE1_A>`[src]

`pub fn variant(&self) -> Variant<u8, WAVE1_A>`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_noise(&self) -> bool`[src]

Checks if the value of the field is NOISE

`pub fn is_triangle(&self) -> bool`[src]

Checks if the value of the field is TRIANGLE

`impl R<u8, TSEL1_A>`[src]

`pub fn variant(&self) -> Variant<u8, TSEL1_A>`[src]

Get enumerated values variant

`pub fn is_tim6_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM6_TRGO

`pub fn is_tim3_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM3_TRGO

`pub fn is_tim7_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM7_TRGO

`pub fn is_tim15_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM15_TRGO

`pub fn is_tim2_trgo(&self) -> bool`[src]

Checks if the value of the field is TIM2_TRGO

`pub fn is_exti9(&self) -> bool`[src]

Checks if the value of the field is EXTI9

`pub fn is_software(&self) -> bool`[src]

Checks if the value of the field is SOFTWARE

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn dmaudrie2(&self) -> DMAUDRIE2_R`[src]

Bit 29 - DAC channel2 DMA underrun interrupt enable

`pub fn dmaen2(&self) -> DMAEN2_R`[src]

Bit 28 - DAC channel2 DMA enable

`pub fn mamp2(&self) -> MAMP2_R`[src]

Bits 24:27 - DAC channel2 mask/amplitude selector

`pub fn wave2(&self) -> WAVE2_R`[src]

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

`pub fn tsel2(&self) -> TSEL2_R`[src]

Bits 19:21 - DAC channel2 trigger selection

`pub fn ten2(&self) -> TEN2_R`[src]

Bit 18 - DAC channel2 trigger enable

`pub fn boff2(&self) -> BOFF2_R`[src]

Bit 17 - DAC channel2 output buffer disable

`pub fn en2(&self) -> EN2_R`[src]

Bit 16 - DAC channel2 enable

`pub fn dmaudrie1(&self) -> DMAUDRIE1_R`[src]

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

`pub fn dmaen1(&self) -> DMAEN1_R`[src]

Bit 12 - DAC channel1 DMA enable

`pub fn mamp1(&self) -> MAMP1_R`[src]

Bits 8:11 - DAC channel1 mask/amplitude selector

`pub fn wave1(&self) -> WAVE1_R`[src]

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

`pub fn tsel1(&self) -> TSEL1_R`[src]

Bits 3:5 - DAC channel1 trigger selection

`pub fn ten1(&self) -> TEN1_R`[src]

Bit 2 - DAC channel1 trigger enable

`pub fn boff1(&self) -> BOFF1_R`[src]

Bit 1 - DAC channel1 output buffer disable

`pub fn en1(&self) -> EN1_R`[src]

Bit 0 - DAC channel1 enable

`impl R<u32, Reg<u32, _DHR12R1>>`[src]

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

`impl R<u32, Reg<u32, _DHR12L1>>`[src]

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

`impl R<u32, Reg<u32, _DHR8R1>>`[src]

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

`impl R<u32, Reg<u32, _DHR12R2>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 0:11 - DAC channel2 12-bit right-aligned data

`impl R<u32, Reg<u32, _DHR12L2>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 4:15 - DAC channel2 12-bit left-aligned data

`impl R<u32, Reg<u32, _DHR8R2>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 0:7 - DAC channel2 8-bit right-aligned data

`impl R<u32, Reg<u32, _DHR12RD>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 16:27 - DAC channel2 12-bit right-aligned data

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

`impl R<u32, Reg<u32, _DHR12LD>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 20:31 - DAC channel2 12-bit left-aligned data

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

`impl R<u32, Reg<u32, _DHR8RD>>`[src]

`pub fn dacc2dhr(&self) -> DACC2DHR_R`[src]

Bits 8:15 - DAC channel2 8-bit right-aligned data

`pub fn dacc1dhr(&self) -> DACC1DHR_R`[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

`impl R<u32, Reg<u32, _DOR1>>`[src]

`pub fn dacc1dor(&self) -> DACC1DOR_R`[src]

Bits 0:11 - DAC channel1 data output

`impl R<u32, Reg<u32, _DOR2>>`[src]

`pub fn dacc2dor(&self) -> DACC2DOR_R`[src]

Bits 0:11 - DAC channel2 data output

`impl R<bool, DMAUDR2_A>`[src]

`pub fn variant(&self) -> DMAUDR2_A`[src]

Get enumerated values variant

`pub fn is_no_underrun(&self) -> bool`[src]

Checks if the value of the field is NOUNDERRUN

`pub fn is_underrun(&self) -> bool`[src]

Checks if the value of the field is UNDERRUN

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn dmaudr2(&self) -> DMAUDR2_R`[src]

Bit 29 - DAC channel2 DMA underrun flag

`pub fn dmaudr1(&self) -> DMAUDR1_R`[src]

Bit 13 - DAC channel1 DMA underrun flag

`impl R<bool, PDDS_A>`[src]

`pub fn variant(&self) -> PDDS_A`[src]

Get enumerated values variant

`pub fn is_stop_mode(&self) -> bool`[src]

Checks if the value of the field is STOP_MODE

`pub fn is_standby_mode(&self) -> bool`[src]

Checks if the value of the field is STANDBY_MODE

`impl R<u8, VOS_A>`[src]

`pub fn variant(&self) -> Variant<u8, VOS_A>`[src]

Get enumerated values variant

`pub fn is_scale1(&self) -> bool`[src]

Checks if the value of the field is SCALE1

`pub fn is_scale2(&self) -> bool`[src]

Checks if the value of the field is SCALE2

`pub fn is_scale3(&self) -> bool`[src]

Checks if the value of the field is SCALE3

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn lpds(&self) -> LPDS_R`[src]

Bit 0 - Low-power deep sleep

`pub fn pdds(&self) -> PDDS_R`[src]

Bit 1 - Power down deepsleep

`pub fn csbf(&self) -> CSBF_R`[src]

Bit 3 - Clear standby flag

`pub fn pvde(&self) -> PVDE_R`[src]

Bit 4 - Power voltage detector enable

`pub fn pls(&self) -> PLS_R`[src]

Bits 5:7 - PVD level selection

`pub fn dbp(&self) -> DBP_R`[src]

Bit 8 - Disable backup domain write protection

`pub fn fpds(&self) -> FPDS_R`[src]

Bit 9 - Flash power down in Stop mode

`pub fn lpuds(&self) -> LPUDS_R`[src]

Bit 10 - Low-power regulator in deepsleep under-drive mode

`pub fn mruds(&self) -> MRUDS_R`[src]

Bit 11 - Main regulator in deepsleep under-drive mode

`pub fn adcdc1(&self) -> ADCDC1_R`[src]

Bit 13 - ADCDC1

`pub fn vos(&self) -> VOS_R`[src]

Bits 14:15 - Regulator voltage scaling output selection

`pub fn oden(&self) -> ODEN_R`[src]

Bit 16 - Over-drive enable

`pub fn odswen(&self) -> ODSWEN_R`[src]

Bit 17 - Over-drive switching enabled

`pub fn uden(&self) -> UDEN_R`[src]

Bits 18:19 - Under-drive enable in stop mode

`impl R<u32, Reg<u32, _CSR1>>`[src]

`pub fn wuif(&self) -> WUIF_R`[src]

Bit 0 - Wakeup internal flag

`pub fn sbf(&self) -> SBF_R`[src]

Bit 1 - Standby flag

`pub fn pvdo(&self) -> PVDO_R`[src]

Bit 2 - PVD output

`pub fn brr(&self) -> BRR_R`[src]

Bit 3 - Backup regulator ready

`pub fn bre(&self) -> BRE_R`[src]

Bit 9 - Backup regulator enable

`pub fn vosrdy(&self) -> VOSRDY_R`[src]

Bit 14 - Regulator voltage scaling output selection ready bit

`pub fn odrdy(&self) -> ODRDY_R`[src]

Bit 16 - Over-drive mode ready

`pub fn odswrdy(&self) -> ODSWRDY_R`[src]

Bit 17 - Over-drive mode switching ready

`pub fn udrdy(&self) -> UDRDY_R`[src]

Bits 18:19 - Under-drive ready flag

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn cwupf1(&self) -> CWUPF1_R`[src]

Bit 0 - Clear Wakeup Pin flag for PA0

`pub fn cwupf2(&self) -> CWUPF2_R`[src]

Bit 1 - Clear Wakeup Pin flag for PA2

`pub fn cwupf3(&self) -> CWUPF3_R`[src]

Bit 2 - Clear Wakeup Pin flag for PC1

`pub fn cwupf4(&self) -> CWUPF4_R`[src]

Bit 3 - Clear Wakeup Pin flag for PC13

`pub fn cwupf5(&self) -> CWUPF5_R`[src]

Bit 4 - Clear Wakeup Pin flag for PI8

`pub fn cwupf6(&self) -> CWUPF6_R`[src]

Bit 5 - Clear Wakeup Pin flag for PI11

`pub fn wupp1(&self) -> WUPP1_R`[src]

Bit 8 - Wakeup pin polarity bit for PA0

`pub fn wupp2(&self) -> WUPP2_R`[src]

Bit 9 - Wakeup pin polarity bit for PA2

`pub fn wupp3(&self) -> WUPP3_R`[src]

Bit 10 - Wakeup pin polarity bit for PC1

`pub fn wupp4(&self) -> WUPP4_R`[src]

Bit 11 - Wakeup pin polarity bit for PC13

`pub fn wupp5(&self) -> WUPP5_R`[src]

Bit 12 - Wakeup pin polarity bit for PI8

`pub fn wupp6(&self) -> WUPP6_R`[src]

Bit 13 - Wakeup pin polarity bit for PI11

`impl R<u32, Reg<u32, _CSR2>>`[src]

`pub fn wupf1(&self) -> WUPF1_R`[src]

Bit 0 - Wakeup Pin flag for PA0

`pub fn wupf2(&self) -> WUPF2_R`[src]

Bit 1 - Wakeup Pin flag for PA2

`pub fn wupf3(&self) -> WUPF3_R`[src]

Bit 2 - Wakeup Pin flag for PC1

`pub fn wupf4(&self) -> WUPF4_R`[src]

Bit 3 - Wakeup Pin flag for PC13

`pub fn wupf5(&self) -> WUPF5_R`[src]

Bit 4 - Wakeup Pin flag for PI8

`pub fn wupf6(&self) -> WUPF6_R`[src]

Bit 5 - Wakeup Pin flag for PI11

`pub fn ewup1(&self) -> EWUP1_R`[src]

Bit 8 - Enable Wakeup pin for PA0

`pub fn ewup2(&self) -> EWUP2_R`[src]

Bit 9 - Enable Wakeup pin for PA2

`pub fn ewup3(&self) -> EWUP3_R`[src]

Bit 10 - Enable Wakeup pin for PC1

`pub fn ewup4(&self) -> EWUP4_R`[src]

Bit 11 - Enable Wakeup pin for PC13

`pub fn ewup5(&self) -> EWUP5_R`[src]

Bit 12 - Enable Wakeup pin for PI8

`pub fn ewup6(&self) -> EWUP6_R`[src]

Bit 13 - Enable Wakeup pin for PI11

`impl R<u8, PR_A>`[src]

`pub fn variant(&self) -> PR_A`[src]

Get enumerated values variant

`pub fn is_divide_by4(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY4

`pub fn is_divide_by8(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY8

`pub fn is_divide_by16(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY16

`pub fn is_divide_by32(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY32

`pub fn is_divide_by64(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY64

`pub fn is_divide_by128(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY128

`pub fn is_divide_by256(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY256

`pub fn is_divide_by256bis(&self) -> bool`[src]

Checks if the value of the field is DIVIDEBY256BIS

`impl R<u32, Reg<u32, _PR>>`[src]

`pub fn pr(&self) -> PR_R`[src]

Bits 0:2 - Prescaler divider

`impl R<u32, Reg<u32, _RLR>>`[src]

`pub fn rl(&self) -> RL_R`[src]

Bits 0:11 - Watchdog counter reload value

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn rvu(&self) -> RVU_R`[src]

Bit 1 - Watchdog counter reload value update

`pub fn pvu(&self) -> PVU_R`[src]

Bit 0 - Watchdog prescaler value update

`impl R<u32, Reg<u32, _WINR>>`[src]

`pub fn win(&self) -> WIN_R`[src]

Bits 0:11 - Watchdog counter window value

`impl R<bool, WDGA_A>`[src]

`pub fn variant(&self) -> WDGA_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn wdga(&self) -> WDGA_R`[src]

Bit 7 - Activation bit

`pub fn t(&self) -> T_R`[src]

Bits 0:6 - 7-bit counter (MSB to LSB)

`impl R<bool, EWI_A>`[src]

`pub fn variant(&self) -> Variant<bool, EWI_A>`[src]

Get enumerated values variant

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`impl R<u8, WDGTB_A>`[src]

`pub fn variant(&self) -> WDGTB_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u32, Reg<u32, _CFR>>`[src]

`pub fn ewi(&self) -> EWI_R`[src]

Bit 9 - Early wakeup interrupt

`pub fn w(&self) -> W_R`[src]

Bits 0:6 - 7-bit window value

`pub fn wdgtb(&self) -> WDGTB_R`[src]

Bits 7:8 - Timer base

`impl R<bool, EWIF_A>`[src]

`pub fn variant(&self) -> EWIF_A`[src]

Get enumerated values variant

`pub fn is_pending(&self) -> bool`[src]

Checks if the value of the field is PENDING

`pub fn is_finished(&self) -> bool`[src]

Checks if the value of the field is FINISHED

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn ewif(&self) -> EWIF_R`[src]

Bit 0 - Early wakeup interrupt flag

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn arpe(&self) -> ARPE_R`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&self) -> CMS_R`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&self) -> DIR_R`[src]

Bit 4 - Direction

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`impl R<bool, TI1S_A>`[src]

`pub fn variant(&self) -> TI1S_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_xor(&self) -> bool`[src]

Checks if the value of the field is XOR

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> MMS_A`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`pub fn is_update(&self) -> bool`[src]

Checks if the value of the field is UPDATE

`pub fn is_compare_pulse(&self) -> bool`[src]

Checks if the value of the field is COMPAREPULSE

`pub fn is_compare_oc1(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC1

`pub fn is_compare_oc2(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC2

`pub fn is_compare_oc3(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC3

`pub fn is_compare_oc4(&self) -> bool`[src]

Checks if the value of the field is COMPAREOC4

`impl R<bool, CCDS_A>`[src]

`pub fn variant(&self) -> CCDS_A`[src]

Get enumerated values variant

`pub fn is_on_compare(&self) -> bool`[src]

Checks if the value of the field is ONCOMPARE

`pub fn is_on_update(&self) -> bool`[src]

Checks if the value of the field is ONUPDATE

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn ois4(&self) -> OIS4_R`[src]

Bit 14 - Output Idle state 4

`pub fn ois3n(&self) -> OIS3N_R`[src]

Bit 13 - Output Idle state 3

`pub fn ois3(&self) -> OIS3_R`[src]

Bit 12 - Output Idle state 3

`pub fn ois2n(&self) -> OIS2N_R`[src]

Bit 11 - Output Idle state 2

`pub fn ois2(&self) -> OIS2_R`[src]

Bit 10 - Output Idle state 2

`pub fn ois1n(&self) -> OIS1N_R`[src]

Bit 9 - Output Idle state 1

`pub fn ois1(&self) -> OIS1_R`[src]

Bit 8 - Output Idle state 1

`pub fn ti1s(&self) -> TI1S_R`[src]

Bit 7 - TI1 selection

`pub fn mms(&self) -> MMS_R`[src]

Bits 4:6 - Master mode selection

`pub fn ccds(&self) -> CCDS_R`[src]

Bit 3 - Capture/compare DMA selection

`pub fn ccus(&self) -> CCUS_R`[src]

Bit 2 - Capture/compare control update selection

`pub fn ccpc(&self) -> CCPC_R`[src]

Bit 0 - Capture/compare preloaded control

`impl R<bool, ETP_A>`[src]

`pub fn variant(&self) -> ETP_A`[src]

Get enumerated values variant

`pub fn is_not_inverted(&self) -> bool`[src]

Checks if the value of the field is NOTINVERTED

`pub fn is_inverted(&self) -> bool`[src]

Checks if the value of the field is INVERTED

`impl R<bool, ECE_A>`[src]

`pub fn variant(&self) -> ECE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, ETPS_A>`[src]

`pub fn variant(&self) -> ETPS_A`[src]

Get enumerated values variant

`pub fn is_div1(&self) -> bool`[src]

Checks if the value of the field is DIV1

`pub fn is_div2(&self) -> bool`[src]

Checks if the value of the field is DIV2

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u8, ETF_A>`[src]

`pub fn variant(&self) -> ETF_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<bool, MSM_A>`[src]

`pub fn variant(&self) -> MSM_A`[src]

Get enumerated values variant

`pub fn is_no_sync(&self) -> bool`[src]

Checks if the value of the field is NOSYNC

`pub fn is_sync(&self) -> bool`[src]

Checks if the value of the field is SYNC

`impl R<u8, TS_A>`[src]

`pub fn variant(&self) -> Variant<u8, TS_A>`[src]

Get enumerated values variant

`pub fn is_itr0(&self) -> bool`[src]

Checks if the value of the field is ITR0

`pub fn is_itr1(&self) -> bool`[src]

Checks if the value of the field is ITR1

`pub fn is_itr2(&self) -> bool`[src]

Checks if the value of the field is ITR2

`pub fn is_ti1f_ed(&self) -> bool`[src]

Checks if the value of the field is TI1F_ED

`pub fn is_ti1fp1(&self) -> bool`[src]

Checks if the value of the field is TI1FP1

`pub fn is_ti2fp2(&self) -> bool`[src]

Checks if the value of the field is TI2FP2

`pub fn is_etrf(&self) -> bool`[src]

Checks if the value of the field is ETRF

`impl R<u8, SMS_A>`[src]

`pub fn variant(&self) -> SMS_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_encoder_mode_1(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_1

`pub fn is_encoder_mode_2(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_2

`pub fn is_encoder_mode_3(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_3

`pub fn is_reset_mode(&self) -> bool`[src]

Checks if the value of the field is RESET_MODE

`pub fn is_gated_mode(&self) -> bool`[src]

Checks if the value of the field is GATED_MODE

`pub fn is_trigger_mode(&self) -> bool`[src]

Checks if the value of the field is TRIGGER_MODE

`pub fn is_ext_clock_mode(&self) -> bool`[src]

Checks if the value of the field is EXT_CLOCK_MODE

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn etp(&self) -> ETP_R`[src]

Bit 15 - External trigger polarity

`pub fn ece(&self) -> ECE_R`[src]

Bit 14 - External clock enable

`pub fn etps(&self) -> ETPS_R`[src]

Bits 12:13 - External trigger prescaler

`pub fn etf(&self) -> ETF_R`[src]

`pub fn cc3de(&self) -> CC3DE_R`[src]

Bit 11 - Capture/Compare 3 DMA request enable

`pub fn cc2de(&self) -> CC2DE_R`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&self) -> CC1DE_R`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&self) -> UDE_R`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&self) -> TIE_R`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&self) -> CC4IE_R`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&self) -> CC3IE_R`[src]

Bit 3 - Capture/Compare 3 interrupt enable

`pub fn cc2ie(&self) -> CC2IE_R`[src]

Bit 2 - Capture/Compare 2 interrupt enable

`pub fn cc1ie(&self) -> CC1IE_R`[src]

`pub fn cc2of(&self) -> CC2OF_R`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn bif(&self) -> BIF_R`[src]

Bit 7 - Break interrupt flag

`pub fn tif(&self) -> TIF_R`[src]

Bit 6 - Trigger interrupt flag

`pub fn comif(&self) -> COMIF_R`[src]

Bit 5 - COM interrupt flag

`pub fn cc4if(&self) -> CC4IF_R`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&self) -> CC3IF_R`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&self) -> CC2IF_R`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u8, OC2M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC2M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC2PE_A>`[src]

`pub fn variant(&self) -> OC2PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&self) -> OC2CE_R`[src]

Bit 15 - Output Compare 2 clear enable

`pub fn oc2m(&self) -> OC2M_R`[src]

Bits 12:14 - Output Compare 2 mode

`pub fn oc2pe(&self) -> OC2PE_R`[src]

Bit 11 - Output Compare 2 preload enable

`pub fn oc2fe(&self) -> OC2FE_R`[src]

Bit 10 - Output Compare 2 fast enable

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn oc1ce(&self) -> OC1CE_R`[src]

Bit 7 - Output Compare 1 clear enable

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - Output Compare 1 mode

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - Output Compare 1 preload enable

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - Output Compare 1 fast enable

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u8, CC2S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC2S_A>`[src]

Get enumerated values variant

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, IC1F_A>`[src]

`pub fn variant(&self) -> IC1F_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&self) -> IC2F_R`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&self) -> IC2PSC_R`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u8, OC4M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC4M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC4PE_A>`[src]

`pub fn variant(&self) -> OC4PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&self) -> OC4CE_R`[src]

Bit 15 - Output compare 4 clear enable

`pub fn oc4m(&self) -> OC4M_R`[src]

Bits 12:14 - Output compare 4 mode

`pub fn oc4pe(&self) -> OC4PE_R`[src]

Bit 11 - Output compare 4 preload enable

`pub fn oc4fe(&self) -> OC4FE_R`[src]

Bit 10 - Output compare 4 fast enable

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn oc3ce(&self) -> OC3CE_R`[src]

Bit 7 - Output compare 3 clear enable

`pub fn oc3m(&self) -> OC3M_R`[src]

Bits 4:6 - Output compare 3 mode

`pub fn oc3pe(&self) -> OC3PE_R`[src]

Bit 3 - Output compare 3 preload enable

`pub fn oc3fe(&self) -> OC3FE_R`[src]

Bit 2 - Output compare 3 fast enable

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - Capture/Compare 3 selection

`impl R<u8, CC4S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC4S_A>`[src]

Get enumerated values variant

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&self) -> IC4F_R`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&self) -> IC4PSC_R`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&self) -> IC3F_R`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&self) -> IC3PSC_R`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - Capture/compare 3 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4p(&self) -> CC4P_R`[src]

Bit 13 - Capture/Compare 3 output Polarity

`pub fn cc4e(&self) -> CC4E_R`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&self) -> CC3NP_R`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3ne(&self) -> CC3NE_R`[src]

Bit 10 - Capture/Compare 3 complementary output enable

`pub fn cc3p(&self) -> CC3P_R`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&self) -> CC3E_R`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&self) -> CC2NP_R`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2ne(&self) -> CC2NE_R`[src]

Bit 6 - Capture/Compare 2 complementary output enable

`pub fn cc2p(&self) -> CC2P_R`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&self) -> CC2E_R`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1ne(&self) -> CC1NE_R`[src]

Bit 2 - Capture/Compare 1 complementary output enable

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 1 value

`impl R<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&self) -> DBL_R`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&self) -> DBA_R`[src]

Bits 0:4 - DMA base address

`impl R<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&self) -> DMAB_R`[src]

Bits 0:15 - DMA register for burst accesses

`impl R<u32, Reg<u32, _RCR>>`[src]

`pub fn rep(&self) -> REP_R`[src]

Bits 0:7 - Repetition counter value

`impl R<bool, MOE_A>`[src]

`pub fn variant(&self) -> MOE_A`[src]

Get enumerated values variant

`pub fn is_disabled_idle(&self) -> bool`[src]

Checks if the value of the field is DISABLEDIDLE

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, OSSR_A>`[src]

`pub fn variant(&self) -> OSSR_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_idle_level(&self) -> bool`[src]

Checks if the value of the field is IDLELEVEL

`impl R<bool, OSSI_A>`[src]

`pub fn variant(&self) -> OSSI_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_idle_level(&self) -> bool`[src]

Checks if the value of the field is IDLELEVEL

`impl R<u32, Reg<u32, _BDTR>>`[src]

`pub fn moe(&self) -> MOE_R`[src]

Bit 15 - Main output enable

`pub fn aoe(&self) -> AOE_R`[src]

Bit 14 - Automatic output enable

`pub fn bkp(&self) -> BKP_R`[src]

Bit 13 - Break polarity

`pub fn bke(&self) -> BKE_R`[src]

Bit 12 - Break enable

`pub fn ossr(&self) -> OSSR_R`[src]

Bit 11 - Off-state selection for Run mode

`pub fn ossi(&self) -> OSSI_R`[src]

Bit 10 - Off-state selection for Idle mode

`pub fn lock(&self) -> LOCK_R`[src]

Bits 8:9 - Lock configuration

`pub fn dtg(&self) -> DTG_R`[src]

Bits 0:7 - Dead-time generator setup

`impl R<u32, Reg<u32, _CCMR3_OUTPUT>>`[src]

`pub fn oc5fe(&self) -> OC5FE_R`[src]

Bit 2 - Output compare 5 fast enable

`pub fn oc5pe(&self) -> OC5PE_R`[src]

Bit 3 - Output compare 5 preload enable

`pub fn oc5m(&self) -> OC5M_R`[src]

Bits 4:6 - Output compare 5 mode

`pub fn oc5ce(&self) -> OC5CE_R`[src]

Bit 7 - Output compare 5 clear enable

`pub fn oc6fe(&self) -> OC6FE_R`[src]

Bit 10 - Output compare 6 fast enable

`pub fn oc6pe(&self) -> OC6PE_R`[src]

Bit 11 - Output compare 6 preload enable

`pub fn oc6m(&self) -> OC6M_R`[src]

Bits 12:14 - Output compare 6 mode

`pub fn oc6ce(&self) -> OC6CE_R`[src]

Bit 15 - Output compare 6 clear enable

`pub fn oc5m3(&self) -> OC5M3_R`[src]

Bit 16 - Output Compare 5 mode

`pub fn oc6m3(&self) -> OC6M3_R`[src]

Bit 24 - Output Compare 6 mode

`impl R<u32, Reg<u32, _CCR5>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 5 value

`pub fn gc5c1(&self) -> GC5C1_R`[src]

Bit 29 - Group Channel 5 and Channel 1

`pub fn gc5c2(&self) -> GC5C2_R`[src]

Bit 30 - Group Channel 5 and Channel 2

`pub fn gc5c3(&self) -> GC5C3_R`[src]

Bit 31 - Group Channel 5 and Channel 3

`impl R<u32, Reg<u32, _CRR6>>`[src]

`pub fn ccr6(&self) -> CCR6_R`[src]

Bits 0:15 - Capture/Compare 6 value

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn arpe(&self) -> ARPE_R`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&self) -> CMS_R`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&self) -> DIR_R`[src]

Bit 4 - Direction

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`impl R<bool, TI1S_A>`[src]

`pub fn variant(&self) -> TI1S_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_xor(&self) -> bool`[src]

Checks if the value of the field is XOR

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> MMS_A`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`pub fn is_update(&self) -> bool`[src]

Checks if the value of the field is UPDATE

`pub fn is_compare_pulse(&self) -> bool`[src]

Checks if the value of the field is COMPAREPULSE

`pub fn is_compare_oc1(&self) -> bool`[src]

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u8, ETF_A>`[src]

`pub fn variant(&self) -> ETF_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<bool, MSM_A>`[src]

`pub fn variant(&self) -> MSM_A`[src]

Get enumerated values variant

`pub fn is_no_sync(&self) -> bool`[src]

Checks if the value of the field is NOSYNC

`pub fn is_sync(&self) -> bool`[src]

Checks if the value of the field is SYNC

`impl R<u8, TS_A>`[src]

`pub fn variant(&self) -> Variant<u8, TS_A>`[src]

Get enumerated values variant

`pub fn is_itr0(&self) -> bool`[src]

Checks if the value of the field is ITR0

`pub fn is_itr1(&self) -> bool`[src]

Checks if the value of the field is ITR1

`pub fn is_itr2(&self) -> bool`[src]

Checks if the value of the field is ITR2

`pub fn is_ti1f_ed(&self) -> bool`[src]

Checks if the value of the field is TI1F_ED

`pub fn is_ti1fp1(&self) -> bool`[src]

Checks if the value of the field is TI1FP1

`pub fn is_ti2fp2(&self) -> bool`[src]

Checks if the value of the field is TI2FP2

`pub fn is_etrf(&self) -> bool`[src]

Checks if the value of the field is ETRF

`impl R<u8, SMS_A>`[src]

`pub fn variant(&self) -> SMS_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_encoder_mode_1(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_1

`pub fn is_encoder_mode_2(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_2

`pub fn is_encoder_mode_3(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_3

`pub fn is_reset_mode(&self) -> bool`[src]

Checks if the value of the field is RESET_MODE

`pub fn is_gated_mode(&self) -> bool`[src]

Checks if the value of the field is GATED_MODE

`pub fn is_trigger_mode(&self) -> bool`[src]

Checks if the value of the field is TRIGGER_MODE

`pub fn is_ext_clock_mode(&self) -> bool`[src]

Checks if the value of the field is EXT_CLOCK_MODE

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn etp(&self) -> ETP_R`[src]

Bit 15 - External trigger polarity

`pub fn ece(&self) -> ECE_R`[src]

Bit 14 - External clock enable

`pub fn etps(&self) -> ETPS_R`[src]

Bits 12:13 - External trigger prescaler

`pub fn etf(&self) -> ETF_R`[src]

`pub fn cc2de(&self) -> CC2DE_R`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&self) -> CC1DE_R`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&self) -> UDE_R`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&self) -> TIE_R`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&self) -> CC4IE_R`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&self) -> CC3IE_R`[src]

`pub fn cc2of(&self) -> CC2OF_R`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn tif(&self) -> TIF_R`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc4if(&self) -> CC4IF_R`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&self) -> CC3IF_R`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&self) -> CC2IF_R`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u8, OC2M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC2M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC2PE_A>`[src]

`pub fn variant(&self) -> OC2PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&self) -> OC2CE_R`[src]

Bit 15 - OC2CE

`pub fn oc2m(&self) -> OC2M_R`[src]

Bits 12:14 - OC2M

`pub fn oc2pe(&self) -> OC2PE_R`[src]

Bit 11 - OC2PE

`pub fn oc2fe(&self) -> OC2FE_R`[src]

Bit 10 - OC2FE

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - CC2S

`pub fn oc1ce(&self) -> OC1CE_R`[src]

Bit 7 - OC1CE

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - OC1M

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - OC1PE

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - OC1FE

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - CC1S

`impl R<u8, CC2S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC2S_A>`[src]

Get enumerated values variant

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, IC1F_A>`[src]

`pub fn variant(&self) -> IC1F_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&self) -> IC2F_R`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&self) -> IC2PSC_R`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u8, OC4M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC4M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC4PE_A>`[src]

`pub fn variant(&self) -> OC4PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&self) -> OC4CE_R`[src]

Bit 15 - O24CE

`pub fn oc4m(&self) -> OC4M_R`[src]

Bits 12:14 - OC4M

`pub fn oc4pe(&self) -> OC4PE_R`[src]

Bit 11 - OC4PE

`pub fn oc4fe(&self) -> OC4FE_R`[src]

Bit 10 - OC4FE

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - CC4S

`pub fn oc3ce(&self) -> OC3CE_R`[src]

Bit 7 - OC3CE

`pub fn oc3m(&self) -> OC3M_R`[src]

Bits 4:6 - OC3M

`pub fn oc3pe(&self) -> OC3PE_R`[src]

Bit 3 - OC3PE

`pub fn oc3fe(&self) -> OC3FE_R`[src]

Bit 2 - OC3FE

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - CC3S

`impl R<u8, CC4S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC4S_A>`[src]

Get enumerated values variant

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&self) -> IC4F_R`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&self) -> IC4PSC_R`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&self) -> IC3F_R`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&self) -> IC3PSC_R`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - Capture/compare 3 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4np(&self) -> CC4NP_R`[src]

Bit 15 - Capture/Compare 4 output Polarity

`pub fn cc4p(&self) -> CC4P_R`[src]

Bit 13 - Capture/Compare 3 output Polarity

`pub fn cc4e(&self) -> CC4E_R`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&self) -> CC3NP_R`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3p(&self) -> CC3P_R`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&self) -> CC3E_R`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&self) -> CC2NP_R`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&self) -> CC2P_R`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&self) -> CC2E_R`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:31 - Counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:31 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:31 - Capture/Compare 1 value

`impl R<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&self) -> DBL_R`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&self) -> DBA_R`[src]

Bits 0:4 - DMA base address

`impl R<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&self) -> DMAB_R`[src]

Bits 0:15 - DMA register for burst accesses

`impl R<u32, Reg<u32, _OR1>>`[src]

`pub fn ti4_rmp(&self) -> TI4_RMP_R`[src]

Bits 2:3 - Input Capture 4 remap

`pub fn etr1_rmp(&self) -> ETR1_RMP_R`[src]

Bit 1 - External trigger remap

`pub fn itr1_rmp(&self) -> ITR1_RMP_R`[src]

Bit 0 - Internal trigger 1 remap

`impl R<u32, Reg<u32, _OR2>>`[src]

`pub fn etrsel(&self) -> ETRSEL_R`[src]

Bits 14:16 - ETR source selection

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn arpe(&self) -> ARPE_R`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&self) -> CMS_R`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&self) -> DIR_R`[src]

Bit 4 - Direction

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`impl R<bool, TI1S_A>`[src]

`pub fn variant(&self) -> TI1S_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_xor(&self) -> bool`[src]

Checks if the value of the field is XOR

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> MMS_A`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`pub fn is_update(&self) -> bool`[src]

Checks if the value of the field is UPDATE

`pub fn is_compare_pulse(&self) -> bool`[src]

Checks if the value of the field is COMPAREPULSE

`pub fn is_compare_oc1(&self) -> bool`[src]

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u8, ETF_A>`[src]

`pub fn variant(&self) -> ETF_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<bool, MSM_A>`[src]

`pub fn variant(&self) -> MSM_A`[src]

Get enumerated values variant

`pub fn is_no_sync(&self) -> bool`[src]

Checks if the value of the field is NOSYNC

`pub fn is_sync(&self) -> bool`[src]

Checks if the value of the field is SYNC

`impl R<u8, TS_A>`[src]

`pub fn variant(&self) -> Variant<u8, TS_A>`[src]

Get enumerated values variant

`pub fn is_itr0(&self) -> bool`[src]

Checks if the value of the field is ITR0

`pub fn is_itr1(&self) -> bool`[src]

Checks if the value of the field is ITR1

`pub fn is_itr2(&self) -> bool`[src]

Checks if the value of the field is ITR2

`pub fn is_ti1f_ed(&self) -> bool`[src]

Checks if the value of the field is TI1F_ED

`pub fn is_ti1fp1(&self) -> bool`[src]

Checks if the value of the field is TI1FP1

`pub fn is_ti2fp2(&self) -> bool`[src]

Checks if the value of the field is TI2FP2

`pub fn is_etrf(&self) -> bool`[src]

Checks if the value of the field is ETRF

`impl R<u8, SMS_A>`[src]

`pub fn variant(&self) -> SMS_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_encoder_mode_1(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_1

`pub fn is_encoder_mode_2(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_2

`pub fn is_encoder_mode_3(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_3

`pub fn is_reset_mode(&self) -> bool`[src]

Checks if the value of the field is RESET_MODE

`pub fn is_gated_mode(&self) -> bool`[src]

Checks if the value of the field is GATED_MODE

`pub fn is_trigger_mode(&self) -> bool`[src]

Checks if the value of the field is TRIGGER_MODE

`pub fn is_ext_clock_mode(&self) -> bool`[src]

Checks if the value of the field is EXT_CLOCK_MODE

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn etp(&self) -> ETP_R`[src]

Bit 15 - External trigger polarity

`pub fn ece(&self) -> ECE_R`[src]

Bit 14 - External clock enable

`pub fn etps(&self) -> ETPS_R`[src]

Bits 12:13 - External trigger prescaler

`pub fn etf(&self) -> ETF_R`[src]

`pub fn cc2de(&self) -> CC2DE_R`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&self) -> CC1DE_R`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&self) -> UDE_R`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&self) -> TIE_R`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&self) -> CC4IE_R`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&self) -> CC3IE_R`[src]

`pub fn cc2of(&self) -> CC2OF_R`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn tif(&self) -> TIF_R`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc4if(&self) -> CC4IF_R`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&self) -> CC3IF_R`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&self) -> CC2IF_R`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u8, OC2M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC2M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC2PE_A>`[src]

`pub fn variant(&self) -> OC2PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&self) -> OC2CE_R`[src]

Bit 15 - OC2CE

`pub fn oc2m(&self) -> OC2M_R`[src]

Bits 12:14 - OC2M

`pub fn oc2pe(&self) -> OC2PE_R`[src]

Bit 11 - OC2PE

`pub fn oc2fe(&self) -> OC2FE_R`[src]

Bit 10 - OC2FE

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - CC2S

`pub fn oc1ce(&self) -> OC1CE_R`[src]

Bit 7 - OC1CE

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - OC1M

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - OC1PE

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - OC1FE

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - CC1S

`impl R<u8, CC2S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC2S_A>`[src]

Get enumerated values variant

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, IC1F_A>`[src]

`pub fn variant(&self) -> IC1F_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&self) -> IC2F_R`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&self) -> IC2PSC_R`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u8, OC4M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC4M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC4PE_A>`[src]

`pub fn variant(&self) -> OC4PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&self) -> OC4CE_R`[src]

Bit 15 - O24CE

`pub fn oc4m(&self) -> OC4M_R`[src]

Bits 12:14 - OC4M

`pub fn oc4pe(&self) -> OC4PE_R`[src]

Bit 11 - OC4PE

`pub fn oc4fe(&self) -> OC4FE_R`[src]

Bit 10 - OC4FE

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - CC4S

`pub fn oc3ce(&self) -> OC3CE_R`[src]

Bit 7 - OC3CE

`pub fn oc3m(&self) -> OC3M_R`[src]

Bits 4:6 - OC3M

`pub fn oc3pe(&self) -> OC3PE_R`[src]

Bit 3 - OC3PE

`pub fn oc3fe(&self) -> OC3FE_R`[src]

Bit 2 - OC3FE

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - CC3S

`impl R<u8, CC4S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC4S_A>`[src]

Get enumerated values variant

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&self) -> IC4F_R`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&self) -> IC4PSC_R`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&self) -> IC3F_R`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&self) -> IC3PSC_R`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - Capture/compare 3 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4np(&self) -> CC4NP_R`[src]

Bit 15 - Capture/Compare 4 output Polarity

`pub fn cc4p(&self) -> CC4P_R`[src]

Bit 13 - Capture/Compare 3 output Polarity

`pub fn cc4e(&self) -> CC4E_R`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&self) -> CC3NP_R`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3p(&self) -> CC3P_R`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&self) -> CC3E_R`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&self) -> CC2NP_R`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&self) -> CC2P_R`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&self) -> CC2E_R`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt_h(&self) -> CNT_H_R`[src]

Bits 16:31 - High counter value

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - Counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr_h(&self) -> ARR_H_R`[src]

Bits 16:31 - High Auto-reload value

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr1_h(&self) -> CCR1_H_R`[src]

Bits 16:31 - High Capture/Compare 1 value

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 1 value

`impl R<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&self) -> DBL_R`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&self) -> DBA_R`[src]

Bits 0:4 - DMA base address

`impl R<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&self) -> DMAB_R`[src]

Bits 0:15 - DMA register for burst accesses

`impl R<u32, Reg<u32, _OR1>>`[src]

`pub fn ti1_rmp(&self) -> TI1_RMP_R`[src]

Bits 0:1 - Input Capture 1 remap

`impl R<u32, Reg<u32, _OR2>>`[src]

`pub fn etrsel(&self) -> ETRSEL_R`[src]

Bits 14:16 - ETR source selection

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn arpe(&self) -> ARPE_R`[src]

Bit 7 - Auto-reload preload enable

`pub fn cms(&self) -> CMS_R`[src]

Bits 5:6 - Center-aligned mode selection

`pub fn dir(&self) -> DIR_R`[src]

Bit 4 - Direction

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`impl R<bool, TI1S_A>`[src]

`pub fn variant(&self) -> TI1S_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_xor(&self) -> bool`[src]

Checks if the value of the field is XOR

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> MMS_A`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`pub fn is_update(&self) -> bool`[src]

Checks if the value of the field is UPDATE

`pub fn is_compare_pulse(&self) -> bool`[src]

Checks if the value of the field is COMPAREPULSE

`pub fn is_compare_oc1(&self) -> bool`[src]

`pub fn is_div4(&self) -> bool`[src]

Checks if the value of the field is DIV4

`pub fn is_div8(&self) -> bool`[src]

Checks if the value of the field is DIV8

`impl R<u8, ETF_A>`[src]

`pub fn variant(&self) -> ETF_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<bool, MSM_A>`[src]

`pub fn variant(&self) -> MSM_A`[src]

Get enumerated values variant

`pub fn is_no_sync(&self) -> bool`[src]

Checks if the value of the field is NOSYNC

`pub fn is_sync(&self) -> bool`[src]

Checks if the value of the field is SYNC

`impl R<u8, TS_A>`[src]

`pub fn variant(&self) -> Variant<u8, TS_A>`[src]

Get enumerated values variant

`pub fn is_itr0(&self) -> bool`[src]

Checks if the value of the field is ITR0

`pub fn is_itr1(&self) -> bool`[src]

Checks if the value of the field is ITR1

`pub fn is_itr2(&self) -> bool`[src]

Checks if the value of the field is ITR2

`pub fn is_ti1f_ed(&self) -> bool`[src]

Checks if the value of the field is TI1F_ED

`pub fn is_ti1fp1(&self) -> bool`[src]

Checks if the value of the field is TI1FP1

`pub fn is_ti2fp2(&self) -> bool`[src]

Checks if the value of the field is TI2FP2

`pub fn is_etrf(&self) -> bool`[src]

Checks if the value of the field is ETRF

`impl R<u8, SMS_A>`[src]

`pub fn variant(&self) -> SMS_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_encoder_mode_1(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_1

`pub fn is_encoder_mode_2(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_2

`pub fn is_encoder_mode_3(&self) -> bool`[src]

Checks if the value of the field is ENCODER_MODE_3

`pub fn is_reset_mode(&self) -> bool`[src]

Checks if the value of the field is RESET_MODE

`pub fn is_gated_mode(&self) -> bool`[src]

Checks if the value of the field is GATED_MODE

`pub fn is_trigger_mode(&self) -> bool`[src]

Checks if the value of the field is TRIGGER_MODE

`pub fn is_ext_clock_mode(&self) -> bool`[src]

Checks if the value of the field is EXT_CLOCK_MODE

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn etp(&self) -> ETP_R`[src]

Bit 15 - External trigger polarity

`pub fn ece(&self) -> ECE_R`[src]

Bit 14 - External clock enable

`pub fn etps(&self) -> ETPS_R`[src]

Bits 12:13 - External trigger prescaler

`pub fn etf(&self) -> ETF_R`[src]

`pub fn cc2de(&self) -> CC2DE_R`[src]

Bit 10 - Capture/Compare 2 DMA request enable

`pub fn cc1de(&self) -> CC1DE_R`[src]

Bit 9 - Capture/Compare 1 DMA request enable

`pub fn ude(&self) -> UDE_R`[src]

Bit 8 - Update DMA request enable

`pub fn tie(&self) -> TIE_R`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc4ie(&self) -> CC4IE_R`[src]

Bit 4 - Capture/Compare 4 interrupt enable

`pub fn cc3ie(&self) -> CC3IE_R`[src]

`pub fn cc2of(&self) -> CC2OF_R`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn tif(&self) -> TIF_R`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc4if(&self) -> CC4IF_R`[src]

Bit 4 - Capture/Compare 4 interrupt flag

`pub fn cc3if(&self) -> CC3IF_R`[src]

Bit 3 - Capture/Compare 3 interrupt flag

`pub fn cc2if(&self) -> CC2IF_R`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u8, OC2M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC2M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC2PE_A>`[src]

`pub fn variant(&self) -> OC2PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2ce(&self) -> OC2CE_R`[src]

Bit 15 - OC2CE

`pub fn oc2m(&self) -> OC2M_R`[src]

Bits 12:14 - OC2M

`pub fn oc2pe(&self) -> OC2PE_R`[src]

Bit 11 - OC2PE

`pub fn oc2fe(&self) -> OC2FE_R`[src]

Bit 10 - OC2FE

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - CC2S

`pub fn oc1ce(&self) -> OC1CE_R`[src]

Bit 7 - OC1CE

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - OC1M

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - OC1PE

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - OC1FE

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - CC1S

`impl R<u8, CC2S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC2S_A>`[src]

Get enumerated values variant

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, IC1F_A>`[src]

`pub fn variant(&self) -> IC1F_A`[src]

Get enumerated values variant

`pub fn is_no_filter(&self) -> bool`[src]

Checks if the value of the field is NOFILTER

`pub fn is_fck_int_n2(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N2

`pub fn is_fck_int_n4(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N4

`pub fn is_fck_int_n8(&self) -> bool`[src]

Checks if the value of the field is FCK_INT_N8

`pub fn is_fdts_div2_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N6

`pub fn is_fdts_div2_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV2_N8

`pub fn is_fdts_div4_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N6

`pub fn is_fdts_div4_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV4_N8

`pub fn is_fdts_div8_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N6

`pub fn is_fdts_div8_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV8_N8

`pub fn is_fdts_div16_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N5

`pub fn is_fdts_div16_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N6

`pub fn is_fdts_div16_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV16_N8

`pub fn is_fdts_div32_n5(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N5

`pub fn is_fdts_div32_n6(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N6

`pub fn is_fdts_div32_n8(&self) -> bool`[src]

Checks if the value of the field is FDTS_DIV32_N8

`impl R<u8, CC1S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC1S_A>`[src]

Get enumerated values variant

`pub fn is_ti1(&self) -> bool`[src]

Checks if the value of the field is TI1

`pub fn is_ti2(&self) -> bool`[src]

Checks if the value of the field is TI2

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&self) -> IC2F_R`[src]

Bits 12:15 - Input capture 2 filter

`pub fn ic2psc(&self) -> IC2PSC_R`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u8, OC4M_A>`[src]

`pub fn variant(&self) -> Variant<u8, OC4M_A>`[src]

Get enumerated values variant

`pub fn is_frozen(&self) -> bool`[src]

Checks if the value of the field is FROZEN

`pub fn is_active_on_match(&self) -> bool`[src]

Checks if the value of the field is ACTIVEONMATCH

`pub fn is_inactive_on_match(&self) -> bool`[src]

Checks if the value of the field is INACTIVEONMATCH

`pub fn is_toggle(&self) -> bool`[src]

Checks if the value of the field is TOGGLE

`pub fn is_force_inactive(&self) -> bool`[src]

Checks if the value of the field is FORCEINACTIVE

`pub fn is_force_active(&self) -> bool`[src]

Checks if the value of the field is FORCEACTIVE

`pub fn is_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is PWMMODE1

`pub fn is_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is PWMMODE2

`pub fn is_opm_mode1(&self) -> bool`[src]

Checks if the value of the field is OPMMODE1

`pub fn is_opm_mode2(&self) -> bool`[src]

Checks if the value of the field is OPMMODE2

`pub fn is_combined_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE1

`pub fn is_combined_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is COMBINEDPWMMODE2

`pub fn is_asymmetric_pwm_mode1(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE1

`pub fn is_asymmetric_pwm_mode2(&self) -> bool`[src]

Checks if the value of the field is ASYMMETRICPWMMODE2

`impl R<bool, OC4PE_A>`[src]

`pub fn variant(&self) -> OC4PE_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_output(&self) -> bool`[src]

Checks if the value of the field is OUTPUT

`impl R<u32, Reg<u32, _CCMR2_OUTPUT>>`[src]

`pub fn oc4ce(&self) -> OC4CE_R`[src]

Bit 15 - O24CE

`pub fn oc4m(&self) -> OC4M_R`[src]

Bits 12:14 - OC4M

`pub fn oc4pe(&self) -> OC4PE_R`[src]

Bit 11 - OC4PE

`pub fn oc4fe(&self) -> OC4FE_R`[src]

Bit 10 - OC4FE

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - CC4S

`pub fn oc3ce(&self) -> OC3CE_R`[src]

Bit 7 - OC3CE

`pub fn oc3m(&self) -> OC3M_R`[src]

Bits 4:6 - OC3M

`pub fn oc3pe(&self) -> OC3PE_R`[src]

Bit 3 - OC3PE

`pub fn oc3fe(&self) -> OC3FE_R`[src]

Bit 2 - OC3FE

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - CC3S

`impl R<u8, CC4S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC4S_A>`[src]

Get enumerated values variant

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u8, CC3S_A>`[src]

`pub fn variant(&self) -> Variant<u8, CC3S_A>`[src]

Get enumerated values variant

`pub fn is_ti3(&self) -> bool`[src]

Checks if the value of the field is TI3

`pub fn is_ti4(&self) -> bool`[src]

Checks if the value of the field is TI4

`pub fn is_trc(&self) -> bool`[src]

Checks if the value of the field is TRC

`impl R<u32, Reg<u32, _CCMR2_INPUT>>`[src]

`pub fn ic4f(&self) -> IC4F_R`[src]

Bits 12:15 - Input capture 4 filter

`pub fn ic4psc(&self) -> IC4PSC_R`[src]

Bits 10:11 - Input capture 4 prescaler

`pub fn cc4s(&self) -> CC4S_R`[src]

Bits 8:9 - Capture/Compare 4 selection

`pub fn ic3f(&self) -> IC3F_R`[src]

Bits 4:7 - Input capture 3 filter

`pub fn ic3psc(&self) -> IC3PSC_R`[src]

Bits 2:3 - Input capture 3 prescaler

`pub fn cc3s(&self) -> CC3S_R`[src]

Bits 0:1 - Capture/compare 3 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc4np(&self) -> CC4NP_R`[src]

Bit 15 - Capture/Compare 4 output Polarity

`pub fn cc4p(&self) -> CC4P_R`[src]

Bit 13 - Capture/Compare 3 output Polarity

`pub fn cc4e(&self) -> CC4E_R`[src]

Bit 12 - Capture/Compare 4 output enable

`pub fn cc3np(&self) -> CC3NP_R`[src]

Bit 11 - Capture/Compare 3 output Polarity

`pub fn cc3p(&self) -> CC3P_R`[src]

Bit 9 - Capture/Compare 3 output Polarity

`pub fn cc3e(&self) -> CC3E_R`[src]

Bit 8 - Capture/Compare 3 output enable

`pub fn cc2np(&self) -> CC2NP_R`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&self) -> CC2P_R`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&self) -> CC2E_R`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt_h(&self) -> CNT_H_R`[src]

Bits 16:31 - High counter value

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - Counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr_h(&self) -> ARR_H_R`[src]

Bits 16:31 - High Auto-reload value

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr1_h(&self) -> CCR1_H_R`[src]

Bits 16:31 - High Capture/Compare 1 value

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 1 value

`impl R<u32, Reg<u32, _DCR>>`[src]

`pub fn dbl(&self) -> DBL_R`[src]

Bits 8:12 - DMA burst length

`pub fn dba(&self) -> DBA_R`[src]

Bits 0:4 - DMA base address

`impl R<u32, Reg<u32, _DMAR>>`[src]

`pub fn dmab(&self) -> DMAB_R`[src]

Bits 0:15 - DMA register for burst accesses

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&self) -> CKD_R`[src]

Bits 8:9 - Clock division

`pub fn arpe(&self) -> ARPE_R`[src]

Bit 7 - Auto-reload preload enable

`pub fn opm(&self) -> OPM_R`[src]

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn msm(&self) -> MSM_R`[src]

Bit 7 - Master/Slave mode

`pub fn ts(&self) -> TS_R`[src]

Bits 4:6 - Trigger selection

`pub fn sms(&self) -> SMS_R`[src]

Bits 0:2 - Slave mode selection

`impl R<bool, UIE_A>`[src]

`pub fn variant(&self) -> UIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _DIER>>`[src]

`pub fn tie(&self) -> TIE_R`[src]

Bit 6 - Trigger interrupt enable

`pub fn cc2ie(&self) -> CC2IE_R`[src]

Bit 2 - Capture/Compare 2 interrupt enable

`pub fn cc1ie(&self) -> CC1IE_R`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&self) -> UIE_R`[src]

Bit 0 - Update interrupt enable

`impl R<bool, UIF_A>`[src]

`pub fn variant(&self) -> UIF_A`[src]

Get enumerated values variant

`pub fn is_clear(&self) -> bool`[src]

Checks if the value of the field is CLEAR

`pub fn is_update_pending(&self) -> bool`[src]

Checks if the value of the field is UPDATEPENDING

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn cc2of(&self) -> CC2OF_R`[src]

Bit 10 - Capture/compare 2 overcapture flag

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn tif(&self) -> TIF_R`[src]

Bit 6 - Trigger interrupt flag

`pub fn cc2if(&self) -> CC2IF_R`[src]

Bit 2 - Capture/Compare 2 interrupt flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc2m(&self) -> OC2M_R`[src]

Bits 12:14 - Output Compare 2 mode

`pub fn oc2pe(&self) -> OC2PE_R`[src]

Bit 11 - Output Compare 2 preload enable

`pub fn oc2fe(&self) -> OC2FE_R`[src]

Bit 10 - Output Compare 2 fast enable

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - Output Compare 1 mode

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - Output Compare 1 preload enable

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - Output Compare 1 fast enable

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic2f(&self) -> IC2F_R`[src]

Bits 12:14 - Input capture 2 filter

`pub fn ic2psc(&self) -> IC2PSC_R`[src]

Bits 10:11 - Input capture 2 prescaler

`pub fn cc2s(&self) -> CC2S_R`[src]

Bits 8:9 - Capture/Compare 2 selection

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:6 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc2np(&self) -> CC2NP_R`[src]

Bit 7 - Capture/Compare 2 output Polarity

`pub fn cc2p(&self) -> CC2P_R`[src]

Bit 5 - Capture/Compare 2 output Polarity

`pub fn cc2e(&self) -> CC2E_R`[src]

Bit 4 - Capture/Compare 2 output enable

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 1 value

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`impl R<bool, UIE_A>`[src]

`pub fn variant(&self) -> UIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _DIER>>`[src]

`pub fn cc1ie(&self) -> CC1IE_R`[src]

Bit 1 - Capture/Compare 1 interrupt enable

`pub fn uie(&self) -> UIE_R`[src]

Bit 0 - Update interrupt enable

`impl R<bool, UIF_A>`[src]

`pub fn variant(&self) -> UIF_A`[src]

Get enumerated values variant

`pub fn is_clear(&self) -> bool`[src]

Checks if the value of the field is CLEAR

`pub fn is_update_pending(&self) -> bool`[src]

Checks if the value of the field is UPDATEPENDING

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn cc1of(&self) -> CC1OF_R`[src]

Bit 9 - Capture/Compare 1 overcapture flag

`pub fn cc1if(&self) -> CC1IF_R`[src]

Bit 1 - Capture/compare 1 interrupt flag

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u32, Reg<u32, _CCMR1_OUTPUT>>`[src]

`pub fn oc1m(&self) -> OC1M_R`[src]

Bits 4:6 - Output Compare 1 mode

`pub fn oc1pe(&self) -> OC1PE_R`[src]

Bit 3 - Output Compare 1 preload enable

`pub fn oc1fe(&self) -> OC1FE_R`[src]

Bit 2 - Output Compare 1 fast enable

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u32, Reg<u32, _CCMR1_INPUT>>`[src]

`pub fn ic1f(&self) -> IC1F_R`[src]

Bits 4:7 - Input capture 1 filter

`pub fn ic1psc(&self) -> IC1PSC_R`[src]

Bits 2:3 - Input capture 1 prescaler

`pub fn cc1s(&self) -> CC1S_R`[src]

Bits 0:1 - Capture/Compare 1 selection

`impl R<u32, Reg<u32, _CCER>>`[src]

`pub fn cc1np(&self) -> CC1NP_R`[src]

Bit 3 - Capture/Compare 1 output Polarity

`pub fn cc1p(&self) -> CC1P_R`[src]

Bit 1 - Capture/Compare 1 output Polarity

`pub fn cc1e(&self) -> CC1E_R`[src]

Bit 0 - Capture/Compare 1 output enable

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto-reload value

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ccr(&self) -> CCR_R`[src]

Bits 0:15 - Capture/Compare 1 value

`impl R<u32, Reg<u32, _SMCR>>`[src]

`pub fn sms3(&self) -> SMS3_R`[src]

Bit 16 - Slave mode selection

`pub fn etp(&self) -> ETP_R`[src]

Bit 15 - External trigger polarity

`pub fn ece(&self) -> ECE_R`[src]

Bit 14 - External clock enable

`pub fn etps(&self) -> ETPS_R`[src]

Bits 12:13 - External trigger prescaler

`pub fn etf(&self) -> ETF_R`[src]

Bits 8:11 - External trigger filter

`pub fn msm(&self) -> MSM_R`[src]

Bit 7 - Master/slave mode

`pub fn ts(&self) -> TS_R`[src]

Bits 4:6 - Trigger selection

`pub fn sms(&self) -> SMS_R`[src]

Bits 0:2 - Slave mode selection

Bit 3 - One-pulse mode

`pub fn urs(&self) -> URS_R`[src]

Bit 2 - Update request source

`pub fn udis(&self) -> UDIS_R`[src]

Bit 1 - Update disable

`pub fn cen(&self) -> CEN_R`[src]

Bit 0 - Counter enable

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> Variant<u8, MMS_A>`[src]

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`pub fn is_enable(&self) -> bool`[src]

Checks if the value of the field is ENABLE

`pub fn is_update(&self) -> bool`[src]

Checks if the value of the field is UPDATE

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn mms(&self) -> MMS_R`[src]

Bits 4:6 - Master mode selection

`impl R<bool, UDE_A>`[src]

`pub fn variant(&self) -> UDE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, UIE_A>`[src]

`pub fn variant(&self) -> UIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _DIER>>`[src]

`pub fn ude(&self) -> UDE_R`[src]

Bit 8 - Update DMA request enable

`pub fn uie(&self) -> UIE_R`[src]

Bit 0 - Update interrupt enable

`impl R<bool, UIF_A>`[src]

`pub fn variant(&self) -> UIF_A`[src]

Get enumerated values variant

`pub fn is_clear(&self) -> bool`[src]

Checks if the value of the field is CLEAR

`pub fn is_update_pending(&self) -> bool`[src]

Checks if the value of the field is UPDATEPENDING

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn uif(&self) -> UIF_R`[src]

Bit 0 - Update interrupt flag

`impl R<u32, Reg<u32, _CNT>>`[src]

`pub fn cnt(&self) -> CNT_R`[src]

Bits 0:15 - Low counter value

`impl R<u32, Reg<u32, _PSC>>`[src]

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:15 - Prescaler value

`pub fn is_ifg80(&self) -> bool`[src]

Checks if the value of the field is IFG80

`pub fn is_ifg40(&self) -> bool`[src]

Checks if the value of the field is IFG40

`impl R<bool, JD_A>`[src]

`pub fn variant(&self) -> JD_A`[src]

Get enumerated values variant

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`impl R<bool, WD_A>`[src]

`pub fn variant(&self) -> WD_A`[src]

Get enumerated values variant

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`impl R<bool, CSTF_A>`[src]

`pub fn variant(&self) -> CSTF_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _MACCR>>`[src]

`pub fn re(&self) -> RE_R`[src]

Bit 2 - Receiver enable

`pub fn te(&self) -> TE_R`[src]

Bit 3 - Transmitter enable

`pub fn dc(&self) -> DC_R`[src]

Bit 4 - Deferral check

`pub fn bl(&self) -> BL_R`[src]

Bits 5:6 - Back-off limit

`pub fn apcs(&self) -> APCS_R`[src]

Bit 7 - Automatic pad/CRC stripping

`pub fn rd(&self) -> RD_R`[src]

Bit 9 - Retry disable

`pub fn ipco(&self) -> IPCO_R`[src]

Bit 10 - IPv4 checksum offload

`pub fn dm(&self) -> DM_R`[src]

Bit 11 - Duplex mode

`pub fn lm(&self) -> LM_R`[src]

Bit 12 - Loopback mode

`pub fn rod(&self) -> ROD_R`[src]

Bit 13 - Receive own disable

`pub fn fes(&self) -> FES_R`[src]

Bit 14 - Fast Ethernet speed

`pub fn csd(&self) -> CSD_R`[src]

Bit 16 - Carrier sense disable

`pub fn ifg(&self) -> IFG_R`[src]

`pub fn is_forward_all(&self) -> bool`[src]

Checks if the value of the field is FORWARDALL

`pub fn is_forward_all_filtered(&self) -> bool`[src]

Checks if the value of the field is FORWARDALLFILTERED

`impl R<bool, SAIF_A>`[src]

`pub fn variant(&self) -> SAIF_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_invert(&self) -> bool`[src]

Checks if the value of the field is INVERT

`impl R<bool, SAF_A>`[src]

`pub fn variant(&self) -> SAF_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, HPF_A>`[src]

`pub fn variant(&self) -> HPF_A`[src]

Get enumerated values variant

`pub fn is_hash_only(&self) -> bool`[src]

Checks if the value of the field is HASHONLY

`pub fn is_hash_or_perfect(&self) -> bool`[src]

Checks if the value of the field is HASHORPERFECT

`impl R<bool, RA_A>`[src]

`pub fn variant(&self) -> RA_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _MACFFR>>`[src]

`pub fn pm(&self) -> PM_R`[src]

Bit 0 - Promiscuous mode

`pub fn hu(&self) -> HU_R`[src]

Bit 1 - Hash unicast

`pub fn hm(&self) -> HM_R`[src]

Bit 2 - Hash multicast

`pub fn daif(&self) -> DAIF_R`[src]

Bit 3 - Destination address unique filtering

`pub fn pam(&self) -> PAM_R`[src]

Bit 4 - Pass all multicast

`pub fn bfd(&self) -> BFD_R`[src]

Bit 5 - Broadcast frames disable

`pub fn pcf(&self) -> PCF_R`[src]

Bits 6:7 - Pass control frames

`pub fn saif(&self) -> SAIF_R`[src]

Bit 7 - Source address inverse filtering

`pub fn saf(&self) -> SAF_R`[src]

Bit 8 - Source address filter

`pub fn hpf(&self) -> HPF_R`[src]

Bit 9 - Hash or perfect filter

`pub fn ra(&self) -> RA_R`[src]

Bit 31 - Receive all

`impl R<u32, Reg<u32, _MACHTHR>>`[src]

`pub fn hth(&self) -> HTH_R`[src]

Bits 0:31 - Upper 32 bits of hash table

`impl R<u32, Reg<u32, _MACHTLR>>`[src]

`pub fn htl(&self) -> HTL_R`[src]

Bits 0:31 - Lower 32 bits of hash table

`impl R<bool, MB_A>`[src]

`pub fn variant(&self) -> Variant<bool, MB_A>`[src]

Get enumerated values variant

`pub fn is_busy(&self) -> bool`[src]

Checks if the value of the field is BUSY

`impl R<bool, MW_A>`[src]

`pub fn variant(&self) -> MW_A`[src]

Get enumerated values variant

`pub fn is_read(&self) -> bool`[src]

Checks if the value of the field is READ

`pub fn is_write(&self) -> bool`[src]

Checks if the value of the field is WRITE

`impl R<u8, CR_A>`[src]

`pub fn variant(&self) -> Variant<u8, CR_A>`[src]

Get enumerated values variant

`pub fn is_cr_60_100(&self) -> bool`[src]

Checks if the value of the field is CR_60_100

`pub fn is_cr_100_150(&self) -> bool`[src]

Checks if the value of the field is CR_100_150

`pub fn is_cr_20_35(&self) -> bool`[src]

Checks if the value of the field is CR_20_35

`pub fn is_cr_35_60(&self) -> bool`[src]

Checks if the value of the field is CR_35_60

`pub fn is_cr_150_168(&self) -> bool`[src]

Checks if the value of the field is CR_150_168

`impl R<u32, Reg<u32, _MACMIIAR>>`[src]

`pub fn mb(&self) -> MB_R`[src]

Bit 0 - MII busy

`pub fn mw(&self) -> MW_R`[src]

Bit 1 - MII write

`pub fn cr(&self) -> CR_R`[src]

Bits 2:4 - Clock range

`pub fn mr(&self) -> MR_R`[src]

Bits 6:10 - MII register - select the desired MII register in the PHY device

`pub fn pa(&self) -> PA_R`[src]

Bits 11:15 - PHY address - select which of possible 32 PHYs is being accessed

Checks if the value of the field is PLT4

`pub fn is_plt28(&self) -> bool`[src]

Checks if the value of the field is PLT28

`pub fn is_plt144(&self) -> bool`[src]

Checks if the value of the field is PLT144

`pub fn is_plt256(&self) -> bool`[src]

Checks if the value of the field is PLT256

`impl R<bool, ZQPD_A>`[src]

`pub fn variant(&self) -> ZQPD_A`[src]

Get enumerated values variant

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`impl R<u32, Reg<u32, _MACFCR>>`[src]

`pub fn fcb(&self) -> FCB_R`[src]

Bit 0 - Flow control busy/back pressure activate

`pub fn tfce(&self) -> TFCE_R`[src]

Bit 1 - Transmit flow control enable

`pub fn rfce(&self) -> RFCE_R`[src]

Bit 2 - Receive flow control enable

`pub fn upfd(&self) -> UPFD_R`[src]

Bit 3 - Unicast pause frame detect

`pub fn plt(&self) -> PLT_R`[src]

Bits 4:5 - Pause low threshold

`pub fn zqpd(&self) -> ZQPD_R`[src]

Bit 7 - Zero-quanta pause disable

`pub fn pt(&self) -> PT_R`[src]

Bits 16:31 - Pause time

`impl R<bool, VLANTC_A>`[src]

`pub fn variant(&self) -> VLANTC_A`[src]

Get enumerated values variant

`pub fn is_vlantc16(&self) -> bool`[src]

Checks if the value of the field is VLANTC16

`pub fn is_vlantc12(&self) -> bool`[src]

Checks if the value of the field is VLANTC12

`impl R<u32, Reg<u32, _MACVLANTR>>`[src]

`pub fn vlanti(&self) -> VLANTI_R`[src]

Bits 0:15 - VLAN tag identifier (for receive frames)

`pub fn vlantc(&self) -> VLANTC_R`[src]

Bit 16 - 12-bit VLAN tag comparison

Get enumerated values variant

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _MACPMTCSR>>`[src]

`pub fn pd(&self) -> PD_R`[src]

Bit 0 - Power down

`pub fn mpe(&self) -> MPE_R`[src]

Bit 1 - Magic packet enable

`pub fn wfe(&self) -> WFE_R`[src]

Bit 2 - Wakeup frame enable

`pub fn mpr(&self) -> MPR_R`[src]

Bit 5 - Magic packet received

`pub fn wfr(&self) -> WFR_R`[src]

Bit 6 - Wakeup frame received

`pub fn gu(&self) -> GU_R`[src]

Bit 9 - Global unicast

`pub fn wffrpr(&self) -> WFFRPR_R`[src]

Bit 31 - Wakeup frame filter register pointer reset

`impl R<u32, Reg<u32, _MACDBGR>>`[src]

`pub fn tff(&self) -> TFF_R`[src]

Bit 25 - Tx FIFO full

`pub fn tfne(&self) -> TFNE_R`[src]

Bit 24 - Tx FIFO not empty

`pub fn tfwa(&self) -> TFWA_R`[src]

Bit 22 - Tx FIFO write active

`pub fn tfrs(&self) -> TFRS_R`[src]

Bits 20:21 - Tx FIFO read status

`pub fn mtp(&self) -> MTP_R`[src]

Bit 19 - MAC transmitter in pause

`pub fn mtfcs(&self) -> MTFCS_R`[src]

Bits 17:18 - MAC transmit frame controller status

`pub fn mmtea(&self) -> MMTEA_R`[src]

Bit 16 - MAC MII transmit engine active

`pub fn rffl(&self) -> RFFL_R`[src]

Bits 8:9 - Rx FIFO fill level

`pub fn rfrcs(&self) -> RFRCS_R`[src]

Bits 5:6 - Rx FIFO read controller status

`pub fn rfwra(&self) -> RFWRA_R`[src]

Bit 4 - Rx FIFO write controller active

`pub fn msfrwcs(&self) -> MSFRWCS_R`[src]

Bits 1:2 - MAC small FIFO read/write controllers status

`pub fn mmrpea(&self) -> MMRPEA_R`[src]

Bit 0 - MAC MII receive protocol engine active

`impl R<u32, Reg<u32, _MACSR>>`[src]

`pub fn pmts(&self) -> PMTS_R`[src]

Bit 3 - PMT status

`pub fn mmcs(&self) -> MMCS_R`[src]

Bit 4 - MMC status

`pub fn mmcrs(&self) -> MMCRS_R`[src]

Bit 5 - MMC receive status

`pub fn mmcts(&self) -> MMCTS_R`[src]

Bit 6 - MMC transmit status

`pub fn tsts(&self) -> TSTS_R`[src]

Bit 9 - Time stamp trigger status

`impl R<bool, PMTIM_A>`[src]

`pub fn variant(&self) -> PMTIM_A`[src]

Get enumerated values variant

`pub fn is_unmasked(&self) -> bool`[src]

Checks if the value of the field is UNMASKED

`pub fn is_masked(&self) -> bool`[src]

Checks if the value of the field is MASKED

`impl R<bool, TSTIM_A>`[src]

`pub fn variant(&self) -> TSTIM_A`[src]

Get enumerated values variant

`pub fn is_unmasked(&self) -> bool`[src]

Checks if the value of the field is UNMASKED

`pub fn is_masked(&self) -> bool`[src]

Checks if the value of the field is MASKED

`impl R<u32, Reg<u32, _MACIMR>>`[src]

`pub fn pmtim(&self) -> PMTIM_R`[src]

Bit 3 - PMT interrupt mask

`pub fn tstim(&self) -> TSTIM_R`[src]

Bit 9 - Time stamp trigger interrupt mask

`impl R<u32, Reg<u32, _MACA0HR>>`[src]

`pub fn maca0h(&self) -> MACA0H_R`[src]

Bits 0:15 - MAC address0 high

`pub fn mo(&self) -> MO_R`[src]

Bit 31 - Always 1

`impl R<u32, Reg<u32, _MACA0LR>>`[src]

`pub fn maca0l(&self) -> MACA0L_R`[src]

Bits 0:31 - 0

`impl R<bool, SA_A>`[src]

`pub fn variant(&self) -> SA_A`[src]

Get enumerated values variant

`pub fn is_destination(&self) -> bool`[src]

Checks if the value of the field is DESTINATION

`pub fn is_source(&self) -> bool`[src]

Checks if the value of the field is SOURCE

`impl R<bool, AE_A>`[src]

`pub fn variant(&self) -> AE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _MACA1HR>>`[src]

`pub fn maca1h(&self) -> MACA1H_R`[src]

Bits 0:15 - MACA1H

`pub fn mbc(&self) -> MBC_R`[src]

Bits 24:29 - MBC

`pub fn sa(&self) -> SA_R`[src]

Bit 30 - SA

`pub fn ae(&self) -> AE_R`[src]

Bit 31 - AE

`impl R<u32, Reg<u32, _MACA1LR>>`[src]

`pub fn maca1l(&self) -> MACA1L_R`[src]

Bits 0:31 - MACA1LR

`impl R<bool, SA_A>`[src]

`pub fn variant(&self) -> SA_A`[src]

Get enumerated values variant

`pub fn is_destination(&self) -> bool`[src]

Checks if the value of the field is DESTINATION

`pub fn is_source(&self) -> bool`[src]

Checks if the value of the field is SOURCE

`impl R<bool, AE_A>`[src]

`pub fn variant(&self) -> AE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _MACA2HR>>`[src]

`pub fn maca2h(&self) -> MACA2H_R`[src]

Bits 0:15 - MAC2AH

`pub fn mbc(&self) -> MBC_R`[src]

Bits 24:29 - MBC

`pub fn sa(&self) -> SA_R`[src]

Bit 30 - SA

`pub fn ae(&self) -> AE_R`[src]

Bit 31 - AE

`impl R<u32, Reg<u32, _MACA2LR>>`[src]

`pub fn maca2l(&self) -> MACA2L_R`[src]

Bits 0:31 - MACA2L

`impl R<bool, SA_A>`[src]

`pub fn variant(&self) -> SA_A`[src]

Get enumerated values variant

`pub fn is_destination(&self) -> bool`[src]

Checks if the value of the field is DESTINATION

`pub fn is_source(&self) -> bool`[src]

Checks if the value of the field is SOURCE

`impl R<bool, AE_A>`[src]

`pub fn variant(&self) -> AE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _MACA3HR>>`[src]

`pub fn maca3h(&self) -> MACA3H_R`[src]

Bits 0:15 - MACA3H

`pub fn mbc(&self) -> MBC_R`[src]

Bits 24:29 - MBC

`pub fn sa(&self) -> SA_R`[src]

Bit 30 - SA

`pub fn ae(&self) -> AE_R`[src]

Bit 31 - AE

`impl R<u32, Reg<u32, _MACA3LR>>`[src]

`pub fn maca3l(&self) -> MACA3L_R`[src]

Bits 0:31 - MBCA3L

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&self) -> DR_R`[src]

Bits 0:31 - Data Register

`impl R<u32, Reg<u32, _IDR>>`[src]

`pub fn idr(&self) -> IDR_R`[src]

Bits 0:7 - Independent Data register

`impl R<u32, Reg<u32, _INIT>>`[src]

`pub fn crc_init(&self) -> CRC_INIT_R`[src]

Bits 0:31 - Programmable initial CRC value

`impl R<u32, Reg<u32, _POL>>`[src]

`pub fn pol(&self) -> POL_R`[src]

Bits 0:31 - Programmable polynomial

`impl R<bool, IDE_A>`[src]

`pub fn variant(&self) -> IDE_A`[src]

Get enumerated values variant

`pub fn is_standard(&self) -> bool`[src]

Checks if the value of the field is STANDARD

`pub fn is_extended(&self) -> bool`[src]

Checks if the value of the field is EXTENDED

`impl R<bool, RTR_A>`[src]

`pub fn variant(&self) -> RTR_A`[src]

Get enumerated values variant

`pub fn is_data(&self) -> bool`[src]

Checks if the value of the field is DATA

`pub fn is_remote(&self) -> bool`[src]

Checks if the value of the field is REMOTE

`impl R<u32, Reg<u32, _TIR>>`[src]

`pub fn stid(&self) -> STID_R`[src]

Bits 21:31 - STID

`pub fn exid(&self) -> EXID_R`[src]

Bits 3:20 - EXID

`pub fn ide(&self) -> IDE_R`[src]

Bit 2 - IDE

`pub fn rtr(&self) -> RTR_R`[src]

Bit 1 - RTR

`pub fn txrq(&self) -> TXRQ_R`[src]

Bit 0 - TXRQ

`impl R<u32, Reg<u32, _TDTR>>`[src]

`pub fn time(&self) -> TIME_R`[src]

Bits 16:31 - TIME

`pub fn tgt(&self) -> TGT_R`[src]

Bit 8 - TGT

`pub fn dlc(&self) -> DLC_R`[src]

Bits 0:3 - DLC

`impl R<u32, Reg<u32, _TDLR>>`[src]

`pub fn data3(&self) -> DATA3_R`[src]

Bits 24:31 - DATA3

`pub fn data2(&self) -> DATA2_R`[src]

Bits 16:23 - DATA2

`pub fn data1(&self) -> DATA1_R`[src]

Bits 8:15 - DATA1

`pub fn data0(&self) -> DATA0_R`[src]

Bits 0:7 - DATA0

`impl R<u32, Reg<u32, _TDHR>>`[src]

`pub fn data7(&self) -> DATA7_R`[src]

Bits 24:31 - DATA7

`pub fn data6(&self) -> DATA6_R`[src]

Bits 16:23 - DATA6

`pub fn data5(&self) -> DATA5_R`[src]

Bits 8:15 - DATA5

`pub fn data4(&self) -> DATA4_R`[src]

Bits 0:7 - DATA4

`impl R<bool, IDE_A>`[src]

`pub fn variant(&self) -> IDE_A`[src]

Get enumerated values variant

`pub fn is_standard(&self) -> bool`[src]

Checks if the value of the field is STANDARD

`pub fn is_extended(&self) -> bool`[src]

Checks if the value of the field is EXTENDED

`impl R<bool, RTR_A>`[src]

`pub fn variant(&self) -> RTR_A`[src]

Get enumerated values variant

`pub fn is_data(&self) -> bool`[src]

Checks if the value of the field is DATA

`pub fn is_remote(&self) -> bool`[src]

Checks if the value of the field is REMOTE

`impl R<u32, Reg<u32, _RIR>>`[src]

`pub fn stid(&self) -> STID_R`[src]

Bits 21:31 - STID

`pub fn exid(&self) -> EXID_R`[src]

Bits 3:20 - EXID

`pub fn ide(&self) -> IDE_R`[src]

Bit 2 - IDE

`pub fn rtr(&self) -> RTR_R`[src]

Bit 1 - RTR

`impl R<u32, Reg<u32, _RDTR>>`[src]

`pub fn time(&self) -> TIME_R`[src]

Bits 16:31 - TIME

`pub fn fmi(&self) -> FMI_R`[src]

Bits 8:15 - FMI

`pub fn dlc(&self) -> DLC_R`[src]

Bits 0:3 - DLC

`impl R<u32, Reg<u32, _RDLR>>`[src]

`pub fn data3(&self) -> DATA3_R`[src]

Bits 24:31 - DATA3

`pub fn data2(&self) -> DATA2_R`[src]

Bits 16:23 - DATA2

`pub fn data1(&self) -> DATA1_R`[src]

Bits 8:15 - DATA1

`pub fn data0(&self) -> DATA0_R`[src]

Bits 0:7 - DATA0

`impl R<u32, Reg<u32, _RDHR>>`[src]

`pub fn data7(&self) -> DATA7_R`[src]

Bits 24:31 - DATA7

`pub fn data6(&self) -> DATA6_R`[src]

Bits 16:23 - DATA6

`pub fn data5(&self) -> DATA5_R`[src]

Bits 8:15 - DATA5

`pub fn data4(&self) -> DATA4_R`[src]

Bits 0:7 - DATA4

`impl R<u32, Reg<u32, _FR1>>`[src]

`pub fn fb(&self) -> FB_R`[src]

Bits 0:31 - Filter bits

`impl R<u32, Reg<u32, _FR2>>`[src]

`pub fn fb(&self) -> FB_R`[src]

Bits 0:31 - Filter bits

`impl R<u32, Reg<u32, _MCR>>`[src]

`pub fn dbf(&self) -> DBF_R`[src]

Bit 16 - DBF

`pub fn reset(&self) -> RESET_R`[src]

Bit 15 - RESET

`pub fn ttcm(&self) -> TTCM_R`[src]

Bit 7 - TTCM

`pub fn abom(&self) -> ABOM_R`[src]

Bit 6 - ABOM

`pub fn awum(&self) -> AWUM_R`[src]

Bit 5 - AWUM

`pub fn nart(&self) -> NART_R`[src]

Bit 4 - NART

`pub fn rflm(&self) -> RFLM_R`[src]

Bit 3 - RFLM

`pub fn txfp(&self) -> TXFP_R`[src]

Bit 2 - TXFP

`pub fn sleep(&self) -> SLEEP_R`[src]

Bit 1 - SLEEP

`pub fn inrq(&self) -> INRQ_R`[src]

Bit 0 - INRQ

`impl R<u32, Reg<u32, _MSR>>`[src]

`pub fn rx(&self) -> RX_R`[src]

Bit 11 - RX

`pub fn samp(&self) -> SAMP_R`[src]

Bit 10 - SAMP

`pub fn rxm(&self) -> RXM_R`[src]

Bit 9 - RXM

`pub fn txm(&self) -> TXM_R`[src]

Bit 8 - TXM

`pub fn slaki(&self) -> SLAKI_R`[src]

Bit 4 - SLAKI

`pub fn wkui(&self) -> WKUI_R`[src]

Bit 3 - WKUI

`pub fn erri(&self) -> ERRI_R`[src]

Bit 2 - ERRI

`pub fn slak(&self) -> SLAK_R`[src]

Bit 1 - SLAK

`pub fn inak(&self) -> INAK_R`[src]

Bit 0 - INAK

`impl R<u32, Reg<u32, _TSR>>`[src]

`pub fn low2(&self) -> LOW2_R`[src]

Bit 31 - Lowest priority flag for mailbox 2

`pub fn low1(&self) -> LOW1_R`[src]

Bit 30 - Lowest priority flag for mailbox 1

`pub fn low0(&self) -> LOW0_R`[src]

Bit 29 - Lowest priority flag for mailbox 0

`pub fn tme2(&self) -> TME2_R`[src]

Bit 28 - Lowest priority flag for mailbox 2

`pub fn tme1(&self) -> TME1_R`[src]

Bit 27 - Lowest priority flag for mailbox 1

`pub fn tme0(&self) -> TME0_R`[src]

Bit 26 - Lowest priority flag for mailbox 0

`pub fn code(&self) -> CODE_R`[src]

Bits 24:25 - CODE

`pub fn abrq2(&self) -> ABRQ2_R`[src]

Bit 23 - ABRQ2

`pub fn terr2(&self) -> TERR2_R`[src]

Bit 19 - TERR2

`pub fn alst2(&self) -> ALST2_R`[src]

Bit 18 - ALST2

`pub fn txok2(&self) -> TXOK2_R`[src]

Bit 17 - TXOK2

`pub fn rqcp2(&self) -> RQCP2_R`[src]

Bit 16 - RQCP2

`pub fn abrq1(&self) -> ABRQ1_R`[src]

Bit 15 - ABRQ1

`pub fn terr1(&self) -> TERR1_R`[src]

Bit 11 - TERR1

`pub fn alst1(&self) -> ALST1_R`[src]

Bit 10 - ALST1

`pub fn txok1(&self) -> TXOK1_R`[src]

Bit 9 - TXOK1

`pub fn rqcp1(&self) -> RQCP1_R`[src]

Bit 8 - RQCP1

`pub fn abrq0(&self) -> ABRQ0_R`[src]

Bit 7 - ABRQ0

`pub fn terr0(&self) -> TERR0_R`[src]

Bit 3 - TERR0

`pub fn alst0(&self) -> ALST0_R`[src]

Bit 2 - ALST0

`pub fn txok0(&self) -> TXOK0_R`[src]

Bit 1 - TXOK0

`pub fn rqcp0(&self) -> RQCP0_R`[src]

Bit 0 - RQCP0

`pub fn lecie(&self) -> LECIE_R`[src]

Bit 11 - LECIE

`pub fn bofie(&self) -> BOFIE_R`[src]

Bit 10 - BOFIE

`pub fn epvie(&self) -> EPVIE_R`[src]

Bit 9 - EPVIE

`pub fn ewgie(&self) -> EWGIE_R`[src]

Bit 8 - EWGIE

`pub fn fovie1(&self) -> FOVIE1_R`[src]

Bit 6 - FOVIE1

`pub fn ffie1(&self) -> FFIE1_R`[src]

Bit 5 - FFIE1

`pub fn fmpie1(&self) -> FMPIE1_R`[src]

Bit 4 - FMPIE1

`pub fn fovie0(&self) -> FOVIE0_R`[src]

Bit 3 - FOVIE0

`pub fn ffie0(&self) -> FFIE0_R`[src]

Bit 2 - FFIE0

`pub fn fmpie0(&self) -> FMPIE0_R`[src]

Bit 1 - FMPIE0

`pub fn tmeie(&self) -> TMEIE_R`[src]

Bit 0 - TMEIE

`impl R<u8, LEC_A>`[src]

`pub fn variant(&self) -> LEC_A`[src]

Get enumerated values variant

`pub fn is_no_error(&self) -> bool`[src]

Checks if the value of the field is NOERROR

`pub fn is_stuff(&self) -> bool`[src]

Checks if the value of the field is STUFF

`pub fn is_form(&self) -> bool`[src]

Checks if the value of the field is FORM

`pub fn is_ack(&self) -> bool`[src]

Checks if the value of the field is ACK

`pub fn is_bit_recessive(&self) -> bool`[src]

Checks if the value of the field is BITRECESSIVE

`pub fn is_bit_dominant(&self) -> bool`[src]

Checks if the value of the field is BITDOMINANT

`pub fn is_crc(&self) -> bool`[src]

Checks if the value of the field is CRC

`pub fn is_custom(&self) -> bool`[src]

Checks if the value of the field is CUSTOM

`impl R<u32, Reg<u32, _ESR>>`[src]

`pub fn rec(&self) -> REC_R`[src]

Bits 24:31 - REC

`pub fn tec(&self) -> TEC_R`[src]

Bits 16:23 - TEC

`pub fn lec(&self) -> LEC_R`[src]

Bits 4:6 - LEC

`pub fn boff(&self) -> BOFF_R`[src]

Bit 2 - BOFF

`pub fn epvf(&self) -> EPVF_R`[src]

Bit 1 - EPVF

`pub fn ewgf(&self) -> EWGF_R`[src]

Bit 0 - EWGF

`impl R<bool, SILM_A>`[src]

`pub fn variant(&self) -> SILM_A`[src]

Get enumerated values variant

`pub fn is_normal(&self) -> bool`[src]

Checks if the value of the field is NORMAL

`pub fn is_silent(&self) -> bool`[src]

Checks if the value of the field is SILENT

`impl R<bool, LBKM_A>`[src]

`pub fn variant(&self) -> LBKM_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _BTR>>`[src]

`pub fn silm(&self) -> SILM_R`[src]

Bit 31 - SILM

`pub fn lbkm(&self) -> LBKM_R`[src]

Bit 30 - LBKM

`pub fn sjw(&self) -> SJW_R`[src]

Bits 24:25 - SJW

`pub fn ts2(&self) -> TS2_R`[src]

Bits 20:22 - TS2

`pub fn ts1(&self) -> TS1_R`[src]

Bits 16:19 - TS1

`pub fn brp(&self) -> BRP_R`[src]

Bits 0:9 - BRP

`impl R<u32, Reg<u32, _FMR>>`[src]

`pub fn can2sb(&self) -> CAN2SB_R`[src]

Bits 8:13 - CAN2SB

`pub fn finit(&self) -> FINIT_R`[src]

Bit 0 - FINIT

`impl R<u32, Reg<u32, _FM1R>>`[src]

`pub fn fbm0(&self) -> FBM0_R`[src]

Bit 0 - Filter mode

`pub fn fbm1(&self) -> FBM1_R`[src]

Bit 1 - Filter mode

`pub fn fbm2(&self) -> FBM2_R`[src]

Bit 2 - Filter mode

`pub fn fbm3(&self) -> FBM3_R`[src]

Bit 3 - Filter mode

`pub fn fbm4(&self) -> FBM4_R`[src]

Bit 4 - Filter mode

`pub fn fbm5(&self) -> FBM5_R`[src]

Bit 5 - Filter mode

`pub fn fbm6(&self) -> FBM6_R`[src]

Bit 6 - Filter mode

`pub fn fbm7(&self) -> FBM7_R`[src]

Bit 7 - Filter mode

`pub fn fbm8(&self) -> FBM8_R`[src]

Bit 8 - Filter mode

`pub fn fbm9(&self) -> FBM9_R`[src]

Bit 9 - Filter mode

`pub fn fbm10(&self) -> FBM10_R`[src]

Bit 10 - Filter mode

`pub fn fbm11(&self) -> FBM11_R`[src]

Bit 11 - Filter mode

`pub fn fbm12(&self) -> FBM12_R`[src]

Bit 12 - Filter mode

`pub fn fbm13(&self) -> FBM13_R`[src]

Bit 13 - Filter mode

`pub fn fbm14(&self) -> FBM14_R`[src]

Bit 14 - Filter mode

`pub fn fbm15(&self) -> FBM15_R`[src]

Bit 15 - Filter mode

`pub fn fbm16(&self) -> FBM16_R`[src]

Bit 16 - Filter mode

`pub fn fbm17(&self) -> FBM17_R`[src]

Bit 17 - Filter mode

`pub fn fbm18(&self) -> FBM18_R`[src]

Bit 18 - Filter mode

`pub fn fbm19(&self) -> FBM19_R`[src]

Bit 19 - Filter mode

`pub fn fbm20(&self) -> FBM20_R`[src]

Bit 20 - Filter mode

`pub fn fbm21(&self) -> FBM21_R`[src]

Bit 21 - Filter mode

`pub fn fbm22(&self) -> FBM22_R`[src]

Bit 22 - Filter mode

`pub fn fbm23(&self) -> FBM23_R`[src]

Bit 23 - Filter mode

`pub fn fbm24(&self) -> FBM24_R`[src]

Bit 24 - Filter mode

`pub fn fbm25(&self) -> FBM25_R`[src]

Bit 25 - Filter mode

`pub fn fbm26(&self) -> FBM26_R`[src]

Bit 26 - Filter mode

`pub fn fbm27(&self) -> FBM27_R`[src]

Bit 27 - Filter mode

`impl R<u32, Reg<u32, _FS1R>>`[src]

`pub fn fsc0(&self) -> FSC0_R`[src]

Bit 0 - Filter scale configuration

`pub fn fsc1(&self) -> FSC1_R`[src]

Bit 1 - Filter scale configuration

`pub fn fsc2(&self) -> FSC2_R`[src]

Bit 2 - Filter scale configuration

`pub fn fsc3(&self) -> FSC3_R`[src]

Bit 3 - Filter scale configuration

`pub fn fsc4(&self) -> FSC4_R`[src]

Bit 4 - Filter scale configuration

`pub fn fsc5(&self) -> FSC5_R`[src]

Bit 5 - Filter scale configuration

`pub fn fsc6(&self) -> FSC6_R`[src]

Bit 6 - Filter scale configuration

`pub fn fsc7(&self) -> FSC7_R`[src]

Bit 7 - Filter scale configuration

`pub fn fsc8(&self) -> FSC8_R`[src]

Bit 8 - Filter scale configuration

`pub fn fsc9(&self) -> FSC9_R`[src]

Bit 9 - Filter scale configuration

`pub fn fsc10(&self) -> FSC10_R`[src]

Bit 10 - Filter scale configuration

`pub fn fsc11(&self) -> FSC11_R`[src]

Bit 11 - Filter scale configuration

`pub fn fsc12(&self) -> FSC12_R`[src]

Bit 12 - Filter scale configuration

`pub fn fsc13(&self) -> FSC13_R`[src]

Bit 13 - Filter scale configuration

`pub fn fsc14(&self) -> FSC14_R`[src]

Bit 14 - Filter scale configuration

`pub fn fsc15(&self) -> FSC15_R`[src]

Bit 15 - Filter scale configuration

`pub fn fsc16(&self) -> FSC16_R`[src]

Bit 16 - Filter scale configuration

`pub fn fsc17(&self) -> FSC17_R`[src]

Bit 17 - Filter scale configuration

`pub fn fsc18(&self) -> FSC18_R`[src]

Bit 18 - Filter scale configuration

`pub fn fsc19(&self) -> FSC19_R`[src]

Bit 19 - Filter scale configuration

`pub fn fsc20(&self) -> FSC20_R`[src]

Bit 20 - Filter scale configuration

`pub fn fsc21(&self) -> FSC21_R`[src]

Bit 21 - Filter scale configuration

`pub fn fsc22(&self) -> FSC22_R`[src]

Bit 22 - Filter scale configuration

`pub fn fsc23(&self) -> FSC23_R`[src]

Bit 23 - Filter scale configuration

`pub fn fsc24(&self) -> FSC24_R`[src]

Bit 24 - Filter scale configuration

`pub fn fsc25(&self) -> FSC25_R`[src]

Bit 25 - Filter scale configuration

`pub fn fsc26(&self) -> FSC26_R`[src]

Bit 26 - Filter scale configuration

`pub fn fsc27(&self) -> FSC27_R`[src]

Bit 27 - Filter scale configuration

`impl R<u32, Reg<u32, _FFA1R>>`[src]

`pub fn ffa0(&self) -> FFA0_R`[src]

Bit 0 - Filter FIFO assignment for filter 0

`pub fn ffa1(&self) -> FFA1_R`[src]

Bit 1 - Filter FIFO assignment for filter 1

`pub fn ffa2(&self) -> FFA2_R`[src]

Bit 2 - Filter FIFO assignment for filter 2

`pub fn ffa3(&self) -> FFA3_R`[src]

Bit 3 - Filter FIFO assignment for filter 3

`pub fn ffa4(&self) -> FFA4_R`[src]

Bit 4 - Filter FIFO assignment for filter 4

`pub fn ffa5(&self) -> FFA5_R`[src]

Bit 5 - Filter FIFO assignment for filter 5

`pub fn ffa6(&self) -> FFA6_R`[src]

Bit 6 - Filter FIFO assignment for filter 6

`pub fn ffa7(&self) -> FFA7_R`[src]

Bit 7 - Filter FIFO assignment for filter 7

`pub fn ffa8(&self) -> FFA8_R`[src]

Bit 8 - Filter FIFO assignment for filter 8

`pub fn ffa9(&self) -> FFA9_R`[src]

Bit 9 - Filter FIFO assignment for filter 9

`pub fn ffa10(&self) -> FFA10_R`[src]

Bit 10 - Filter FIFO assignment for filter 10

`pub fn ffa11(&self) -> FFA11_R`[src]

Bit 11 - Filter FIFO assignment for filter 11

`pub fn ffa12(&self) -> FFA12_R`[src]

Bit 12 - Filter FIFO assignment for filter 12

`pub fn ffa13(&self) -> FFA13_R`[src]

Bit 13 - Filter FIFO assignment for filter 13

`pub fn ffa14(&self) -> FFA14_R`[src]

Bit 14 - Filter FIFO assignment for filter 14

`pub fn ffa15(&self) -> FFA15_R`[src]

Bit 15 - Filter FIFO assignment for filter 15

`pub fn ffa16(&self) -> FFA16_R`[src]

Bit 16 - Filter FIFO assignment for filter 16

`pub fn ffa17(&self) -> FFA17_R`[src]

Bit 17 - Filter FIFO assignment for filter 17

`pub fn ffa18(&self) -> FFA18_R`[src]

Bit 18 - Filter FIFO assignment for filter 18

`pub fn ffa19(&self) -> FFA19_R`[src]

Bit 19 - Filter FIFO assignment for filter 19

`pub fn ffa20(&self) -> FFA20_R`[src]

Bit 20 - Filter FIFO assignment for filter 20

`pub fn ffa21(&self) -> FFA21_R`[src]

Bit 21 - Filter FIFO assignment for filter 21

`pub fn ffa22(&self) -> FFA22_R`[src]

Bit 22 - Filter FIFO assignment for filter 22

`pub fn ffa23(&self) -> FFA23_R`[src]

Bit 23 - Filter FIFO assignment for filter 23

`pub fn ffa24(&self) -> FFA24_R`[src]

Bit 24 - Filter FIFO assignment for filter 24

`pub fn ffa25(&self) -> FFA25_R`[src]

Bit 25 - Filter FIFO assignment for filter 25

`pub fn ffa26(&self) -> FFA26_R`[src]

Bit 26 - Filter FIFO assignment for filter 26

`pub fn ffa27(&self) -> FFA27_R`[src]

Bit 27 - Filter FIFO assignment for filter 27

`impl R<u32, Reg<u32, _FA1R>>`[src]

`pub fn fact0(&self) -> FACT0_R`[src]

Bit 0 - Filter active

`pub fn fact1(&self) -> FACT1_R`[src]

Bit 1 - Filter active

`pub fn fact2(&self) -> FACT2_R`[src]

Bit 2 - Filter active

`pub fn fact3(&self) -> FACT3_R`[src]

Bit 3 - Filter active

`pub fn fact4(&self) -> FACT4_R`[src]

Bit 4 - Filter active

`pub fn fact5(&self) -> FACT5_R`[src]

Bit 5 - Filter active

`pub fn fact6(&self) -> FACT6_R`[src]

Bit 6 - Filter active

`pub fn fact7(&self) -> FACT7_R`[src]

Bit 7 - Filter active

`pub fn fact8(&self) -> FACT8_R`[src]

Bit 8 - Filter active

`pub fn fact9(&self) -> FACT9_R`[src]

Bit 9 - Filter active

`pub fn fact10(&self) -> FACT10_R`[src]

Bit 10 - Filter active

`pub fn fact11(&self) -> FACT11_R`[src]

Bit 11 - Filter active

`pub fn fact12(&self) -> FACT12_R`[src]

Bit 12 - Filter active

`pub fn fact13(&self) -> FACT13_R`[src]

Bit 13 - Filter active

`pub fn fact14(&self) -> FACT14_R`[src]

Bit 14 - Filter active

`pub fn fact15(&self) -> FACT15_R`[src]

Bit 15 - Filter active

`pub fn fact16(&self) -> FACT16_R`[src]

Bit 16 - Filter active

`pub fn fact17(&self) -> FACT17_R`[src]

Bit 17 - Filter active

`pub fn fact18(&self) -> FACT18_R`[src]

Bit 18 - Filter active

`pub fn fact19(&self) -> FACT19_R`[src]

Bit 19 - Filter active

`pub fn fact20(&self) -> FACT20_R`[src]

Bit 20 - Filter active

`pub fn fact21(&self) -> FACT21_R`[src]

Bit 21 - Filter active

`pub fn fact22(&self) -> FACT22_R`[src]

Bit 22 - Filter active

`pub fn fact23(&self) -> FACT23_R`[src]

Bit 23 - Filter active

`pub fn fact24(&self) -> FACT24_R`[src]

Bit 24 - Filter active

`pub fn fact25(&self) -> FACT25_R`[src]

Bit 25 - Filter active

`pub fn fact26(&self) -> FACT26_R`[src]

Bit 26 - Filter active

`pub fn fact27(&self) -> FACT27_R`[src]

Bit 27 - Filter active

`impl R<u8, LATENCY_A>`[src]

`pub fn variant(&self) -> LATENCY_A`[src]

Get enumerated values variant

`pub fn is_ws0(&self) -> bool`[src]

Checks if the value of the field is WS0

`pub fn is_ws1(&self) -> bool`[src]

Checks if the value of the field is WS1

`pub fn is_ws2(&self) -> bool`[src]

Checks if the value of the field is WS2

`pub fn is_ws3(&self) -> bool`[src]

Checks if the value of the field is WS3

`pub fn is_ws4(&self) -> bool`[src]

Checks if the value of the field is WS4

`pub fn is_ws5(&self) -> bool`[src]

Checks if the value of the field is WS5

`pub fn is_ws6(&self) -> bool`[src]

Checks if the value of the field is WS6

`pub fn is_ws7(&self) -> bool`[src]

Checks if the value of the field is WS7

`pub fn is_ws8(&self) -> bool`[src]

Checks if the value of the field is WS8

`pub fn is_ws9(&self) -> bool`[src]

Checks if the value of the field is WS9

`pub fn is_ws10(&self) -> bool`[src]

Checks if the value of the field is WS10

`pub fn is_ws11(&self) -> bool`[src]

Checks if the value of the field is WS11

`pub fn is_ws12(&self) -> bool`[src]

Checks if the value of the field is WS12

`pub fn is_ws13(&self) -> bool`[src]

Checks if the value of the field is WS13

`pub fn is_ws14(&self) -> bool`[src]

Checks if the value of the field is WS14

`pub fn is_ws15(&self) -> bool`[src]

Checks if the value of the field is WS15

`impl R<bool, PRFTEN_A>`[src]

`pub fn variant(&self) -> PRFTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, ARTEN_A>`[src]

`pub fn variant(&self) -> ARTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, ARTRST_A>`[src]

`pub fn variant(&self) -> ARTRST_A`[src]

Get enumerated values variant

`pub fn is_not_reset(&self) -> bool`[src]

Checks if the value of the field is NOTRESET

`pub fn is_reset(&self) -> bool`[src]

Checks if the value of the field is RESET

`impl R<u32, Reg<u32, _ACR>>`[src]

`pub fn latency(&self) -> LATENCY_R`[src]

Bits 0:3 - Latency

`pub fn prften(&self) -> PRFTEN_R`[src]

Bit 8 - Prefetch enable

`pub fn arten(&self) -> ARTEN_R`[src]

Bit 9 - ART Accelerator Enable

`pub fn artrst(&self) -> ARTRST_R`[src]

Bit 11 - ART Accelerator reset

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn eop(&self) -> EOP_R`[src]

Bit 0 - End of operation

`pub fn operr(&self) -> OPERR_R`[src]

Bit 1 - Operation error

`pub fn wrperr(&self) -> WRPERR_R`[src]

Bit 4 - Write protection error

`pub fn pgaerr(&self) -> PGAERR_R`[src]

Bit 5 - Programming alignment error

`pub fn pgperr(&self) -> PGPERR_R`[src]

Bit 6 - Programming parallelism error

`pub fn erserr(&self) -> ERSERR_R`[src]

Bit 7 - Programming sequence error

`pub fn bsy(&self) -> BSY_R`[src]

Bit 16 - Busy

`impl R<bool, PG_A>`[src]

`pub fn variant(&self) -> Variant<bool, PG_A>`[src]

Get enumerated values variant

`pub fn is_program(&self) -> bool`[src]

Checks if the value of the field is PROGRAM

`impl R<bool, SER_A>`[src]

`pub fn variant(&self) -> Variant<bool, SER_A>`[src]

Get enumerated values variant

`pub fn is_sector_erase(&self) -> bool`[src]

Checks if the value of the field is SECTORERASE

`impl R<bool, MER1_A>`[src]

`pub fn variant(&self) -> Variant<bool, MER1_A>`[src]

Get enumerated values variant

`pub fn is_mass_erase(&self) -> bool`[src]

Checks if the value of the field is MASSERASE

`impl R<u8, PSIZE_A>`[src]

`pub fn variant(&self) -> PSIZE_A`[src]

Get enumerated values variant

`pub fn is_psize8(&self) -> bool`[src]

Checks if the value of the field is PSIZE8

`pub fn is_psize16(&self) -> bool`[src]

Checks if the value of the field is PSIZE16

`pub fn is_psize32(&self) -> bool`[src]

Checks if the value of the field is PSIZE32

`pub fn is_psize64(&self) -> bool`[src]

Checks if the value of the field is PSIZE64

`impl R<bool, MER2_A>`[src]

`pub fn variant(&self) -> Variant<bool, MER2_A>`[src]

Get enumerated values variant

`pub fn is_mass_erase(&self) -> bool`[src]

Checks if the value of the field is MASSERASE

Bit 0 - Programming

`pub fn ser(&self) -> SER_R`[src]

Bit 1 - Sector Erase

`pub fn mer1(&self) -> MER1_R`[src]

Bit 2 - Mass Erase of sectors 0 to 11

`pub fn snb(&self) -> SNB_R`[src]

Bits 3:7 - Sector number

`pub fn psize(&self) -> PSIZE_R`[src]

Bits 8:9 - Program size

`pub fn mer2(&self) -> MER2_R`[src]

Bit 15 - Mass Erase of sectors 12 to 23

`pub fn strt(&self) -> STRT_R`[src]

Bit 16 - Start

`pub fn eopie(&self) -> EOPIE_R`[src]

Bit 24 - End of operation interrupt enable

`pub fn errie(&self) -> ERRIE_R`[src]

Bit 25 - Error interrupt enable

`pub fn lock(&self) -> LOCK_R`[src]

Bit 31 - Lock

`impl R<u32, Reg<u32, _OPTCR>>`[src]

`pub fn optlock(&self) -> OPTLOCK_R`[src]

Bit 0 - Option lock

`pub fn optstrt(&self) -> OPTSTRT_R`[src]

Bit 1 - Option start

`pub fn bor_lev(&self) -> BOR_LEV_R`[src]

Bits 2:3 - BOR reset Level

`pub fn wwdg_sw(&self) -> WWDG_SW_R`[src]

Bit 4 - User option bytes

`pub fn iwdg_sw(&self) -> IWDG_SW_R`[src]

Bit 5 - User option bytes

`pub fn n_rst_stop(&self) -> NRST_STOP_R`[src]

Bit 6 - User option bytes

`pub fn n_rst_stdby(&self) -> NRST_STDBY_R`[src]

Bit 7 - User option bytes

`pub fn rdp(&self) -> RDP_R`[src]

Bits 8:15 - Read protect

`pub fn n_wrp(&self) -> NWRP_R`[src]

Bits 16:27 - Not write protect

`pub fn n_dboot(&self) -> NDBOOT_R`[src]

Bit 28 - Dual Boot mode (valid only when nDBANK=0)

`pub fn n_dbank(&self) -> NDBANK_R`[src]

Bit 29 - Not dual bank mode

`pub fn iwdg_stdby(&self) -> IWDG_STDBY_R`[src]

Bit 30 - Independent watchdog counter freeze in standby mode

`pub fn iwdg_stop(&self) -> IWDG_STOP_R`[src]

Bit 31 - Independent watchdog counter freeze in Stop mode

`impl R<u32, Reg<u32, _OPTCR1>>`[src]

`pub fn boot_add0(&self) -> BOOT_ADD0_R`[src]

Bits 0:15 - Boot base address when Boot pin =0

`pub fn boot_add1(&self) -> BOOT_ADD1_R`[src]

Bits 16:31 - Boot base address when Boot pin =1

`impl R<bool, MR0_A>`[src]

`pub fn variant(&self) -> MR0_A`[src]

Get enumerated values variant

`pub fn is_masked(&self) -> bool`[src]

Checks if the value of the field is MASKED

`pub fn is_unmasked(&self) -> bool`[src]

Checks if the value of the field is UNMASKED

`impl R<u32, Reg<u32, _IMR>>`[src]

`pub fn mr0(&self) -> MR0_R`[src]

Bit 0 - Interrupt Mask on line 0

`pub fn mr1(&self) -> MR1_R`[src]

Bit 1 - Interrupt Mask on line 1

`pub fn mr2(&self) -> MR2_R`[src]

Bit 2 - Interrupt Mask on line 2

`pub fn mr3(&self) -> MR3_R`[src]

Bit 3 - Interrupt Mask on line 3

`pub fn mr4(&self) -> MR4_R`[src]

Bit 4 - Interrupt Mask on line 4

`pub fn mr5(&self) -> MR5_R`[src]

Bit 5 - Interrupt Mask on line 5

`pub fn mr6(&self) -> MR6_R`[src]

Bit 6 - Interrupt Mask on line 6

`pub fn mr7(&self) -> MR7_R`[src]

Bit 7 - Interrupt Mask on line 7

`pub fn mr8(&self) -> MR8_R`[src]

Bit 8 - Interrupt Mask on line 8

`pub fn mr9(&self) -> MR9_R`[src]

Bit 9 - Interrupt Mask on line 9

`pub fn mr10(&self) -> MR10_R`[src]

Bit 10 - Interrupt Mask on line 10

`pub fn mr11(&self) -> MR11_R`[src]

Bit 11 - Interrupt Mask on line 11

`pub fn mr12(&self) -> MR12_R`[src]

Bit 12 - Interrupt Mask on line 12

`pub fn mr13(&self) -> MR13_R`[src]

Bit 13 - Interrupt Mask on line 13

`pub fn mr14(&self) -> MR14_R`[src]

Bit 14 - Interrupt Mask on line 14

`pub fn mr15(&self) -> MR15_R`[src]

Bit 15 - Interrupt Mask on line 15

`pub fn mr16(&self) -> MR16_R`[src]

Bit 16 - Interrupt Mask on line 16

`pub fn mr17(&self) -> MR17_R`[src]

Bit 17 - Interrupt Mask on line 17

`pub fn mr18(&self) -> MR18_R`[src]

Bit 18 - Interrupt Mask on line 18

`pub fn mr19(&self) -> MR19_R`[src]

Bit 19 - Interrupt Mask on line 19

`pub fn mr20(&self) -> MR20_R`[src]

Bit 20 - Interrupt Mask on line 20

`pub fn mr21(&self) -> MR21_R`[src]

Bit 21 - Interrupt Mask on line 21

`pub fn mr22(&self) -> MR22_R`[src]

Bit 22 - Interrupt Mask on line 22

`impl R<bool, MR0_A>`[src]

`pub fn variant(&self) -> MR0_A`[src]

Get enumerated values variant

`pub fn is_masked(&self) -> bool`[src]

Checks if the value of the field is MASKED

`pub fn is_unmasked(&self) -> bool`[src]

Checks if the value of the field is UNMASKED

`impl R<u32, Reg<u32, _EMR>>`[src]

`pub fn mr0(&self) -> MR0_R`[src]

Bit 0 - Event Mask on line 0

`pub fn mr1(&self) -> MR1_R`[src]

Bit 1 - Event Mask on line 1

`pub fn mr2(&self) -> MR2_R`[src]

Bit 2 - Event Mask on line 2

`pub fn mr3(&self) -> MR3_R`[src]

Bit 3 - Event Mask on line 3

`pub fn mr4(&self) -> MR4_R`[src]

Bit 4 - Event Mask on line 4

`pub fn mr5(&self) -> MR5_R`[src]

Bit 5 - Event Mask on line 5

`pub fn mr6(&self) -> MR6_R`[src]

Bit 6 - Event Mask on line 6

`pub fn mr7(&self) -> MR7_R`[src]

Bit 7 - Event Mask on line 7

`pub fn mr8(&self) -> MR8_R`[src]

Bit 8 - Event Mask on line 8

`pub fn mr9(&self) -> MR9_R`[src]

Bit 9 - Event Mask on line 9

`pub fn mr10(&self) -> MR10_R`[src]

Bit 10 - Event Mask on line 10

`pub fn mr11(&self) -> MR11_R`[src]

Bit 11 - Event Mask on line 11

`pub fn mr12(&self) -> MR12_R`[src]

Bit 12 - Event Mask on line 12

`pub fn mr13(&self) -> MR13_R`[src]

Bit 13 - Event Mask on line 13

`pub fn mr14(&self) -> MR14_R`[src]

Bit 14 - Event Mask on line 14

`pub fn mr15(&self) -> MR15_R`[src]

Bit 15 - Event Mask on line 15

`pub fn mr16(&self) -> MR16_R`[src]

Bit 16 - Event Mask on line 16

`pub fn mr17(&self) -> MR17_R`[src]

Bit 17 - Event Mask on line 17

`pub fn mr18(&self) -> MR18_R`[src]

Bit 18 - Event Mask on line 18

`pub fn mr19(&self) -> MR19_R`[src]

Bit 19 - Event Mask on line 19

`pub fn mr20(&self) -> MR20_R`[src]

Bit 20 - Event Mask on line 20

`pub fn mr21(&self) -> MR21_R`[src]

Bit 21 - Event Mask on line 21

`pub fn mr22(&self) -> MR22_R`[src]

Bit 22 - Event Mask on line 22

`impl R<bool, TR0_A>`[src]

`pub fn variant(&self) -> TR0_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _RTSR>>`[src]

`pub fn tr0(&self) -> TR0_R`[src]

Bit 0 - Rising trigger event configuration of line 0

`pub fn tr1(&self) -> TR1_R`[src]

Bit 1 - Rising trigger event configuration of line 1

`pub fn tr2(&self) -> TR2_R`[src]

Bit 2 - Rising trigger event configuration of line 2

`pub fn tr3(&self) -> TR3_R`[src]

Bit 3 - Rising trigger event configuration of line 3

`pub fn tr4(&self) -> TR4_R`[src]

Bit 4 - Rising trigger event configuration of line 4

`pub fn tr5(&self) -> TR5_R`[src]

Bit 5 - Rising trigger event configuration of line 5

`pub fn tr6(&self) -> TR6_R`[src]

Bit 6 - Rising trigger event configuration of line 6

`pub fn tr7(&self) -> TR7_R`[src]

Bit 7 - Rising trigger event configuration of line 7

`pub fn tr8(&self) -> TR8_R`[src]

Bit 8 - Rising trigger event configuration of line 8

`pub fn tr9(&self) -> TR9_R`[src]

Bit 9 - Rising trigger event configuration of line 9

`pub fn tr10(&self) -> TR10_R`[src]

Bit 10 - Rising trigger event configuration of line 10

`pub fn tr11(&self) -> TR11_R`[src]

Bit 11 - Rising trigger event configuration of line 11

`pub fn tr12(&self) -> TR12_R`[src]

Bit 12 - Rising trigger event configuration of line 12

`pub fn tr13(&self) -> TR13_R`[src]

Bit 13 - Rising trigger event configuration of line 13

`pub fn tr14(&self) -> TR14_R`[src]

Bit 14 - Rising trigger event configuration of line 14

`pub fn tr15(&self) -> TR15_R`[src]

Bit 15 - Rising trigger event configuration of line 15

`pub fn tr16(&self) -> TR16_R`[src]

Bit 16 - Rising trigger event configuration of line 16

`pub fn tr17(&self) -> TR17_R`[src]

Bit 17 - Rising trigger event configuration of line 17

`pub fn tr18(&self) -> TR18_R`[src]

Bit 18 - Rising trigger event configuration of line 18

`pub fn tr19(&self) -> TR19_R`[src]

Bit 19 - Rising trigger event configuration of line 19

`pub fn tr20(&self) -> TR20_R`[src]

Bit 20 - Rising trigger event configuration of line 20

`pub fn tr21(&self) -> TR21_R`[src]

Bit 21 - Rising trigger event configuration of line 21

`pub fn tr22(&self) -> TR22_R`[src]

Bit 22 - Rising trigger event configuration of line 22

`impl R<bool, TR0_A>`[src]

`pub fn variant(&self) -> TR0_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _FTSR>>`[src]

`pub fn tr0(&self) -> TR0_R`[src]

Bit 0 - Falling trigger event configuration of line 0

`pub fn tr1(&self) -> TR1_R`[src]

Bit 1 - Falling trigger event configuration of line 1

`pub fn tr2(&self) -> TR2_R`[src]

Bit 2 - Falling trigger event configuration of line 2

`pub fn tr3(&self) -> TR3_R`[src]

Bit 3 - Falling trigger event configuration of line 3

`pub fn tr4(&self) -> TR4_R`[src]

Bit 4 - Falling trigger event configuration of line 4

`pub fn tr5(&self) -> TR5_R`[src]

Bit 5 - Falling trigger event configuration of line 5

`pub fn tr6(&self) -> TR6_R`[src]

Bit 6 - Falling trigger event configuration of line 6

`pub fn tr7(&self) -> TR7_R`[src]

Bit 7 - Falling trigger event configuration of line 7

`pub fn tr8(&self) -> TR8_R`[src]

Bit 8 - Falling trigger event configuration of line 8

`pub fn tr9(&self) -> TR9_R`[src]

Bit 9 - Falling trigger event configuration of line 9

`pub fn tr10(&self) -> TR10_R`[src]

Bit 10 - Falling trigger event configuration of line 10

`pub fn tr11(&self) -> TR11_R`[src]

Bit 11 - Falling trigger event configuration of line 11

`pub fn tr12(&self) -> TR12_R`[src]

Bit 12 - Falling trigger event configuration of line 12

`pub fn tr13(&self) -> TR13_R`[src]

Bit 13 - Falling trigger event configuration of line 13

`pub fn tr14(&self) -> TR14_R`[src]

Bit 14 - Falling trigger event configuration of line 14

`pub fn tr15(&self) -> TR15_R`[src]

Bit 15 - Falling trigger event configuration of line 15

`pub fn tr16(&self) -> TR16_R`[src]

Bit 16 - Falling trigger event configuration of line 16

`pub fn tr17(&self) -> TR17_R`[src]

Bit 17 - Falling trigger event configuration of line 17

`pub fn tr18(&self) -> TR18_R`[src]

Bit 18 - Falling trigger event configuration of line 18

`pub fn tr19(&self) -> TR19_R`[src]

Bit 19 - Falling trigger event configuration of line 19

`pub fn tr20(&self) -> TR20_R`[src]

Bit 20 - Falling trigger event configuration of line 20

`pub fn tr21(&self) -> TR21_R`[src]

Bit 21 - Falling trigger event configuration of line 21

`pub fn tr22(&self) -> TR22_R`[src]

Bit 22 - Falling trigger event configuration of line 22

`impl R<bool, SWIER0_A>`[src]

`pub fn variant(&self) -> Variant<bool, SWIER0_A>`[src]

Get enumerated values variant

`pub fn is_pend(&self) -> bool`[src]

Checks if the value of the field is PEND

`impl R<u32, Reg<u32, _SWIER>>`[src]

`pub fn swier0(&self) -> SWIER0_R`[src]

Bit 0 - Software Interrupt on line 0

`pub fn swier1(&self) -> SWIER1_R`[src]

Bit 1 - Software Interrupt on line 1

`pub fn swier2(&self) -> SWIER2_R`[src]

Bit 2 - Software Interrupt on line 2

`pub fn swier3(&self) -> SWIER3_R`[src]

Bit 3 - Software Interrupt on line 3

`pub fn swier4(&self) -> SWIER4_R`[src]

Bit 4 - Software Interrupt on line 4

`pub fn swier5(&self) -> SWIER5_R`[src]

Bit 5 - Software Interrupt on line 5

`pub fn swier6(&self) -> SWIER6_R`[src]

Bit 6 - Software Interrupt on line 6

`pub fn swier7(&self) -> SWIER7_R`[src]

Bit 7 - Software Interrupt on line 7

`pub fn swier8(&self) -> SWIER8_R`[src]

Bit 8 - Software Interrupt on line 8

`pub fn swier9(&self) -> SWIER9_R`[src]

Bit 9 - Software Interrupt on line 9

`pub fn swier10(&self) -> SWIER10_R`[src]

Bit 10 - Software Interrupt on line 10

`pub fn swier11(&self) -> SWIER11_R`[src]

Bit 11 - Software Interrupt on line 11

`pub fn swier12(&self) -> SWIER12_R`[src]

Bit 12 - Software Interrupt on line 12

`pub fn swier13(&self) -> SWIER13_R`[src]

Bit 13 - Software Interrupt on line 13

`pub fn swier14(&self) -> SWIER14_R`[src]

Bit 14 - Software Interrupt on line 14

`pub fn swier15(&self) -> SWIER15_R`[src]

Bit 15 - Software Interrupt on line 15

`pub fn swier16(&self) -> SWIER16_R`[src]

Bit 16 - Software Interrupt on line 16

`pub fn swier17(&self) -> SWIER17_R`[src]

Bit 17 - Software Interrupt on line 17

`pub fn swier18(&self) -> SWIER18_R`[src]

Bit 18 - Software Interrupt on line 18

`pub fn swier19(&self) -> SWIER19_R`[src]

Bit 19 - Software Interrupt on line 19

`pub fn swier20(&self) -> SWIER20_R`[src]

Bit 20 - Software Interrupt on line 20

`pub fn swier21(&self) -> SWIER21_R`[src]

Bit 21 - Software Interrupt on line 21

`pub fn swier22(&self) -> SWIER22_R`[src]

Bit 22 - Software Interrupt on line 22

`impl R<bool, PR0_A>`[src]

`pub fn variant(&self) -> PR0_A`[src]

Get enumerated values variant

`pub fn is_not_pending(&self) -> bool`[src]

Checks if the value of the field is NOTPENDING

`pub fn is_pending(&self) -> bool`[src]

Checks if the value of the field is PENDING

`impl R<u32, Reg<u32, _PR>>`[src]

`pub fn pr0(&self) -> PR0_R`[src]

Bit 0 - Pending bit 0

`pub fn pr1(&self) -> PR1_R`[src]

Bit 1 - Pending bit 1

`pub fn pr2(&self) -> PR2_R`[src]

Bit 2 - Pending bit 2

`pub fn pr3(&self) -> PR3_R`[src]

Bit 3 - Pending bit 3

`pub fn pr4(&self) -> PR4_R`[src]

Bit 4 - Pending bit 4

`pub fn pr5(&self) -> PR5_R`[src]

Bit 5 - Pending bit 5

`pub fn pr6(&self) -> PR6_R`[src]

Bit 6 - Pending bit 6

`pub fn pr7(&self) -> PR7_R`[src]

Bit 7 - Pending bit 7

`pub fn pr8(&self) -> PR8_R`[src]

Bit 8 - Pending bit 8

`pub fn pr9(&self) -> PR9_R`[src]

Bit 9 - Pending bit 9

`pub fn pr10(&self) -> PR10_R`[src]

Bit 10 - Pending bit 10

`pub fn pr11(&self) -> PR11_R`[src]

Bit 11 - Pending bit 11

`pub fn pr12(&self) -> PR12_R`[src]

Bit 12 - Pending bit 12

`pub fn pr13(&self) -> PR13_R`[src]

Bit 13 - Pending bit 13

`pub fn pr14(&self) -> PR14_R`[src]

Bit 14 - Pending bit 14

`pub fn pr15(&self) -> PR15_R`[src]

Bit 15 - Pending bit 15

`pub fn pr16(&self) -> PR16_R`[src]

Bit 16 - Pending bit 16

`pub fn pr17(&self) -> PR17_R`[src]

Bit 17 - Pending bit 17

`pub fn pr18(&self) -> PR18_R`[src]

Bit 18 - Pending bit 18

`pub fn pr19(&self) -> PR19_R`[src]

Bit 19 - Pending bit 19

`pub fn pr20(&self) -> PR20_R`[src]

Bit 20 - Pending bit 20

`pub fn pr21(&self) -> PR21_R`[src]

Bit 21 - Pending bit 21

`pub fn pr22(&self) -> PR22_R`[src]

Bit 22 - Pending bit 22

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn cluten(&self) -> CLUTEN_R`[src]

Bit 4 - Color Look-Up Table Enable

`pub fn colken(&self) -> COLKEN_R`[src]

Bit 1 - Color Keying Enable

`pub fn len(&self) -> LEN_R`[src]

Bit 0 - Layer Enable

`impl R<u32, Reg<u32, _WHPCR>>`[src]

`pub fn whsppos(&self) -> WHSPPOS_R`[src]

Bits 16:27 - Window Horizontal Stop Position

`pub fn whstpos(&self) -> WHSTPOS_R`[src]

Bits 0:11 - Window Horizontal Start Position

`impl R<u32, Reg<u32, _WVPCR>>`[src]

`pub fn wvsppos(&self) -> WVSPPOS_R`[src]

Bits 16:26 - Window Vertical Stop Position

`pub fn wvstpos(&self) -> WVSTPOS_R`[src]

Bits 0:10 - Window Vertical Start Position

`impl R<u32, Reg<u32, _CKCR>>`[src]

`pub fn ckred(&self) -> CKRED_R`[src]

Bits 16:23 - Color Key Red value

`pub fn ckgreen(&self) -> CKGREEN_R`[src]

Bits 8:15 - Color Key Green value

`pub fn ckblue(&self) -> CKBLUE_R`[src]

Bits 0:7 - Color Key Blue value

`impl R<u32, Reg<u32, _PFCR>>`[src]

`pub fn pf(&self) -> PF_R`[src]

Bits 0:2 - Pixel Format

`impl R<u32, Reg<u32, _CACR>>`[src]

`pub fn consta(&self) -> CONSTA_R`[src]

Bits 0:7 - Constant Alpha

`impl R<u32, Reg<u32, _DCCR>>`[src]

`pub fn dcalpha(&self) -> DCALPHA_R`[src]

Bits 24:31 - Default Color Alpha

`pub fn dcred(&self) -> DCRED_R`[src]

Bits 16:23 - Default Color Red

`pub fn dcgreen(&self) -> DCGREEN_R`[src]

Bits 8:15 - Default Color Green

`pub fn dcblue(&self) -> DCBLUE_R`[src]

Bits 0:7 - Default Color Blue

`impl R<u32, Reg<u32, _BFCR>>`[src]

`pub fn bf1(&self) -> BF1_R`[src]

Bits 8:10 - Blending Factor 1

`pub fn bf2(&self) -> BF2_R`[src]

Bits 0:2 - Blending Factor 2

`impl R<u32, Reg<u32, _CFBAR>>`[src]

`pub fn cfbadd(&self) -> CFBADD_R`[src]

Bits 0:31 - Color Frame Buffer Start Address

`impl R<u32, Reg<u32, _CFBLR>>`[src]

`pub fn cfbp(&self) -> CFBP_R`[src]

Bits 16:28 - Color Frame Buffer Pitch in bytes

`pub fn cfbll(&self) -> CFBLL_R`[src]

Bits 0:12 - Color Frame Buffer Line Length

`impl R<u32, Reg<u32, _CFBLNR>>`[src]

`pub fn cfblnbr(&self) -> CFBLNBR_R`[src]

Bits 0:10 - Frame Buffer Line Number

`impl R<u32, Reg<u32, _SSCR>>`[src]

`pub fn hsw(&self) -> HSW_R`[src]

Bits 16:25 - Horizontal Synchronization Width (in units of pixel clock period)

`pub fn vsh(&self) -> VSH_R`[src]

Bits 0:10 - Vertical Synchronization Height (in units of horizontal scan line)

`impl R<u32, Reg<u32, _BPCR>>`[src]

`pub fn ahbp(&self) -> AHBP_R`[src]

Bits 16:25 - Accumulated Horizontal back porch (in units of pixel clock period)

`pub fn avbp(&self) -> AVBP_R`[src]

Bits 0:10 - Accumulated Vertical back porch (in units of horizontal scan line)

`impl R<u32, Reg<u32, _AWCR>>`[src]

`pub fn aaw(&self) -> AAW_R`[src]

Bits 16:25 - Accumulated Active Width (in units of pixel clock period)

`pub fn aah(&self) -> AAH_R`[src]

Bits 0:10 - Accumulated Active Height (in units of horizontal scan line)

`impl R<u32, Reg<u32, _TWCR>>`[src]

`pub fn totalw(&self) -> TOTALW_R`[src]

Bits 16:25 - Total Width (in units of pixel clock period)

`pub fn totalh(&self) -> TOTALH_R`[src]

Bits 0:10 - Total Height (in units of horizontal scan line)

`impl R<u32, Reg<u32, _GCR>>`[src]

`pub fn hspol(&self) -> HSPOL_R`[src]

Bit 31 - Horizontal Synchronization Polarity

`pub fn vspol(&self) -> VSPOL_R`[src]

Bit 30 - Vertical Synchronization Polarity

`pub fn depol(&self) -> DEPOL_R`[src]

Bit 29 - Data Enable Polarity

`pub fn pcpol(&self) -> PCPOL_R`[src]

Bit 28 - Pixel Clock Polarity

`pub fn den(&self) -> DEN_R`[src]

Bit 16 - Dither Enable

`pub fn drw(&self) -> DRW_R`[src]

Bits 12:14 - Dither Red Width

`pub fn dgw(&self) -> DGW_R`[src]

Bits 8:10 - Dither Green Width

`pub fn dbw(&self) -> DBW_R`[src]

Bits 4:6 - Dither Blue Width

`pub fn ltdcen(&self) -> LTDCEN_R`[src]

Bit 0 - LCD-TFT controller enable bit

`impl R<u32, Reg<u32, _SRCR>>`[src]

`pub fn vbr(&self) -> VBR_R`[src]

Bit 1 - Vertical Blanking Reload

`pub fn imr(&self) -> IMR_R`[src]

Bit 0 - Immediate Reload

`impl R<u32, Reg<u32, _BCCR>>`[src]

`pub fn bc(&self) -> BC_R`[src]

Bits 0:23 - Background Color Red value

`impl R<u32, Reg<u32, _IER>>`[src]

`pub fn rrie(&self) -> RRIE_R`[src]

Bit 3 - Register Reload interrupt enable

`pub fn terrie(&self) -> TERRIE_R`[src]

Bit 2 - Transfer Error Interrupt Enable

`pub fn fuie(&self) -> FUIE_R`[src]

Bit 1 - FIFO Underrun Interrupt Enable

`pub fn lie(&self) -> LIE_R`[src]

Bit 0 - Line Interrupt Enable

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn rrif(&self) -> RRIF_R`[src]

Bit 3 - Register Reload Interrupt Flag

`pub fn terrif(&self) -> TERRIF_R`[src]

Bit 2 - Transfer Error interrupt flag

`pub fn fuif(&self) -> FUIF_R`[src]

Bit 1 - FIFO Underrun Interrupt flag

`pub fn lif(&self) -> LIF_R`[src]

Bit 0 - Line Interrupt flag

`impl R<u32, Reg<u32, _LIPCR>>`[src]

`pub fn lipos(&self) -> LIPOS_R`[src]

Bits 0:10 - Line Interrupt Position

`impl R<u32, Reg<u32, _CPSR>>`[src]

`pub fn cxpos(&self) -> CXPOS_R`[src]

Bits 16:31 - Current X Position

`pub fn cypos(&self) -> CYPOS_R`[src]

Bits 0:15 - Current Y Position

`impl R<u32, Reg<u32, _CDSR>>`[src]

`pub fn hsyncs(&self) -> HSYNCS_R`[src]

`impl R<u8, SYNCEN_A>`[src]

`pub fn variant(&self) -> Variant<u8, SYNCEN_A>`[src]

Get enumerated values variant

`pub fn is_asynchronous(&self) -> bool`[src]

Checks if the value of the field is ASYNCHRONOUS

`pub fn is_internal(&self) -> bool`[src]

Checks if the value of the field is INTERNAL

`pub fn is_bit10(&self) -> bool`[src]

Checks if the value of the field is BIT10

`pub fn is_bit16(&self) -> bool`[src]

Checks if the value of the field is BIT16

`pub fn is_bit20(&self) -> bool`[src]

Checks if the value of the field is BIT20

`pub fn is_bit24(&self) -> bool`[src]

Checks if the value of the field is BIT24

`pub fn is_bit32(&self) -> bool`[src]

Checks if the value of the field is BIT32

`impl R<u8, PRTCFG_A>`[src]

`pub fn variant(&self) -> Variant<u8, PRTCFG_A>`[src]

Get enumerated values variant

`pub fn is_free(&self) -> bool`[src]

Checks if the value of the field is FREE

`pub fn is_spdif(&self) -> bool`[src]

Checks if the value of the field is SPDIF

`pub fn is_ac97(&self) -> bool`[src]

Checks if the value of the field is AC97

`impl R<u8, MODE_A>`[src]

`pub fn variant(&self) -> MODE_A`[src]

Get enumerated values variant

`pub fn is_master_tx(&self) -> bool`[src]

Checks if the value of the field is MASTERTX

`pub fn is_master_rx(&self) -> bool`[src]

Checks if the value of the field is MASTERRX

`pub fn is_slave_tx(&self) -> bool`[src]

Checks if the value of the field is SLAVETX

`pub fn is_slave_rx(&self) -> bool`[src]

Checks if the value of the field is SLAVERX

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn mcjdiv(&self) -> MCJDIV_R`[src]

Bits 20:23 - Master clock divider

`pub fn nodiv(&self) -> NODIV_R`[src]

Bit 19 - No divider

`pub fn dmaen(&self) -> DMAEN_R`[src]

Bit 17 - DMA enable

`pub fn saien(&self) -> SAIEN_R`[src]

Bit 16 - Audio block A enable

`pub fn outdriv(&self) -> OUTDRIV_R`[src]

Bit 13 - Output drive

`pub fn mono(&self) -> MONO_R`[src]

Bit 12 - Mono mode

`pub fn syncen(&self) -> SYNCEN_R`[src]

Bits 10:11 - Synchronization enable

`pub fn ckstr(&self) -> CKSTR_R`[src]

Bit 9 - Clock strobing edge

`pub fn lsbfirst(&self) -> LSBFIRST_R`[src]

Bit 8 - Least significant bit first

`pub fn ds(&self) -> DS_R`[src]

Bits 5:7 - Data size

`pub fn prtcfg(&self) -> PRTCFG_R`[src]

Bits 2:3 - Protocol configuration

`pub fn mode(&self) -> MODE_R`[src]

Bits 0:1 - Audio block mode

`impl R<u8, COMP_A>`[src]

`pub fn variant(&self) -> Variant<u8, COMP_A>`[src]

`pub fn is_quarter2(&self) -> bool`[src]

Checks if the value of the field is QUARTER2

`pub fn is_quarter3(&self) -> bool`[src]

Checks if the value of the field is QUARTER3

`pub fn is_full(&self) -> bool`[src]

Checks if the value of the field is FULL

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn comp(&self) -> COMP_R`[src]

Bits 14:15 - Companding mode

`pub fn cpl(&self) -> CPL_R`[src]

Bit 13 - Complement bit

`pub fn mutecn(&self) -> MUTECN_R`[src]

Bits 7:12 - Mute counter

`pub fn muteval(&self) -> MUTEVAL_R`[src]

Bit 6 - Mute value

`pub fn mute(&self) -> MUTE_R`[src]

Bit 5 - Mute

`pub fn tris(&self) -> TRIS_R`[src]

Bit 4 - Tristate management on data line

`pub fn fflush(&self) -> FFLUSH_R`[src]

Bit 3 - FIFO flush

`pub fn fth(&self) -> FTH_R`[src]

Bits 0:2 - FIFO threshold

`impl R<bool, FSOFF_A>`[src]

`pub fn variant(&self) -> FSOFF_A`[src]

Get enumerated values variant

`pub fn is_on_first(&self) -> bool`[src]

Checks if the value of the field is ONFIRST

`pub fn is_before_first(&self) -> bool`[src]

Checks if the value of the field is BEFOREFIRST

`impl R<bool, FSPOL_A>`[src]

`pub fn variant(&self) -> FSPOL_A`[src]

Get enumerated values variant

`pub fn is_falling_edge(&self) -> bool`[src]

Checks if the value of the field is FALLINGEDGE

`pub fn is_rising_edge(&self) -> bool`[src]

Checks if the value of the field is RISINGEDGE

`impl R<u32, Reg<u32, _FRCR>>`[src]

`pub fn fsoff(&self) -> FSOFF_R`[src]

Bit 18 - Frame synchronization offset

`pub fn fspol(&self) -> FSPOL_R`[src]

Bit 17 - Frame synchronization polarity

`pub fn fsdef(&self) -> FSDEF_R`[src]

Bit 16 - Frame synchronization definition

`pub fn fsall(&self) -> FSALL_R`[src]

Bits 8:14 - Frame synchronization active level length

`pub fn frl(&self) -> FRL_R`[src]

Bits 0:7 - Frame length

`impl R<u16, SLOTEN_A>`[src]

`pub fn variant(&self) -> Variant<u16, SLOTEN_A>`[src]

Get enumerated values variant

`pub fn is_inactive(&self) -> bool`[src]

Checks if the value of the field is INACTIVE

`pub fn is_active(&self) -> bool`[src]

Checks if the value of the field is ACTIVE

`impl R<u8, SLOTSZ_A>`[src]

`pub fn variant(&self) -> Variant<u8, SLOTSZ_A>`[src]

Get enumerated values variant

`pub fn is_data_size(&self) -> bool`[src]

Checks if the value of the field is DATASIZE

`pub fn is_bit16(&self) -> bool`[src]

Checks if the value of the field is BIT16

`pub fn is_bit32(&self) -> bool`[src]

Checks if the value of the field is BIT32

`impl R<u32, Reg<u32, _SLOTR>>`[src]

`pub fn sloten(&self) -> SLOTEN_R`[src]

`impl R<u32, Reg<u32, _IM>>`[src]

`pub fn lfsdetie(&self) -> LFSDETIE_R`[src]

Bit 6 - Late frame synchronization detection interrupt enable

`pub fn afsdetie(&self) -> AFSDETIE_R`[src]

Bit 5 - Anticipated frame synchronization detection interrupt enable

`pub fn cnrdyie(&self) -> CNRDYIE_R`[src]

Bit 4 - Codec not ready interrupt enable

`pub fn freqie(&self) -> FREQIE_R`[src]

Bit 3 - FIFO request interrupt enable

`pub fn wckcfgie(&self) -> WCKCFGIE_R`[src]

Bit 2 - Wrong clock configuration interrupt enable

`pub fn mutedetie(&self) -> MUTEDETIE_R`[src]

Bit 1 - Mute detection interrupt enable

`pub fn ovrudrie(&self) -> OVRUDRIE_R`[src]

Bit 0 - Overrun/underrun interrupt enable

`impl R<u8, FLVL_A>`[src]

`pub fn variant(&self) -> Variant<u8, FLVL_A>`[src]

Get enumerated values variant

`pub fn is_empty(&self) -> bool`[src]

Checks if the value of the field is EMPTY

`pub fn is_quarter1(&self) -> bool`[src]

Checks if the value of the field is QUARTER1

`pub fn is_quarter2(&self) -> bool`[src]

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn flvl(&self) -> FLVL_R`[src]

Bits 16:18 - FIFO level threshold

`pub fn lfsdet(&self) -> LFSDET_R`[src]

Bit 6 - Late frame synchronization detection

`pub fn afsdet(&self) -> AFSDET_R`[src]

Bit 5 - Anticipated frame synchronization detection

`pub fn cnrdy(&self) -> CNRDY_R`[src]

Bit 4 - Codec not ready

`pub fn freq(&self) -> FREQ_R`[src]

Bit 3 - FIFO request

`pub fn wckcfg(&self) -> WCKCFG_R`[src]

`pub fn ccnrdy(&self) -> CCNRDY_R`[src]

Bit 4 - Clear codec not ready flag

`pub fn cwckcfg(&self) -> CWCKCFG_R`[src]

Bit 2 - Clear wrong clock configuration flag

`pub fn cmutedet(&self) -> CMUTEDET_R`[src]

Bit 1 - Mute detection flag

`pub fn covrudr(&self) -> COVRUDR_R`[src]

Bit 0 - Clear overrun / underrun

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn data(&self) -> DATA_R`[src]

Bits 0:31 - Data

`impl R<u32, Reg<u32, _GCR>>`[src]

`pub fn syncin(&self) -> SYNCIN_R`[src]

Bits 0:1 - Synchronization inputs

`pub fn syncout(&self) -> SYNCOUT_R`[src]

Bits 4:5 - Synchronization outputs

`impl R<u8, MODE_A>`[src]

`pub fn variant(&self) -> MODE_A`[src]

Get enumerated values variant

`pub fn is_memory_to_memory(&self) -> bool`[src]

`impl R<bool, TEIE_A>`[src]

`pub fn variant(&self) -> TEIE_A`[src]

`pub fn is_suspended(&self) -> bool`[src]

Checks if the value of the field is SUSPENDED

`impl R<bool, START_A>`[src]

`pub fn variant(&self) -> Variant<bool, START_A>`[src]

Get enumerated values variant

`pub fn is_start(&self) -> bool`[src]

Checks if the value of the field is START

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn mode(&self) -> MODE_R`[src]

Bits 16:17 - DMA2D mode

`pub fn ceie(&self) -> CEIE_R`[src]

Bit 13 - Configuration Error Interrupt Enable

`pub fn ctcie(&self) -> CTCIE_R`[src]

Bit 12 - CLUT transfer complete interrupt enable

`pub fn caeie(&self) -> CAEIE_R`[src]

Bit 11 - CLUT access error interrupt enable

`pub fn twie(&self) -> TWIE_R`[src]

Bit 10 - Transfer watermark interrupt enable

`pub fn tcie(&self) -> TCIE_R`[src]

Bit 9 - Transfer complete interrupt enable

`pub fn teie(&self) -> TEIE_R`[src]

Bit 8 - Transfer error interrupt enable

`pub fn abort(&self) -> ABORT_R`[src]

Bit 2 - Abort

`pub fn susp(&self) -> SUSP_R`[src]

Bit 1 - Suspend

`pub fn start(&self) -> START_R`[src]

Bit 0 - Start

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn ceif(&self) -> CEIF_R`[src]

Bit 5 - Configuration error interrupt flag

`pub fn ctcif(&self) -> CTCIF_R`[src]

Bit 4 - CLUT transfer complete interrupt flag

`pub fn caeif(&self) -> CAEIF_R`[src]

Bit 3 - CLUT access error interrupt flag

`pub fn twif(&self) -> TWIF_R`[src]

`pub fn caecif(&self) -> CAECIF_R`[src]

Bit 3 - Clear CLUT access error interrupt flag

`pub fn ctwif(&self) -> CTWIF_R`[src]

Bit 2 - Clear transfer watermark interrupt flag

`pub fn ctcif(&self) -> CTCIF_R`[src]

Bit 1 - Clear transfer complete interrupt flag

`pub fn cteif(&self) -> CTEIF_R`[src]

Bit 0 - Clear Transfer error interrupt flag

`impl R<u32, Reg<u32, _FGMAR>>`[src]

`pub fn ma(&self) -> MA_R`[src]

Bits 0:31 - Memory address

`impl R<u32, Reg<u32, _FGOR>>`[src]

`pub fn lo(&self) -> LO_R`[src]

Bits 0:13 - Line offset

`impl R<u32, Reg<u32, _BGMAR>>`[src]

`pub fn ma(&self) -> MA_R`[src]

Bits 0:31 - Memory address

`impl R<u32, Reg<u32, _BGOR>>`[src]

`pub fn lo(&self) -> LO_R`[src]

Bits 0:13 - Line offset

`impl R<u8, AM_A>`[src]

`pub fn variant(&self) -> Variant<u8, AM_A>`[src]

Get enumerated values variant

`pub fn is_no_modify(&self) -> bool`[src]

Checks if the value of the field is NOMODIFY

`pub fn is_replace(&self) -> bool`[src]

Checks if the value of the field is REPLACE

`pub fn is_multiply(&self) -> bool`[src]

Checks if the value of the field is MULTIPLY

`impl R<bool, START_A>`[src]

`pub fn variant(&self) -> Variant<bool, START_A>`[src]

Get enumerated values variant

`pub fn is_start(&self) -> bool`[src]

Checks if the value of the field is START

`impl R<bool, CCM_A>`[src]

`pub fn variant(&self) -> CCM_A`[src]

Get enumerated values variant

`pub fn is_argb8888(&self) -> bool`[src]

Checks if the value of the field is ARGB8888

`pub fn is_rgb888(&self) -> bool`[src]

Checks if the value of the field is RGB888

`impl R<u8, CM_A>`[src]

`pub fn variant(&self) -> Variant<u8, CM_A>`[src]

Get enumerated values variant

`pub fn is_argb8888(&self) -> bool`[src]

Checks if the value of the field is ARGB8888

`pub fn is_rgb888(&self) -> bool`[src]

Checks if the value of the field is RGB888

`pub fn is_rgb565(&self) -> bool`[src]

Checks if the value of the field is RGB565

`pub fn is_argb1555(&self) -> bool`[src]

Checks if the value of the field is ARGB1555

`pub fn is_argb4444(&self) -> bool`[src]

Checks if the value of the field is ARGB4444

`pub fn is_l8(&self) -> bool`[src]

Checks if the value of the field is L8

`pub fn is_al44(&self) -> bool`[src]

Checks if the value of the field is AL44

`pub fn is_al88(&self) -> bool`[src]

Checks if the value of the field is AL88

`pub fn is_l4(&self) -> bool`[src]

Checks if the value of the field is L4

`pub fn is_a8(&self) -> bool`[src]

Checks if the value of the field is A8

`pub fn is_a4(&self) -> bool`[src]

Checks if the value of the field is A4

`impl R<u32, Reg<u32, _FGPFCCR>>`[src]

`pub fn alpha(&self) -> ALPHA_R`[src]

Bits 24:31 - Alpha value

`pub fn am(&self) -> AM_R`[src]

Bits 16:17 - Alpha mode

`pub fn cs(&self) -> CS_R`[src]

Bits 8:15 - CLUT size

`pub fn start(&self) -> START_R`[src]

Bit 5 - Start

`pub fn ccm(&self) -> CCM_R`[src]

Bit 4 - CLUT color mode

`pub fn cm(&self) -> CM_R`[src]

Bits 0:3 - Color mode

`impl R<u32, Reg<u32, _FGCOLR>>`[src]

`pub fn red(&self) -> RED_R`[src]

Bits 16:23 - Red Value

`pub fn green(&self) -> GREEN_R`[src]

Bits 8:15 - Green Value

`pub fn blue(&self) -> BLUE_R`[src]

Bits 0:7 - Blue Value

`impl R<u8, AM_A>`[src]

`pub fn variant(&self) -> Variant<u8, AM_A>`[src]

Get enumerated values variant

`pub fn is_no_modify(&self) -> bool`[src]

Checks if the value of the field is NOMODIFY

`pub fn is_replace(&self) -> bool`[src]

Checks if the value of the field is REPLACE

`pub fn is_multiply(&self) -> bool`[src]

Checks if the value of the field is MULTIPLY

`impl R<bool, START_A>`[src]

`pub fn variant(&self) -> Variant<bool, START_A>`[src]

Get enumerated values variant

`pub fn is_start(&self) -> bool`[src]

Checks if the value of the field is START

`impl R<bool, CCM_A>`[src]

`pub fn variant(&self) -> CCM_A`[src]

Get enumerated values variant

`pub fn is_argb8888(&self) -> bool`[src]

Checks if the value of the field is ARGB8888

`pub fn is_rgb888(&self) -> bool`[src]

Checks if the value of the field is RGB888

`impl R<u8, CM_A>`[src]

`pub fn variant(&self) -> Variant<u8, CM_A>`[src]

Get enumerated values variant

`pub fn is_argb8888(&self) -> bool`[src]

Checks if the value of the field is ARGB8888

`pub fn is_rgb888(&self) -> bool`[src]

Checks if the value of the field is RGB888

`pub fn is_rgb565(&self) -> bool`[src]

Checks if the value of the field is RGB565

`pub fn is_argb1555(&self) -> bool`[src]

Checks if the value of the field is ARGB1555

`pub fn is_argb4444(&self) -> bool`[src]

Checks if the value of the field is ARGB4444

`pub fn is_l8(&self) -> bool`[src]

Checks if the value of the field is L8

`pub fn is_al44(&self) -> bool`[src]

Checks if the value of the field is AL44

`pub fn is_al88(&self) -> bool`[src]

Checks if the value of the field is AL88

`pub fn is_l4(&self) -> bool`[src]

Checks if the value of the field is L4

`pub fn is_a8(&self) -> bool`[src]

Checks if the value of the field is A8

`pub fn is_a4(&self) -> bool`[src]

Checks if the value of the field is A4

`impl R<u32, Reg<u32, _BGPFCCR>>`[src]

`pub fn alpha(&self) -> ALPHA_R`[src]

Bits 24:31 - Alpha value

`pub fn am(&self) -> AM_R`[src]

Bits 16:17 - Alpha mode

`pub fn cs(&self) -> CS_R`[src]

Bits 8:15 - CLUT size

`pub fn start(&self) -> START_R`[src]

Bit 5 - Start

`pub fn ccm(&self) -> CCM_R`[src]

Bit 4 - CLUT Color mode

`pub fn cm(&self) -> CM_R`[src]

Bits 0:3 - Color mode

`impl R<u32, Reg<u32, _BGCOLR>>`[src]

`pub fn red(&self) -> RED_R`[src]

Bits 16:23 - Red Value

`pub fn green(&self) -> GREEN_R`[src]

Bits 8:15 - Green Value

`pub fn blue(&self) -> BLUE_R`[src]

Bits 0:7 - Blue Value

`impl R<u32, Reg<u32, _FGCMAR>>`[src]

`pub fn ma(&self) -> MA_R`[src]

Bits 0:31 - Memory Address

`impl R<u32, Reg<u32, _BGCMAR>>`[src]

`pub fn ma(&self) -> MA_R`[src]

Bits 0:31 - Memory address

`impl R<u8, CM_A>`[src]

`pub fn variant(&self) -> Variant<u8, CM_A>`[src]

Get enumerated values variant

`pub fn is_argb8888(&self) -> bool`[src]

Checks if the value of the field is ARGB8888

`pub fn is_rgb888(&self) -> bool`[src]

Checks if the value of the field is RGB888

`pub fn is_rgb565(&self) -> bool`[src]

Checks if the value of the field is RGB565

`pub fn is_argb1555(&self) -> bool`[src]

Checks if the value of the field is ARGB1555

`pub fn is_argb4444(&self) -> bool`[src]

Checks if the value of the field is ARGB4444

`impl R<u32, Reg<u32, _OPFCCR>>`[src]

`pub fn cm(&self) -> CM_R`[src]

Bits 0:2 - Color mode

`impl R<u32, Reg<u32, _OCOLR>>`[src]

`pub fn aplha(&self) -> APLHA_R`[src]

Bits 24:31 - Alpha Channel Value

`pub fn red(&self) -> RED_R`[src]

Bits 16:23 - Red Value

`pub fn green(&self) -> GREEN_R`[src]

Bits 8:15 - Green Value

`pub fn blue(&self) -> BLUE_R`[src]

Bits 0:7 - Blue Value

`impl R<u32, Reg<u32, _OMAR>>`[src]

`pub fn ma(&self) -> MA_R`[src]

Bits 0:31 - Memory Address

`impl R<u32, Reg<u32, _OOR>>`[src]

`pub fn lo(&self) -> LO_R`[src]

Bits 0:13 - Line Offset

`impl R<u32, Reg<u32, _NLR>>`[src]

`pub fn pl(&self) -> PL_R`[src]

Bits 16:29 - Pixel per lines

`pub fn nl(&self) -> NL_R`[src]

Bits 0:15 - Number of lines

`impl R<u32, Reg<u32, _LWR>>`[src]

`pub fn lw(&self) -> LW_R`[src]

Bits 0:15 - Line watermark

`impl R<bool, EN_A>`[src]

`pub fn variant(&self) -> EN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _AMTCR>>`[src]

`pub fn dt(&self) -> DT_R`[src]

Bits 8:15 - Dead Time

`pub fn en(&self) -> EN_R`[src]

Bit 0 - Enable

`impl R<u32, Reg<u32, _FGCLUT>>`[src]

`pub fn aplha(&self) -> APLHA_R`[src]

Bits 24:31 - APLHA

`pub fn red(&self) -> RED_R`[src]

Bits 16:23 - RED

`pub fn green(&self) -> GREEN_R`[src]

Bits 8:15 - GREEN

`pub fn blue(&self) -> BLUE_R`[src]

Bits 0:7 - BLUE

`impl R<u32, Reg<u32, _BGCLUT>>`[src]

`pub fn aplha(&self) -> APLHA_R`[src]

Bits 24:31 - APLHA

`pub fn red(&self) -> RED_R`[src]

Bits 16:23 - RED

`pub fn green(&self) -> GREEN_R`[src]

Bits 8:15 - GREEN

`pub fn blue(&self) -> BLUE_R`[src]

Bits 0:7 - BLUE

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn prescaler(&self) -> PRESCALER_R`[src]

Bits 24:31 - Clock prescaler

`pub fn pmm(&self) -> PMM_R`[src]

Bit 23 - Polling match mode

`pub fn apms(&self) -> APMS_R`[src]

Bit 22 - Automatic poll mode stop

`pub fn toie(&self) -> TOIE_R`[src]

Bit 20 - TimeOut interrupt enable

`pub fn smie(&self) -> SMIE_R`[src]

Bit 19 - Status match interrupt enable

`pub fn ftie(&self) -> FTIE_R`[src]

Bit 18 - FIFO threshold interrupt enable

`pub fn tcie(&self) -> TCIE_R`[src]

Bit 17 - Transfer complete interrupt enable

`pub fn teie(&self) -> TEIE_R`[src]

Bit 16 - Transfer error interrupt enable

`pub fn fthres(&self) -> FTHRES_R`[src]

Bits 8:12 - IFO threshold level

`pub fn fsel(&self) -> FSEL_R`[src]

Bit 7 - FLASH memory selection

`pub fn dfm(&self) -> DFM_R`[src]

Bit 6 - Dual-flash mode

`pub fn sshift(&self) -> SSHIFT_R`[src]

Bit 4 - Sample shift

`pub fn tcen(&self) -> TCEN_R`[src]

Bit 3 - Timeout counter enable

`pub fn dmaen(&self) -> DMAEN_R`[src]

Bit 2 - DMA enable

`pub fn abort(&self) -> ABORT_R`[src]

Bit 1 - Abort request

`pub fn en(&self) -> EN_R`[src]

Bit 0 - Enable

`impl R<u32, Reg<u32, _DCR>>`[src]

`pub fn fsize(&self) -> FSIZE_R`[src]

Bits 16:20 - FLASH memory size

`pub fn csht(&self) -> CSHT_R`[src]

Bits 8:10 - Chip select high time

`pub fn ckmode(&self) -> CKMODE_R`[src]

Bit 0 - Mode 0 / mode 3

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn flevel(&self) -> FLEVEL_R`[src]

Bits 8:14 - FIFO level

`pub fn busy(&self) -> BUSY_R`[src]

Bit 5 - Busy

`pub fn tof(&self) -> TOF_R`[src]

Bit 4 - Timeout flag

`pub fn smf(&self) -> SMF_R`[src]

Bit 3 - Status match flag

`pub fn ftf(&self) -> FTF_R`[src]

Bit 2 - FIFO threshold flag

`pub fn tcf(&self) -> TCF_R`[src]

Bit 1 - Transfer complete flag

`pub fn tef(&self) -> TEF_R`[src]

Bit 0 - Transfer error flag

`impl R<u32, Reg<u32, _FCR>>`[src]

`pub fn ctof(&self) -> CTOF_R`[src]

Bit 4 - Clear timeout flag

`pub fn csmf(&self) -> CSMF_R`[src]

Bit 3 - Clear status match flag

`pub fn ctcf(&self) -> CTCF_R`[src]

Bit 1 - Clear transfer complete flag

`pub fn ctef(&self) -> CTEF_R`[src]

Bit 0 - Clear transfer error flag

`impl R<u32, Reg<u32, _DLR>>`[src]

`pub fn dl(&self) -> DL_R`[src]

Bits 0:31 - Data length

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn ddrm(&self) -> DDRM_R`[src]

Bit 31 - Double data rate mode

`pub fn dhhc(&self) -> DHHC_R`[src]

Bit 30 - DDR hold half cycle

`pub fn sioo(&self) -> SIOO_R`[src]

Bit 28 - Send instruction only once mode

`pub fn fmode(&self) -> FMODE_R`[src]

Bits 26:27 - Functional mode

`pub fn dmode(&self) -> DMODE_R`[src]

Bits 24:25 - Data mode

`pub fn dcyc(&self) -> DCYC_R`[src]

Bits 18:22 - Number of dummy cycles

`pub fn absize(&self) -> ABSIZE_R`[src]

Bits 16:17 - Alternate bytes size

`pub fn abmode(&self) -> ABMODE_R`[src]

Bits 14:15 - Alternate bytes mode

`pub fn adsize(&self) -> ADSIZE_R`[src]

Bits 12:13 - Address size

`pub fn admode(&self) -> ADMODE_R`[src]

Bits 10:11 - Address mode

`pub fn imode(&self) -> IMODE_R`[src]

Bits 8:9 - Instruction mode

`pub fn instruction(&self) -> INSTRUCTION_R`[src]

Bits 0:7 - Instruction

`impl R<u32, Reg<u32, _AR>>`[src]

`pub fn address(&self) -> ADDRESS_R`[src]

Bits 0:31 - Address

`impl R<u32, Reg<u32, _ABR>>`[src]

`pub fn alternate(&self) -> ALTERNATE_R`[src]

Bits 0:31 - ALTERNATE

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn data(&self) -> DATA_R`[src]

Bits 0:31 - Data

`impl R<u32, Reg<u32, _PSMKR>>`[src]

`pub fn mask(&self) -> MASK_R`[src]

Bits 0:31 - Status mask

`impl R<u32, Reg<u32, _PSMAR>>`[src]

`pub fn match_(&self) -> MATCH_R`[src]

Bits 0:31 - Status match

`impl R<u32, Reg<u32, _PIR>>`[src]

`pub fn interval(&self) -> INTERVAL_R`[src]

Bits 0:15 - Polling interval

`impl R<u32, Reg<u32, _LPTR>>`[src]

`pub fn timeout(&self) -> TIMEOUT_R`[src]

Bits 0:15 - Timeout period

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn txeom(&self) -> TXEOM_R`[src]

Bit 2 - Tx End Of Message

`pub fn txsom(&self) -> TXSOM_R`[src]

Bit 1 - Tx start of message

`pub fn cecen(&self) -> CECEN_R`[src]

Bit 0 - CEC Enable

`impl R<u32, Reg<u32, _CFGR>>`[src]

`pub fn sft(&self) -> SFT_R`[src]

Bits 0:2 - Signal Free Time

`pub fn rxtol(&self) -> RXTOL_R`[src]

Bit 3 - Rx-Tolerance

`pub fn brestp(&self) -> BRESTP_R`[src]

Bit 4 - Rx-stop on bit rising error

`pub fn bregen(&self) -> BREGEN_R`[src]

Bit 5 - Generate error-bit on bit rising error

`pub fn lbpegen(&self) -> LBPEGEN_R`[src]

Bit 6 - Generate Error-Bit on Long Bit Period Error

`pub fn brdnogen(&self) -> BRDNOGEN_R`[src]

Bit 7 - Avoid Error-Bit Generation in Broadcast

`pub fn sftop(&self) -> SFTOP_R`[src]

Bit 8 - SFT Option Bit

`pub fn oar(&self) -> OAR_R`[src]

Bits 16:30 - Own addresses configuration

`pub fn lstn(&self) -> LSTN_R`[src]

Bit 31 - Listen mode

`impl R<u32, Reg<u32, _RXDR>>`[src]

`pub fn rxdr(&self) -> RXDR_R`[src]

Bits 0:7 - CEC Rx Data Register

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn txacke(&self) -> TXACKE_R`[src]

Bit 12 - Tx-Missing acknowledge error

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 11 - Tx-Error

`pub fn txudr(&self) -> TXUDR_R`[src]

Bit 10 - Tx-Buffer Underrun

`pub fn txend(&self) -> TXEND_R`[src]

Bit 9 - End of Transmission

`pub fn txbr(&self) -> TXBR_R`[src]

Bit 8 - Tx-Byte Request

`pub fn arblst(&self) -> ARBLST_R`[src]

Bit 7 - Arbitration Lost

`pub fn rxacke(&self) -> RXACKE_R`[src]

Bit 6 - Rx-Missing Acknowledge

`pub fn lbpe(&self) -> LBPE_R`[src]

Bit 5 - Rx-Long Bit Period Error

`pub fn sbpe(&self) -> SBPE_R`[src]

Bit 4 - Rx-Short Bit period error

`pub fn bre(&self) -> BRE_R`[src]

Bit 3 - Rx-Bit rising error

`pub fn rxovr(&self) -> RXOVR_R`[src]

Bit 2 - Rx-Overrun

`pub fn rxend(&self) -> RXEND_R`[src]

Bit 1 - End Of Reception

`pub fn rxbr(&self) -> RXBR_R`[src]

Bit 0 - Rx-Byte Received

`impl R<u32, Reg<u32, _IER>>`[src]

`pub fn txackie(&self) -> TXACKIE_R`[src]

Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable

`pub fn txerrie(&self) -> TXERRIE_R`[src]

Bit 11 - Tx-Error Interrupt Enable

`pub fn txudrie(&self) -> TXUDRIE_R`[src]

Bit 10 - Tx-Underrun interrupt enable

`pub fn txendie(&self) -> TXENDIE_R`[src]

Bit 9 - Tx-End of message interrupt enable

`pub fn txbrie(&self) -> TXBRIE_R`[src]

Bit 8 - Tx-Byte Request Interrupt Enable

`pub fn arblstie(&self) -> ARBLSTIE_R`[src]

Bit 7 - Arbitration Lost Interrupt Enable

`pub fn rxackie(&self) -> RXACKIE_R`[src]

Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable

`pub fn lbpeie(&self) -> LBPEIE_R`[src]

Bit 5 - Long Bit Period Error Interrupt Enable

`pub fn sbpeie(&self) -> SBPEIE_R`[src]

Bit 4 - Short Bit Period Error Interrupt Enable

`pub fn breie(&self) -> BREIE_R`[src]

Bit 3 - Bit Rising Error Interrupt Enable

`pub fn rxovrie(&self) -> RXOVRIE_R`[src]

Bit 2 - Rx-Buffer Overrun Interrupt Enable

`pub fn rxendie(&self) -> RXENDIE_R`[src]

Bit 1 - End Of Reception Interrupt Enable

`pub fn rxbrie(&self) -> RXBRIE_R`[src]

Bit 0 - Rx-Byte Received Interrupt Enable

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn spdifen(&self) -> SPDIFEN_R`[src]

Bits 0:1 - Peripheral Block Enable

`pub fn rxdmaen(&self) -> RXDMAEN_R`[src]

Bit 2 - Receiver DMA ENable for data flow

`pub fn rxsteo(&self) -> RXSTEO_R`[src]

Bit 3 - STerEO Mode

`pub fn drfmt(&self) -> DRFMT_R`[src]

Bits 4:5 - RX Data format

`pub fn pmsk(&self) -> PMSK_R`[src]

Bit 6 - Mask Parity error bit

`pub fn vmsk(&self) -> VMSK_R`[src]

Bit 7 - Mask of Validity bit

`pub fn cumsk(&self) -> CUMSK_R`[src]

Bit 8 - Mask of channel status and user bits

`pub fn ptmsk(&self) -> PTMSK_R`[src]

Bit 9 - Mask of Preamble Type bits

`pub fn cbdmaen(&self) -> CBDMAEN_R`[src]

Bit 10 - Control Buffer DMA ENable for control flow

`pub fn chsel(&self) -> CHSEL_R`[src]

Bit 11 - Channel Selection

`pub fn nbtr(&self) -> NBTR_R`[src]

Bits 12:13 - Maximum allowed re-tries during synchronization phase

`pub fn wfa(&self) -> WFA_R`[src]

Bit 14 - Wait For Activity

`pub fn insel(&self) -> INSEL_R`[src]

Bits 16:18 - input selection

`impl R<u32, Reg<u32, _IMR>>`[src]

`pub fn rxneie(&self) -> RXNEIE_R`[src]

Bit 0 - RXNE interrupt enable

`pub fn csrneie(&self) -> CSRNEIE_R`[src]

Bit 1 - Control Buffer Ready Interrupt Enable

`pub fn perrie(&self) -> PERRIE_R`[src]

Bit 2 - Parity error interrupt enable

`pub fn ovrie(&self) -> OVRIE_R`[src]

Bit 3 - Overrun error Interrupt Enable

`pub fn sblkie(&self) -> SBLKIE_R`[src]

Bit 4 - Synchronization Block Detected Interrupt Enable

`pub fn syncdie(&self) -> SYNCDIE_R`[src]

Bit 5 - Synchronization Done

`pub fn ifeie(&self) -> IFEIE_R`[src]

Bit 6 - Serial Interface Error Interrupt Enable

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn rxne(&self) -> RXNE_R`[src]

Bit 0 - Read data register not empty

`pub fn csrne(&self) -> CSRNE_R`[src]

Bit 1 - Control Buffer register is not empty

`pub fn perr(&self) -> PERR_R`[src]

Bit 2 - Parity error

`pub fn ovr(&self) -> OVR_R`[src]

Bit 3 - Overrun error

`pub fn sbd(&self) -> SBD_R`[src]

Bit 4 - Synchronization Block Detected

`pub fn syncd(&self) -> SYNCD_R`[src]

Bit 5 - Synchronization Done

`pub fn ferr(&self) -> FERR_R`[src]

Bit 6 - Framing error

`pub fn serr(&self) -> SERR_R`[src]

Bit 7 - Synchronization error

`pub fn terr(&self) -> TERR_R`[src]

Bit 8 - Time-out error

`pub fn width5(&self) -> WIDTH5_R`[src]

Bits 16:30 - Duration of 5 symbols counted with SPDIF_CLK

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn dr(&self) -> DR_R`[src]

Bits 0:23 - Parity Error bit

`pub fn pe(&self) -> PE_R`[src]

Bit 24 - Parity Error bit

`pub fn v(&self) -> V_R`[src]

Bit 25 - Validity bit

`pub fn u(&self) -> U_R`[src]

Bit 26 - User bit

`pub fn c(&self) -> C_R`[src]

Bit 27 - Channel Status bit

`pub fn pt(&self) -> PT_R`[src]

Bits 28:29 - Preamble Type

`impl R<u32, Reg<u32, _CSR>>`[src]

`pub fn usr(&self) -> USR_R`[src]

Bits 0:15 - User data information

`pub fn cs(&self) -> CS_R`[src]

Bits 16:23 - Channel A status information

`pub fn sob(&self) -> SOB_R`[src]

Bit 24 - Start Of Block

`impl R<u32, Reg<u32, _DIR>>`[src]

`pub fn thi(&self) -> THI_R`[src]

Bits 0:12 - Threshold HIGH

`pub fn tlo(&self) -> TLO_R`[src]

Bits 16:28 - Threshold LOW

`impl R<u32, Reg<u32, _POWER>>`[src]

`pub fn pwrctrl(&self) -> PWRCTRL_R`[src]

Bits 0:1 - PWRCTRL

`impl R<u32, Reg<u32, _CLKCR>>`[src]

`pub fn hwfc_en(&self) -> HWFC_EN_R`[src]

Bit 14 - HW Flow Control enable

`pub fn negedge(&self) -> NEGEDGE_R`[src]

Bit 13 - SDIO_CK dephasing selection bit

`pub fn widbus(&self) -> WIDBUS_R`[src]

Bits 11:12 - Wide bus mode enable bit

`pub fn bypass(&self) -> BYPASS_R`[src]

Bit 10 - Clock divider bypass enable bit

`pub fn pwrsav(&self) -> PWRSAV_R`[src]

Bit 9 - Power saving configuration bit

`pub fn clken(&self) -> CLKEN_R`[src]

Bit 8 - Clock enable bit

`pub fn clkdiv(&self) -> CLKDIV_R`[src]

Bits 0:7 - Clock divide factor

`impl R<u32, Reg<u32, _ARG>>`[src]

`pub fn cmdarg(&self) -> CMDARG_R`[src]

Bits 0:31 - Command argument

`impl R<u32, Reg<u32, _CMD>>`[src]

`pub fn ce_atacmd(&self) -> CE_ATACMD_R`[src]

Bit 14 - CE-ATA command

`pub fn n_ien(&self) -> NIEN_R`[src]

Bit 13 - not Interrupt Enable

`pub fn encmdcompl(&self) -> ENCMDCOMPL_R`[src]

Bit 12 - Enable CMD completion

`pub fn sdiosuspend(&self) -> SDIOSUSPEND_R`[src]

Bit 11 - SD I/O suspend command

`pub fn cpsmen(&self) -> CPSMEN_R`[src]

Bit 10 - Command path state machine (CPSM) Enable bit

`pub fn waitpend(&self) -> WAITPEND_R`[src]

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)

`pub fn waitint(&self) -> WAITINT_R`[src]

Bit 8 - CPSM waits for interrupt request

`pub fn waitresp(&self) -> WAITRESP_R`[src]

Bits 6:7 - Wait for response bits

`pub fn cmdindex(&self) -> CMDINDEX_R`[src]

Bit 11 - SD I/O enable functions

`pub fn rwmod(&self) -> RWMOD_R`[src]

Bit 10 - Read wait mode

`pub fn rwstop(&self) -> RWSTOP_R`[src]

Bit 9 - Read wait stop

`pub fn rwstart(&self) -> RWSTART_R`[src]

Bit 8 - Read wait start

`pub fn dblocksize(&self) -> DBLOCKSIZE_R`[src]

Bits 4:7 - Data block size

`pub fn dmaen(&self) -> DMAEN_R`[src]

Bit 3 - DMA enable bit

`pub fn dtmode(&self) -> DTMODE_R`[src]

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer

`pub fn dtdir(&self) -> DTDIR_R`[src]

Bit 1 - Data transfer direction selection

`pub fn dten(&self) -> DTEN_R`[src]

Bit 0 - DTEN

`impl R<u32, Reg<u32, _DCOUNT>>`[src]

`pub fn datacount(&self) -> DATACOUNT_R`[src]

Bits 0:24 - Data count value

`impl R<u32, Reg<u32, _STA>>`[src]

`pub fn ceataend(&self) -> CEATAEND_R`[src]

Bit 23 - CE-ATA command completion signal received for CMD61

`pub fn sdioit(&self) -> SDIOIT_R`[src]

Bit 22 - SDIO interrupt received

`pub fn rxdavl(&self) -> RXDAVL_R`[src]

Bit 21 - Data available in receive FIFO

`pub fn txdavl(&self) -> TXDAVL_R`[src]

Bit 20 - Data available in transmit FIFO

`pub fn rxfifoe(&self) -> RXFIFOE_R`[src]

Bit 19 - Receive FIFO empty

`pub fn txfifoe(&self) -> TXFIFOE_R`[src]

Bit 18 - Transmit FIFO empty

`pub fn rxfifof(&self) -> RXFIFOF_R`[src]

Bit 17 - Receive FIFO full

`pub fn txfifof(&self) -> TXFIFOF_R`[src]

Bit 16 - Transmit FIFO full

`pub fn rxfifohf(&self) -> RXFIFOHF_R`[src]

Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO

`pub fn txfifohe(&self) -> TXFIFOHE_R`[src]

Bit 14 - Transmit FIFO half empty: at least 8 words can be written into the FIFO

`pub fn rxact(&self) -> RXACT_R`[src]

Bit 13 - Data receive in progress

`pub fn txact(&self) -> TXACT_R`[src]

Bit 12 - Data transmit in progress

`pub fn cmdact(&self) -> CMDACT_R`[src]

Bit 11 - Command transfer in progress

`pub fn dbckend(&self) -> DBCKEND_R`[src]

Bit 10 - Data block sent/received (CRC check passed)

`pub fn stbiterr(&self) -> STBITERR_R`[src]

Bit 9 - Start bit not detected on all data signals in wide bus mode

`pub fn dataend(&self) -> DATAEND_R`[src]

Bit 8 - Data end (data counter, SDIDCOUNT, is zero)

`pub fn cmdsent(&self) -> CMDSENT_R`[src]

Bit 7 - Command sent (no response required)

`pub fn cmdrend(&self) -> CMDREND_R`[src]

Bit 6 - Command response received (CRC check passed)

`pub fn rxoverr(&self) -> RXOVERR_R`[src]

Bit 5 - Received FIFO overrun error

`pub fn txunderr(&self) -> TXUNDERR_R`[src]

Bit 4 - Transmit FIFO underrun error

`pub fn dtimeout(&self) -> DTIMEOUT_R`[src]

Bit 3 - Data timeout

`pub fn ctimeout(&self) -> CTIMEOUT_R`[src]

Bit 2 - Command response timeout

`pub fn dcrcfail(&self) -> DCRCFAIL_R`[src]

Bit 1 - Data block sent/received (CRC check failed)

`pub fn ccrcfail(&self) -> CCRCFAIL_R`[src]

Bit 0 - Command response received (CRC check failed)

`impl R<u32, Reg<u32, _ICR>>`[src]

`pub fn ceataendc(&self) -> CEATAENDC_R`[src]

Bit 23 - CEATAEND flag clear bit

`pub fn sdioitc(&self) -> SDIOITC_R`[src]

Bit 22 - SDIOIT flag clear bit

`pub fn dbckendc(&self) -> DBCKENDC_R`[src]

Bit 10 - DBCKEND flag clear bit

`pub fn stbiterrc(&self) -> STBITERRC_R`[src]

Bit 9 - STBITERR flag clear bit

`pub fn dataendc(&self) -> DATAENDC_R`[src]

Bit 8 - DATAEND flag clear bit

`pub fn cmdsentc(&self) -> CMDSENTC_R`[src]

Bit 7 - CMDSENT flag clear bit

`pub fn cmdrendc(&self) -> CMDRENDC_R`[src]

Bit 6 - CMDREND flag clear bit

`pub fn rxoverrc(&self) -> RXOVERRC_R`[src]

Bit 5 - RXOVERR flag clear bit

`pub fn txunderrc(&self) -> TXUNDERRC_R`[src]

Bit 4 - TXUNDERR flag clear bit

`pub fn dtimeoutc(&self) -> DTIMEOUTC_R`[src]

Bit 3 - DTIMEOUT flag clear bit

`pub fn ctimeoutc(&self) -> CTIMEOUTC_R`[src]

Bit 2 - CTIMEOUT flag clear bit

`pub fn dcrcfailc(&self) -> DCRCFAILC_R`[src]

Bit 1 - DCRCFAIL flag clear bit

`pub fn ccrcfailc(&self) -> CCRCFAILC_R`[src]

Bit 0 - CCRCFAIL flag clear bit

`impl R<u32, Reg<u32, _MASK>>`[src]

`pub fn ceataendie(&self) -> CEATAENDIE_R`[src]

Bit 23 - CE-ATA command completion signal received interrupt enable

`pub fn sdioitie(&self) -> SDIOITIE_R`[src]

Bit 22 - SDIO mode interrupt received interrupt enable

`pub fn rxdavlie(&self) -> RXDAVLIE_R`[src]

Bit 21 - Data available in Rx FIFO interrupt enable

`pub fn txdavlie(&self) -> TXDAVLIE_R`[src]

Bit 20 - Data available in Tx FIFO interrupt enable

`pub fn rxfifoeie(&self) -> RXFIFOEIE_R`[src]

Bit 19 - Rx FIFO empty interrupt enable

`pub fn txfifoeie(&self) -> TXFIFOEIE_R`[src]

Bit 18 - Tx FIFO empty interrupt enable

`pub fn rxfifofie(&self) -> RXFIFOFIE_R`[src]

Bit 17 - Rx FIFO full interrupt enable

`pub fn txfifofie(&self) -> TXFIFOFIE_R`[src]

Bit 16 - Tx FIFO full interrupt enable

`pub fn rxfifohfie(&self) -> RXFIFOHFIE_R`[src]

Bit 15 - Rx FIFO half full interrupt enable

`pub fn txfifoheie(&self) -> TXFIFOHEIE_R`[src]

Bit 14 - Tx FIFO half empty interrupt enable

`pub fn rxactie(&self) -> RXACTIE_R`[src]

Bit 13 - Data receive acting interrupt enable

`pub fn txactie(&self) -> TXACTIE_R`[src]

Bit 12 - Data transmit acting interrupt enable

`pub fn cmdactie(&self) -> CMDACTIE_R`[src]

Bit 11 - Command acting interrupt enable

`pub fn dbckendie(&self) -> DBCKENDIE_R`[src]

Bit 10 - Data block end interrupt enable

`pub fn stbiterrie(&self) -> STBITERRIE_R`[src]

Bit 9 - Start bit error interrupt enable

`pub fn dataendie(&self) -> DATAENDIE_R`[src]

Bit 8 - Data end interrupt enable

`pub fn cmdsentie(&self) -> CMDSENTIE_R`[src]

Bit 7 - Command sent interrupt enable

`pub fn cmdrendie(&self) -> CMDRENDIE_R`[src]

Bit 6 - Command response received interrupt enable

`pub fn rxoverrie(&self) -> RXOVERRIE_R`[src]

Bit 5 - Rx FIFO overrun error interrupt enable

`pub fn txunderrie(&self) -> TXUNDERRIE_R`[src]

Bit 4 - Tx FIFO underrun error interrupt enable

`pub fn dtimeoutie(&self) -> DTIMEOUTIE_R`[src]

Bit 3 - Data timeout interrupt enable

`pub fn ctimeoutie(&self) -> CTIMEOUTIE_R`[src]

Bit 2 - Command timeout interrupt enable

`pub fn dcrcfailie(&self) -> DCRCFAILIE_R`[src]

Bit 1 - Data CRC fail interrupt enable

`pub fn ccrcfailie(&self) -> CCRCFAILIE_R`[src]

Bit 0 - Command CRC fail interrupt enable

`impl R<u32, Reg<u32, _FIFOCNT>>`[src]

`pub fn fifocount(&self) -> FIFOCOUNT_R`[src]

Bits 0:23 - Remaining number of words to be written to or read from the FIFO

`impl R<u32, Reg<u32, _FIFO>>`[src]

`pub fn fifodata(&self) -> FIFODATA_R`[src]

Bits 0:31 - Receive and transmit FIFO data

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn down(&self) -> DOWN_R`[src]

Bit 6 - Counter direction change up to down

`pub fn up(&self) -> UP_R`[src]

Bit 5 - Counter direction change down to up

`pub fn arrok(&self) -> ARROK_R`[src]

Bit 4 - Autoreload register update OK

`pub fn cmpok(&self) -> CMPOK_R`[src]

Bit 3 - Compare register update OK

`pub fn exttrig(&self) -> EXTTRIG_R`[src]

Bit 2 - External trigger edge event

`pub fn arrm(&self) -> ARRM_R`[src]

Bit 1 - Autoreload match

`pub fn cmpm(&self) -> CMPM_R`[src]

Bit 0 - Compare match

`impl R<u32, Reg<u32, _IER>>`[src]

`pub fn downie(&self) -> DOWNIE_R`[src]

Bit 6 - Direction change to down Interrupt Enable

`pub fn upie(&self) -> UPIE_R`[src]

Bit 5 - Direction change to UP Interrupt Enable

`pub fn arrokie(&self) -> ARROKIE_R`[src]

Bit 4 - Autoreload register update OK Interrupt Enable

`pub fn cmpokie(&self) -> CMPOKIE_R`[src]

Bit 3 - Compare register update OK Interrupt Enable

`pub fn exttrigie(&self) -> EXTTRIGIE_R`[src]

Bit 2 - External trigger valid edge Interrupt Enable

`pub fn arrmie(&self) -> ARRMIE_R`[src]

Bit 1 - Autoreload match Interrupt Enable

`pub fn cmpmie(&self) -> CMPMIE_R`[src]

Bit 0 - Compare match Interrupt Enable

`impl R<u32, Reg<u32, _CFGR>>`[src]

`pub fn enc(&self) -> ENC_R`[src]

Bit 24 - Encoder mode enable

`pub fn countmode(&self) -> COUNTMODE_R`[src]

Bit 23 - counter mode enabled

`pub fn preload(&self) -> PRELOAD_R`[src]

Bit 22 - Registers update mode

`pub fn wavpol(&self) -> WAVPOL_R`[src]

Bit 21 - Waveform shape polarity

`pub fn wave(&self) -> WAVE_R`[src]

Bit 20 - Waveform shape

`pub fn timout(&self) -> TIMOUT_R`[src]

Bit 19 - Timeout enable

`pub fn trigen(&self) -> TRIGEN_R`[src]

Bits 17:18 - Trigger enable and polarity

`pub fn trigsel(&self) -> TRIGSEL_R`[src]

Bits 13:15 - Trigger selector

`pub fn presc(&self) -> PRESC_R`[src]

Bits 9:11 - Clock prescaler

`pub fn trgflt(&self) -> TRGFLT_R`[src]

Bits 6:7 - Configurable digital filter for trigger

`pub fn ckflt(&self) -> CKFLT_R`[src]

Bits 3:4 - Configurable digital filter for external clock

`pub fn ckpol(&self) -> CKPOL_R`[src]

Bits 1:2 - Clock Polarity

`pub fn cksel(&self) -> CKSEL_R`[src]

Bit 0 - Clock selector

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn cntstrt(&self) -> CNTSTRT_R`[src]

Bit 2 - Timer start in continuous mode

`pub fn sngstrt(&self) -> SNGSTRT_R`[src]

Bit 1 - LPTIM start in single mode

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 0 - LPTIM Enable

`impl R<u32, Reg<u32, _CMP>>`[src]

`pub fn cmp(&self) -> CMP_R`[src]

Bits 0:15 - Compare value

`impl R<u32, Reg<u32, _ARR>>`[src]

`pub fn arr(&self) -> ARR_R`[src]

Bits 0:15 - Auto reload value

Checks if the value of the field is NOFILTER

`pub fn is_filter1(&self) -> bool`[src]

Checks if the value of the field is FILTER1

`pub fn is_filter2(&self) -> bool`[src]

Checks if the value of the field is FILTER2

`pub fn is_filter3(&self) -> bool`[src]

Checks if the value of the field is FILTER3

`pub fn is_filter4(&self) -> bool`[src]

Checks if the value of the field is FILTER4

`pub fn is_filter5(&self) -> bool`[src]

Checks if the value of the field is FILTER5

`pub fn is_filter6(&self) -> bool`[src]

Checks if the value of the field is FILTER6

`pub fn is_filter7(&self) -> bool`[src]

Checks if the value of the field is FILTER7

`pub fn is_filter8(&self) -> bool`[src]

Checks if the value of the field is FILTER8

`pub fn is_filter9(&self) -> bool`[src]

Checks if the value of the field is FILTER9

`pub fn is_filter10(&self) -> bool`[src]

Checks if the value of the field is FILTER10

`pub fn is_filter11(&self) -> bool`[src]

Checks if the value of the field is FILTER11

`pub fn is_filter12(&self) -> bool`[src]

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn pe(&self) -> PE_R`[src]

Bit 0 - Peripheral enable

`pub fn txie(&self) -> TXIE_R`[src]

Bit 1 - TX Interrupt enable

`pub fn rxie(&self) -> RXIE_R`[src]

Bit 2 - RX Interrupt enable

`pub fn addrie(&self) -> ADDRIE_R`[src]

Bit 3 - Address match interrupt enable (slave only)

`pub fn nackie(&self) -> NACKIE_R`[src]

Bit 4 - Not acknowledge received interrupt enable

`pub fn stopie(&self) -> STOPIE_R`[src]

Bit 5 - STOP detection Interrupt enable

`pub fn tcie(&self) -> TCIE_R`[src]

Bit 6 - Transfer Complete interrupt enable

`pub fn errie(&self) -> ERRIE_R`[src]

Bit 7 - Error interrupts enable

`pub fn dnf(&self) -> DNF_R`[src]

Bits 8:11 - Digital noise filter

`pub fn anfoff(&self) -> ANFOFF_R`[src]

Bit 12 - Analog noise filter OFF

`pub fn txdmaen(&self) -> TXDMAEN_R`[src]

Bit 14 - DMA transmission requests enable

`pub fn rxdmaen(&self) -> RXDMAEN_R`[src]

Bit 15 - DMA reception requests enable

`pub fn sbc(&self) -> SBC_R`[src]

Bit 16 - Slave byte control

`pub fn nostretch(&self) -> NOSTRETCH_R`[src]

Bit 17 - Clock stretching disable

`pub fn wupen(&self) -> WUPEN_R`[src]

Bit 18 - Wakeup from STOP enable

`pub fn gcen(&self) -> GCEN_R`[src]

Bit 19 - General call enable

`pub fn smbhen(&self) -> SMBHEN_R`[src]

Bit 20 - SMBus Host address enable

`pub fn smbden(&self) -> SMBDEN_R`[src]

Bit 21 - SMBus Device Default address enable

`pub fn alerten(&self) -> ALERTEN_R`[src]

Bit 22 - SMBUS alert enable

`pub fn pecen(&self) -> PECEN_R`[src]

Bit 23 - PEC enable

`impl R<bool, PECBYTE_A>`[src]

Bits 16:23 - Number of bytes

`pub fn nack(&self) -> NACK_R`[src]

Bit 15 - NACK generation (slave mode)

`pub fn stop(&self) -> STOP_R`[src]

Bit 14 - Stop generation (master mode)

`pub fn start(&self) -> START_R`[src]

Bit 13 - Start generation

`pub fn head10r(&self) -> HEAD10R_R`[src]

Bit 12 - 10-bit address header only read direction (master receiver mode)

`pub fn add10(&self) -> ADD10_R`[src]

Bit 11 - 10-bit addressing mode (master mode)

`pub fn rd_wrn(&self) -> RD_WRN_R`[src]

Bit 10 - Transfer direction (master mode)

`pub fn sadd(&self) -> SADD_R`[src]

Bits 0:9 - Slave address bit (master mode)

`impl R<bool, OA1MODE_A>`[src]

`pub fn variant(&self) -> OA1MODE_A`[src]

Get enumerated values variant

`pub fn is_bit7(&self) -> bool`[src]

Checks if the value of the field is BIT7

`pub fn is_bit10(&self) -> bool`[src]

Checks if the value of the field is BIT10

`impl R<bool, OA1EN_A>`[src]

`pub fn variant(&self) -> OA1EN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _OAR1>>`[src]

`pub fn oa1(&self) -> OA1_R`[src]

Bits 0:9 - Interface address

`pub fn oa1mode(&self) -> OA1MODE_R`[src]

Bit 10 - Own Address 1 10-bit mode

`pub fn oa1en(&self) -> OA1EN_R`[src]

Bit 15 - Own Address 1 enable

`impl R<u8, OA2MSK_A>`[src]

`pub fn variant(&self) -> OA2MSK_A`[src]

Get enumerated values variant

`pub fn is_no_mask(&self) -> bool`[src]

Checks if the value of the field is NOMASK

`pub fn is_mask1(&self) -> bool`[src]

Checks if the value of the field is MASK1

`pub fn is_mask2(&self) -> bool`[src]

Checks if the value of the field is MASK2

`pub fn is_mask3(&self) -> bool`[src]

Checks if the value of the field is MASK3

`pub fn is_mask4(&self) -> bool`[src]

Checks if the value of the field is MASK4

`pub fn is_mask5(&self) -> bool`[src]

Checks if the value of the field is MASK5

`pub fn is_mask6(&self) -> bool`[src]

Checks if the value of the field is MASK6

`pub fn is_mask7(&self) -> bool`[src]

Checks if the value of the field is MASK7

`impl R<bool, OA2EN_A>`[src]

`pub fn variant(&self) -> OA2EN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _OAR2>>`[src]

`pub fn oa2(&self) -> OA2_R`[src]

Bits 1:7 - Interface address

`pub fn oa2msk(&self) -> OA2MSK_R`[src]

Bits 8:10 - Own Address 2 masks

`pub fn oa2en(&self) -> OA2EN_R`[src]

Bit 15 - Own Address 2 enable

`impl R<u32, Reg<u32, _TIMINGR>>`[src]

`pub fn scll(&self) -> SCLL_R`[src]

Bits 0:7 - SCL low period (master mode)

`pub fn sclh(&self) -> SCLH_R`[src]

Bits 8:15 - SCL high period (master mode)

`pub fn sdadel(&self) -> SDADEL_R`[src]

Bits 16:19 - Data hold time

`pub fn scldel(&self) -> SCLDEL_R`[src]

Bits 20:23 - Data setup time

`pub fn presc(&self) -> PRESC_R`[src]

Bits 28:31 - Timing prescaler

`impl R<bool, TIDLE_A>`[src]

`pub fn variant(&self) -> TIDLE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, TIMOUTEN_A>`[src]

`pub fn variant(&self) -> TIMOUTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<bool, TEXTEN_A>`[src]

`pub fn variant(&self) -> TEXTEN_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u32, Reg<u32, _TIMEOUTR>>`[src]

`pub fn timeouta(&self) -> TIMEOUTA_R`[src]

Bits 0:11 - Bus timeout A

`pub fn tidle(&self) -> TIDLE_R`[src]

`pub fn alert(&self) -> ALERT_R`[src]

Bit 13 - SMBus alert

`pub fn timeout(&self) -> TIMEOUT_R`[src]

Bit 12 - Timeout or t_low detection flag

`pub fn pecerr(&self) -> PECERR_R`[src]

Bit 11 - PEC Error in reception

`pub fn ovr(&self) -> OVR_R`[src]

Bit 10 - Overrun/Underrun (slave mode)

`pub fn arlo(&self) -> ARLO_R`[src]

Bit 9 - Arbitration lost

`pub fn berr(&self) -> BERR_R`[src]

Bit 8 - Bus error

`pub fn tcr(&self) -> TCR_R`[src]

Bit 7 - Transfer Complete Reload

`pub fn tc(&self) -> TC_R`[src]

Bit 6 - Transfer Complete (master mode)

`pub fn stopf(&self) -> STOPF_R`[src]

Bit 5 - Stop detection flag

`pub fn nackf(&self) -> NACKF_R`[src]

Bit 4 - Not acknowledge received flag

`pub fn addr(&self) -> ADDR_R`[src]

Bit 3 - Address matched (slave mode)

`pub fn rxne(&self) -> RXNE_R`[src]

Bit 2 - Receive data register not empty (receivers)

`pub fn txis(&self) -> TXIS_R`[src]

Bit 1 - Transmit interrupt status (transmitters)

`pub fn txe(&self) -> TXE_R`[src]

Bit 0 - Transmit data register empty (transmitters)

`impl R<u32, Reg<u32, _PECR>>`[src]

`pub fn pec(&self) -> PEC_R`[src]

Bits 0:7 - Packet error checking register

`impl R<u32, Reg<u32, _RXDR>>`[src]

`pub fn rxdata(&self) -> RXDATA_R`[src]

Bits 0:7 - 8-bit receive data

`impl R<u32, Reg<u32, _TXDR>>`[src]

`pub fn txdata(&self) -> TXDATA_R`[src]

Bits 0:7 - 8-bit transmit data

`impl R<u32, Reg<u32, _TR>>`[src]

`pub fn pm(&self) -> PM_R`[src]

Bit 22 - AM/PM notation

`pub fn ht(&self) -> HT_R`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&self) -> HU_R`[src]

Bits 16:19 - Hour units in BCD format

`pub fn mnt(&self) -> MNT_R`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&self) -> MNU_R`[src]

Bits 8:11 - Minute units in BCD format

`pub fn st(&self) -> ST_R`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&self) -> SU_R`[src]

Bits 0:3 - Second units in BCD format

`impl R<u32, Reg<u32, _DR>>`[src]

`pub fn yt(&self) -> YT_R`[src]

Bits 20:23 - Year tens in BCD format

`pub fn yu(&self) -> YU_R`[src]

Bits 16:19 - Year units in BCD format

`pub fn wdu(&self) -> WDU_R`[src]

Bits 13:15 - Week day units

`pub fn mt(&self) -> MT_R`[src]

Bit 12 - Month tens in BCD format

`pub fn mu(&self) -> MU_R`[src]

Bits 8:11 - Month units in BCD format

`pub fn dt(&self) -> DT_R`[src]

Bits 4:5 - Date tens in BCD format

`pub fn du(&self) -> DU_R`[src]

Bits 0:3 - Date units in BCD format

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn wcksel(&self) -> WCKSEL_R`[src]

Bits 0:2 - Wakeup clock selection

`pub fn tsedge(&self) -> TSEDGE_R`[src]

Bit 3 - Time-stamp event active edge

`pub fn refckon(&self) -> REFCKON_R`[src]

Bit 4 - Reference clock detection enable (50 or 60 Hz)

`pub fn bypshad(&self) -> BYPSHAD_R`[src]

Bit 5 - Bypass the shadow registers

`pub fn fmt(&self) -> FMT_R`[src]

Bit 6 - Hour format

`pub fn alrae(&self) -> ALRAE_R`[src]

Bit 8 - Alarm A enable

`pub fn alrbe(&self) -> ALRBE_R`[src]

Bit 9 - Alarm B enable

`pub fn wute(&self) -> WUTE_R`[src]

Bit 10 - Wakeup timer enable

`pub fn tse(&self) -> TSE_R`[src]

Bit 11 - Time stamp enable

`pub fn alraie(&self) -> ALRAIE_R`[src]

Bit 12 - Alarm A interrupt enable

`pub fn alrbie(&self) -> ALRBIE_R`[src]

Bit 13 - Alarm B interrupt enable

`pub fn wutie(&self) -> WUTIE_R`[src]

Bit 14 - Wakeup timer interrupt enable

`pub fn tsie(&self) -> TSIE_R`[src]

Bit 15 - Time-stamp interrupt enable

`pub fn add1h(&self) -> ADD1H_R`[src]

Bit 16 - Add 1 hour (summer time change)

`pub fn sub1h(&self) -> SUB1H_R`[src]

Bit 17 - Subtract 1 hour (winter time change)

`pub fn bkp(&self) -> BKP_R`[src]

Bit 18 - Backup

`pub fn cosel(&self) -> COSEL_R`[src]

Bit 19 - Calibration output selection

`pub fn pol(&self) -> POL_R`[src]

Bit 20 - Output polarity

`pub fn osel(&self) -> OSEL_R`[src]

Bits 21:22 - Output selection

`pub fn coe(&self) -> COE_R`[src]

Bit 23 - Calibration output enable

`pub fn itse(&self) -> ITSE_R`[src]

Bit 24 - timestamp on internal event enable

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn alrawf(&self) -> ALRAWF_R`[src]

Bit 0 - Alarm A write flag

`pub fn alrbwf(&self) -> ALRBWF_R`[src]

Bit 1 - Alarm B write flag

`pub fn wutwf(&self) -> WUTWF_R`[src]

Bit 2 - Wakeup timer write flag

`pub fn shpf(&self) -> SHPF_R`[src]

Bit 3 - Shift operation pending

`pub fn inits(&self) -> INITS_R`[src]

Bit 4 - Initialization status flag

`pub fn rsf(&self) -> RSF_R`[src]

Bit 5 - Registers synchronization flag

`pub fn initf(&self) -> INITF_R`[src]

Bit 6 - Initialization flag

`pub fn init(&self) -> INIT_R`[src]

Bit 7 - Initialization mode

`pub fn alraf(&self) -> ALRAF_R`[src]

Bit 8 - Alarm A flag

`pub fn alrbf(&self) -> ALRBF_R`[src]

Bit 9 - Alarm B flag

`pub fn wutf(&self) -> WUTF_R`[src]

Bit 10 - Wakeup timer flag

`pub fn tsf(&self) -> TSF_R`[src]

Bit 11 - Time-stamp flag

`pub fn tsovf(&self) -> TSOVF_R`[src]

Bit 12 - Time-stamp overflow flag

`pub fn tamp1f(&self) -> TAMP1F_R`[src]

Bit 13 - Tamper detection flag

`pub fn tamp2f(&self) -> TAMP2F_R`[src]

Bit 14 - RTC_TAMP2 detection flag

`pub fn tamp3f(&self) -> TAMP3F_R`[src]

Bit 15 - RTC_TAMP3 detection flag

`pub fn recalpf(&self) -> RECALPF_R`[src]

Bit 16 - Recalibration pending Flag

`impl R<u32, Reg<u32, _PRER>>`[src]

`pub fn prediv_a(&self) -> PREDIV_A_R`[src]

Bits 16:22 - Asynchronous prescaler factor

`pub fn prediv_s(&self) -> PREDIV_S_R`[src]

Bits 0:14 - Synchronous prescaler factor

`impl R<u32, Reg<u32, _WUTR>>`[src]

`pub fn wut(&self) -> WUT_R`[src]

Bits 0:15 - Wakeup auto-reload value bits

`impl R<u32, Reg<u32, _ALRMAR>>`[src]

`pub fn msk4(&self) -> MSK4_R`[src]

Bit 31 - Alarm A date mask

`pub fn wdsel(&self) -> WDSEL_R`[src]

Bit 30 - Week day selection

`pub fn dt(&self) -> DT_R`[src]

Bits 28:29 - Date tens in BCD format

`pub fn du(&self) -> DU_R`[src]

Bits 24:27 - Date units or day in BCD format

`pub fn msk3(&self) -> MSK3_R`[src]

Bit 23 - Alarm A hours mask

`pub fn pm(&self) -> PM_R`[src]

Bit 22 - AM/PM notation

`pub fn ht(&self) -> HT_R`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&self) -> HU_R`[src]

Bits 16:19 - Hour units in BCD format

`pub fn msk2(&self) -> MSK2_R`[src]

Bit 15 - Alarm A minutes mask

`pub fn mnt(&self) -> MNT_R`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&self) -> MNU_R`[src]

Bits 8:11 - Minute units in BCD format

`pub fn msk1(&self) -> MSK1_R`[src]

Bit 7 - Alarm A seconds mask

`pub fn st(&self) -> ST_R`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&self) -> SU_R`[src]

Bits 0:3 - Second units in BCD format

`impl R<u32, Reg<u32, _ALRMBR>>`[src]

`pub fn msk4(&self) -> MSK4_R`[src]

Bit 31 - Alarm B date mask

`pub fn wdsel(&self) -> WDSEL_R`[src]

Bit 30 - Week day selection

`pub fn dt(&self) -> DT_R`[src]

Bits 28:29 - Date tens in BCD format

`pub fn du(&self) -> DU_R`[src]

Bits 24:27 - Date units or day in BCD format

`pub fn msk3(&self) -> MSK3_R`[src]

Bit 23 - Alarm B hours mask

`pub fn pm(&self) -> PM_R`[src]

Bit 22 - AM/PM notation

`pub fn ht(&self) -> HT_R`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn hu(&self) -> HU_R`[src]

Bits 16:19 - Hour units in BCD format

`pub fn msk2(&self) -> MSK2_R`[src]

Bit 15 - Alarm B minutes mask

`pub fn mnt(&self) -> MNT_R`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn mnu(&self) -> MNU_R`[src]

Bits 8:11 - Minute units in BCD format

`pub fn msk1(&self) -> MSK1_R`[src]

Bit 7 - Alarm B seconds mask

`pub fn st(&self) -> ST_R`[src]

Bits 4:6 - Second tens in BCD format

`pub fn su(&self) -> SU_R`[src]

Bits 0:3 - Second units in BCD format

`impl R<u32, Reg<u32, _SSR>>`[src]

`pub fn ss(&self) -> SS_R`[src]

Bits 0:15 - Sub second value

`impl R<u32, Reg<u32, _TSTR>>`[src]

`pub fn su(&self) -> SU_R`[src]

Bits 0:3 - Second units in BCD format

`pub fn st(&self) -> ST_R`[src]

Bits 4:6 - Second tens in BCD format

`pub fn mnu(&self) -> MNU_R`[src]

Bits 8:11 - Minute units in BCD format

`pub fn mnt(&self) -> MNT_R`[src]

Bits 12:14 - Minute tens in BCD format

`pub fn hu(&self) -> HU_R`[src]

Bits 16:19 - Hour units in BCD format

`pub fn ht(&self) -> HT_R`[src]

Bits 20:21 - Hour tens in BCD format

`pub fn pm(&self) -> PM_R`[src]

Bit 22 - AM/PM notation

`impl R<u32, Reg<u32, _TSDR>>`[src]

`pub fn wdu(&self) -> WDU_R`[src]

Bits 13:15 - Week day units

`pub fn mt(&self) -> MT_R`[src]

Bit 12 - Month tens in BCD format

`pub fn mu(&self) -> MU_R`[src]

Bits 8:11 - Month units in BCD format

`pub fn dt(&self) -> DT_R`[src]

Bits 4:5 - Date tens in BCD format

`pub fn du(&self) -> DU_R`[src]

Bits 0:3 - Date units in BCD format

`impl R<u32, Reg<u32, _TSSSR>>`[src]

`pub fn ss(&self) -> SS_R`[src]

Bits 0:15 - Sub second value

`impl R<u32, Reg<u32, _CALR>>`[src]

`pub fn calp(&self) -> CALP_R`[src]

Bit 15 - Increase frequency of RTC by 488.5 ppm

`pub fn calw8(&self) -> CALW8_R`[src]

Bit 14 - Use an 8-second calibration cycle period

`pub fn calw16(&self) -> CALW16_R`[src]

Bit 13 - Use a 16-second calibration cycle period

`pub fn calm(&self) -> CALM_R`[src]

Bits 0:8 - Calibration minus

`impl R<u32, Reg<u32, _TAMPCR>>`[src]

`pub fn tamp1e(&self) -> TAMP1E_R`[src]

Bit 0 - Tamper 1 detection enable

`pub fn tamp1trg(&self) -> TAMP1TRG_R`[src]

Bit 1 - Active level for tamper 1

`pub fn tampie(&self) -> TAMPIE_R`[src]

Bit 2 - Tamper interrupt enable

`pub fn tamp2e(&self) -> TAMP2E_R`[src]

Bit 3 - Tamper 2 detection enable

`pub fn tamp2trg(&self) -> TAMP2TRG_R`[src]

Bit 4 - Active level for tamper 2

`pub fn tamp3e(&self) -> TAMP3E_R`[src]

Bit 5 - Tamper 3 detection enable

`pub fn tamp3trg(&self) -> TAMP3TRG_R`[src]

Bit 6 - Active level for tamper 3

`pub fn tampts(&self) -> TAMPTS_R`[src]

Bit 7 - Activate timestamp on tamper detection event

`pub fn tampfreq(&self) -> TAMPFREQ_R`[src]

Bits 8:10 - Tamper sampling frequency

`pub fn tampflt(&self) -> TAMPFLT_R`[src]

Bits 11:12 - Tamper filter count

`pub fn tampprch(&self) -> TAMPPRCH_R`[src]

Bits 13:14 - Tamper precharge duration

`pub fn tamppudis(&self) -> TAMPPUDIS_R`[src]

Bit 15 - TAMPER pull-up disable

`pub fn tamp1ie(&self) -> TAMP1IE_R`[src]

Bit 16 - Tamper 1 interrupt enable

`pub fn tamp1noerase(&self) -> TAMP1NOERASE_R`[src]

Bit 17 - Tamper 1 no erase

`pub fn tamp1mf(&self) -> TAMP1MF_R`[src]

Bit 18 - Tamper 1 mask flag

`pub fn tamp2ie(&self) -> TAMP2IE_R`[src]

Bit 19 - Tamper 2 interrupt enable

`pub fn tamp2noerase(&self) -> TAMP2NOERASE_R`[src]

Bit 20 - Tamper 2 no erase

`pub fn tamp2mf(&self) -> TAMP2MF_R`[src]

Bit 21 - Tamper 2 mask flag

`pub fn tamp3ie(&self) -> TAMP3IE_R`[src]

Bit 22 - Tamper 3 interrupt enable

`pub fn tamp3noerase(&self) -> TAMP3NOERASE_R`[src]

Bit 23 - Tamper 3 no erase

`pub fn tamp3mf(&self) -> TAMP3MF_R`[src]

Bit 24 - Tamper 3 mask flag

`impl R<u32, Reg<u32, _ALRMASSR>>`[src]

`pub fn maskss(&self) -> MASKSS_R`[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

`pub fn ss(&self) -> SS_R`[src]

Bits 0:14 - Sub seconds value

`impl R<u32, Reg<u32, _ALRMBSSR>>`[src]

`pub fn maskss(&self) -> MASKSS_R`[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

`pub fn ss(&self) -> SS_R`[src]

Bits 0:14 - Sub seconds value

`impl R<u32, Reg<u32, _OR>>`[src]

`pub fn rtc_alarm_type(&self) -> RTC_ALARM_TYPE_R`[src]

Bit 0 - RTC_ALARM on PC13 output type

`pub fn rtc_out_rmp(&self) -> RTC_OUT_RMP_R`[src]

Bit 1 - RTC_OUT remap

Bit 27 - End of Block interrupt enable

`pub fn rtoie(&self) -> RTOIE_R`[src]

Bit 26 - Receiver timeout interrupt enable

`pub fn over8(&self) -> OVER8_R`[src]

Bit 15 - Oversampling mode

`pub fn cmie(&self) -> CMIE_R`[src]

Bit 14 - Character match interrupt enable

`pub fn mme(&self) -> MME_R`[src]

Bit 13 - Mute mode enable

`pub fn m0(&self) -> M0_R`[src]

Bit 12 - Word length

`pub fn wake(&self) -> WAKE_R`[src]

Bit 11 - Receiver wakeup method

`pub fn pce(&self) -> PCE_R`[src]

Bit 10 - Parity control enable

`pub fn ps(&self) -> PS_R`[src]

Bit 9 - Parity selection

`pub fn peie(&self) -> PEIE_R`[src]

Bit 8 - PE interrupt enable

`pub fn txeie(&self) -> TXEIE_R`[src]

Bit 7 - interrupt enable

`pub fn tcie(&self) -> TCIE_R`[src]

Bit 6 - Transmission complete interrupt enable

`pub fn rxneie(&self) -> RXNEIE_R`[src]

Bit 5 - RXNE interrupt enable

`pub fn idleie(&self) -> IDLEIE_R`[src]

Bit 4 - IDLE interrupt enable

`pub fn te(&self) -> TE_R`[src]

Bit 3 - Transmitter enable

`pub fn re(&self) -> RE_R`[src]

Bit 2 - Receiver enable

`pub fn uesm(&self) -> UESM_R`[src]

`pub fn is_start(&self) -> bool`[src]

Checks if the value of the field is START

`pub fn is_edge(&self) -> bool`[src]

Checks if the value of the field is EDGE

`pub fn is_frame7f(&self) -> bool`[src]

Checks if the value of the field is FRAME7F

`pub fn is_frame55(&self) -> bool`[src]

Checks if the value of the field is FRAME55

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn rtoen(&self) -> RTOEN_R`[src]

Bit 23 - Receiver timeout enable

`pub fn abren(&self) -> ABREN_R`[src]

Bit 20 - Auto baud rate enable

`pub fn msbfirst(&self) -> MSBFIRST_R`[src]

Bit 19 - Most significant bit first

`pub fn datainv(&self) -> DATAINV_R`[src]

Bit 18 - Binary data inversion

`pub fn txinv(&self) -> TXINV_R`[src]

Bit 17 - TX pin active level inversion

`pub fn rxinv(&self) -> RXINV_R`[src]

Bit 16 - RX pin active level inversion

`pub fn swap(&self) -> SWAP_R`[src]

Bit 15 - Swap TX/RX pins

`pub fn linen(&self) -> LINEN_R`[src]

Bit 14 - LIN mode enable

`pub fn stop(&self) -> STOP_R`[src]

Bits 12:13 - STOP bits

`pub fn clken(&self) -> CLKEN_R`[src]

Bit 11 - Clock enable

`pub fn cpol(&self) -> CPOL_R`[src]

Bit 10 - Clock polarity

`pub fn cpha(&self) -> CPHA_R`[src]

Bit 9 - Clock phase

`pub fn lbcl(&self) -> LBCL_R`[src]

Bit 8 - Last bit clock pulse

`pub fn lbdie(&self) -> LBDIE_R`[src]

Bit 6 - LIN break detection interrupt enable

`pub fn lbdl(&self) -> LBDL_R`[src]

Bit 5 - LIN break detection length

`pub fn addm7(&self) -> ADDM7_R`[src]

Bit 4 - 7-bit Address Detection/4-bit Address Detection

`pub fn abrmod(&self) -> ABRMOD_R`[src]

Bits 21:22 - Auto baud rate mode

`pub fn add(&self) -> ADD_R`[src]

Bits 24:31 - Address of the USART node

`impl R<bool, WUFIE_A>`[src]

`pub fn variant(&self) -> WUFIE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

`impl R<u8, WUS_A>`[src]

`pub fn variant(&self) -> Variant<u8, WUS_A>`[src]

`pub fn dep(&self) -> DEP_R`[src]

Bit 15 - Driver enable polarity selection

`pub fn dem(&self) -> DEM_R`[src]

Bit 14 - Driver enable mode

`pub fn ddre(&self) -> DDRE_R`[src]

Bit 13 - DMA Disable on Reception Error

`pub fn ovrdis(&self) -> OVRDIS_R`[src]

Bit 12 - Overrun Disable

`pub fn onebit(&self) -> ONEBIT_R`[src]

Bit 11 - One sample bit method enable

`pub fn ctsie(&self) -> CTSIE_R`[src]

Bit 10 - CTS interrupt enable

`pub fn ctse(&self) -> CTSE_R`[src]

Bit 9 - CTS enable

`pub fn rtse(&self) -> RTSE_R`[src]

Bit 8 - RTS enable

`pub fn dmat(&self) -> DMAT_R`[src]

Bit 7 - DMA enable transmitter

`pub fn dmar(&self) -> DMAR_R`[src]

Bit 6 - DMA enable receiver

`pub fn scen(&self) -> SCEN_R`[src]

Bit 5 - Smartcard mode enable

`pub fn nack(&self) -> NACK_R`[src]

Bit 4 - Smartcard NACK enable

`pub fn hdsel(&self) -> HDSEL_R`[src]

Bit 3 - Half-duplex selection

`pub fn irlp(&self) -> IRLP_R`[src]

Bit 2 - Ir low-power

`pub fn iren(&self) -> IREN_R`[src]

Bit 1 - Ir mode enable

`pub fn eie(&self) -> EIE_R`[src]

Bit 0 - Error interrupt enable

`impl R<u32, Reg<u32, _BRR>>`[src]

`pub fn brr(&self) -> BRR_R`[src]

Bits 0:15 - DIV_Mantissa

`impl R<u32, Reg<u32, _GTPR>>`[src]

`pub fn gt(&self) -> GT_R`[src]

Bits 8:15 - Guard time value

`pub fn psc(&self) -> PSC_R`[src]

Bits 0:7 - Prescaler value

`impl R<u32, Reg<u32, _RTOR>>`[src]

`pub fn blen(&self) -> BLEN_R`[src]

Bits 24:31 - Block Length

`pub fn rto(&self) -> RTO_R`[src]

Bits 0:23 - Receiver timeout value

`impl R<u32, Reg<u32, _ISR>>`[src]

`pub fn reack(&self) -> REACK_R`[src]

Bit 22 - REACK

`pub fn teack(&self) -> TEACK_R`[src]

Bit 21 - TEACK

`pub fn wuf(&self) -> WUF_R`[src]

Bit 20 - WUF

`pub fn rwu(&self) -> RWU_R`[src]

Bit 19 - RWU

`pub fn sbkf(&self) -> SBKF_R`[src]

Bit 18 - SBKF

`pub fn cmf(&self) -> CMF_R`[src]

Bit 17 - CMF

`pub fn busy(&self) -> BUSY_R`[src]

Bit 16 - BUSY

`pub fn abrf(&self) -> ABRF_R`[src]

Bit 15 - ABRF

`pub fn abre(&self) -> ABRE_R`[src]

Bit 14 - ABRE

`pub fn eobf(&self) -> EOBF_R`[src]

Bit 12 - EOBF

`pub fn rtof(&self) -> RTOF_R`[src]

Bit 11 - RTOF

`pub fn cts(&self) -> CTS_R`[src]

Bit 10 - CTS

`pub fn ctsif(&self) -> CTSIF_R`[src]

Bit 9 - CTSIF

`pub fn lbdf(&self) -> LBDF_R`[src]

Bit 8 - LBDF

`pub fn txe(&self) -> TXE_R`[src]

Bit 7 - TXE

`pub fn tc(&self) -> TC_R`[src]

Bit 6 - TC

`pub fn rxne(&self) -> RXNE_R`[src]

Bit 5 - RXNE

`pub fn idle(&self) -> IDLE_R`[src]

Bit 4 - IDLE

`pub fn ore(&self) -> ORE_R`[src]

Bit 3 - ORE

`pub fn nf(&self) -> NF_R`[src]

Bit 2 - NF

`pub fn fe(&self) -> FE_R`[src]

Bit 1 - FE

`pub fn pe(&self) -> PE_R`[src]

Bit 0 - PE

`impl R<u32, Reg<u32, _RDR>>`[src]

`pub fn rdr(&self) -> RDR_R`[src]

Bits 0:8 - Receive data value

`impl R<u32, Reg<u32, _TDR>>`[src]

`pub fn tdr(&self) -> TDR_R`[src]

Bits 0:8 - Transmit data value

`impl R<u32, Reg<u32, _OTG_FS_GOTGCTL>>`[src]

`pub fn srqscs(&self) -> SRQSCS_R`[src]

Bit 0 - Session request success

`pub fn srq(&self) -> SRQ_R`[src]

Bit 1 - Session request

`pub fn hngscs(&self) -> HNGSCS_R`[src]

Bit 8 - Host negotiation success

`pub fn hnprq(&self) -> HNPRQ_R`[src]

Bit 9 - HNP request

`pub fn hshnpen(&self) -> HSHNPEN_R`[src]

Bit 10 - Host set HNP enable

`pub fn dhnpen(&self) -> DHNPEN_R`[src]

Bit 11 - Device HNP enabled

`pub fn cidsts(&self) -> CIDSTS_R`[src]

Bit 16 - Connector ID status

`pub fn dbct(&self) -> DBCT_R`[src]

Bit 17 - Long/short debounce time

`pub fn asvld(&self) -> ASVLD_R`[src]

Bit 18 - A-session valid

`pub fn bsvld(&self) -> BSVLD_R`[src]

Bit 19 - B-session valid

`pub fn vbvaloen(&self) -> VBVALOEN_R`[src]

Bit 2 - VBUS valid override enable

`pub fn vbvaloval(&self) -> VBVALOVAL_R`[src]

Bit 3 - VBUS valid override value

`pub fn avaloen(&self) -> AVALOEN_R`[src]

Bit 4 - A-peripheral session valid override enable

`pub fn avaloval(&self) -> AVALOVAL_R`[src]

Bit 5 - A-peripheral session valid override value

`pub fn bvaloen(&self) -> BVALOEN_R`[src]

Bit 6 - B-peripheral session valid override enable

`pub fn bvaloval(&self) -> BVALOVAL_R`[src]

Bit 7 - B-peripheral session valid override value

`pub fn ehen(&self) -> EHEN_R`[src]

Bit 12 - Embedded host enable

`pub fn otgver(&self) -> OTGVER_R`[src]

Bit 20 - OTG version

`impl R<u32, Reg<u32, _OTG_FS_GOTGINT>>`[src]

`pub fn sedet(&self) -> SEDET_R`[src]

Bit 2 - Session end detected

`pub fn srsschg(&self) -> SRSSCHG_R`[src]

Bit 8 - Session request success status change

`pub fn hnsschg(&self) -> HNSSCHG_R`[src]

Bit 9 - Host negotiation success status change

`pub fn hngdet(&self) -> HNGDET_R`[src]

Bit 17 - Host negotiation detected

`pub fn adtochg(&self) -> ADTOCHG_R`[src]

Bit 18 - A-device timeout change

`pub fn dbcdne(&self) -> DBCDNE_R`[src]

Bit 19 - Debounce done

`pub fn idchng(&self) -> IDCHNG_R`[src]

Bit 20 - ID input pin changed

`impl R<u32, Reg<u32, _OTG_FS_GAHBCFG>>`[src]

`pub fn gint(&self) -> GINT_R`[src]

Bit 0 - Global interrupt mask

`pub fn txfelvl(&self) -> TXFELVL_R`[src]

Bit 7 - TxFIFO empty level

`pub fn ptxfelvl(&self) -> PTXFELVL_R`[src]

Bit 8 - Periodic TxFIFO empty level

`impl R<u32, Reg<u32, _OTG_FS_GUSBCFG>>`[src]

`pub fn tocal(&self) -> TOCAL_R`[src]

Bits 0:2 - FS timeout calibration

`pub fn srpcap(&self) -> SRPCAP_R`[src]

Bit 8 - SRP-capable

`pub fn hnpcap(&self) -> HNPCAP_R`[src]

Bit 9 - HNP-capable

`pub fn trdt(&self) -> TRDT_R`[src]

Bits 10:13 - USB turnaround time

`pub fn fhmod(&self) -> FHMOD_R`[src]

Bit 29 - Force host mode

`pub fn fdmod(&self) -> FDMOD_R`[src]

Bit 30 - Force device mode

`impl R<u32, Reg<u32, _OTG_FS_GRSTCTL>>`[src]

`pub fn csrst(&self) -> CSRST_R`[src]

Bit 0 - Core soft reset

`pub fn hsrst(&self) -> HSRST_R`[src]

Bit 1 - HCLK soft reset

`pub fn fcrst(&self) -> FCRST_R`[src]

Bit 2 - Host frame counter reset

`pub fn rxfflsh(&self) -> RXFFLSH_R`[src]

Bit 4 - RxFIFO flush

`pub fn txfflsh(&self) -> TXFFLSH_R`[src]

Bit 5 - TxFIFO flush

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 6:10 - TxFIFO number

`pub fn ahbidl(&self) -> AHBIDL_R`[src]

Bit 31 - AHB master idle

`impl R<u32, Reg<u32, _OTG_FS_GINTSTS>>`[src]

`pub fn cmod(&self) -> CMOD_R`[src]

Bit 0 - Current mode of operation

`pub fn mmis(&self) -> MMIS_R`[src]

Bit 1 - Mode mismatch interrupt

`pub fn otgint(&self) -> OTGINT_R`[src]

Bit 2 - OTG interrupt

`pub fn sof(&self) -> SOF_R`[src]

Bit 3 - Start of frame

`pub fn rxflvl(&self) -> RXFLVL_R`[src]

Bit 4 - RxFIFO non-empty

`pub fn nptxfe(&self) -> NPTXFE_R`[src]

Bit 5 - Non-periodic TxFIFO empty

`pub fn ginakeff(&self) -> GINAKEFF_R`[src]

Bit 6 - Global IN non-periodic NAK effective

`pub fn goutnakeff(&self) -> GOUTNAKEFF_R`[src]

Bit 7 - Global OUT NAK effective

`pub fn esusp(&self) -> ESUSP_R`[src]

Bit 10 - Early suspend

`pub fn usbsusp(&self) -> USBSUSP_R`[src]

Bit 11 - USB suspend

`pub fn usbrst(&self) -> USBRST_R`[src]

Bit 12 - USB reset

`pub fn enumdne(&self) -> ENUMDNE_R`[src]

Bit 13 - Enumeration done

`pub fn isoodrp(&self) -> ISOODRP_R`[src]

Bit 14 - Isochronous OUT packet dropped interrupt

`pub fn eopf(&self) -> EOPF_R`[src]

Bit 15 - End of periodic frame interrupt

`pub fn iepint(&self) -> IEPINT_R`[src]

Bit 18 - IN endpoint interrupt

`pub fn oepint(&self) -> OEPINT_R`[src]

Bit 19 - OUT endpoint interrupt

`pub fn iisoixfr(&self) -> IISOIXFR_R`[src]

Bit 20 - Incomplete isochronous IN transfer

`pub fn ipxfr_incompisoout(&self) -> IPXFR_INCOMPISOOUT_R`[src]

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

`pub fn hprtint(&self) -> HPRTINT_R`[src]

Bit 24 - Host port interrupt

`pub fn hcint(&self) -> HCINT_R`[src]

Bit 25 - Host channels interrupt

`pub fn ptxfe(&self) -> PTXFE_R`[src]

Bit 26 - Periodic TxFIFO empty

`pub fn cidschg(&self) -> CIDSCHG_R`[src]

Bit 28 - Connector ID status change

`pub fn discint(&self) -> DISCINT_R`[src]

Bit 29 - Disconnect detected interrupt

`pub fn srqint(&self) -> SRQINT_R`[src]

Bit 30 - Session request/new session detected interrupt

`pub fn wkupint(&self) -> WKUPINT_R`[src]

Bit 31 - Resume/remote wakeup detected interrupt

`pub fn rstdet(&self) -> RSTDET_R`[src]

Bit 23 - Reset detected interrupt

`impl R<u32, Reg<u32, _OTG_FS_GINTMSK>>`[src]

`pub fn mmism(&self) -> MMISM_R`[src]

Bit 1 - Mode mismatch interrupt mask

`pub fn otgint(&self) -> OTGINT_R`[src]

Bit 2 - OTG interrupt mask

`pub fn sofm(&self) -> SOFM_R`[src]

Bit 3 - Start of frame mask

`pub fn rxflvlm(&self) -> RXFLVLM_R`[src]

Bit 4 - Receive FIFO non-empty mask

`pub fn nptxfem(&self) -> NPTXFEM_R`[src]

Bit 5 - Non-periodic TxFIFO empty mask

`pub fn ginakeffm(&self) -> GINAKEFFM_R`[src]

Bit 6 - Global non-periodic IN NAK effective mask

`pub fn gonakeffm(&self) -> GONAKEFFM_R`[src]

Bit 7 - Global OUT NAK effective mask

`pub fn esuspm(&self) -> ESUSPM_R`[src]

Bit 10 - Early suspend mask

`pub fn usbsuspm(&self) -> USBSUSPM_R`[src]

Bit 11 - USB suspend mask

`pub fn usbrst(&self) -> USBRST_R`[src]

Bit 12 - USB reset mask

`pub fn enumdnem(&self) -> ENUMDNEM_R`[src]

Bit 13 - Enumeration done mask

`pub fn isoodrpm(&self) -> ISOODRPM_R`[src]

Bit 14 - Isochronous OUT packet dropped interrupt mask

`pub fn eopfm(&self) -> EOPFM_R`[src]

Bit 15 - End of periodic frame interrupt mask

`pub fn iepint(&self) -> IEPINT_R`[src]

Bit 18 - IN endpoints interrupt mask

`pub fn oepint(&self) -> OEPINT_R`[src]

Bit 19 - OUT endpoints interrupt mask

`pub fn iisoixfrm(&self) -> IISOIXFRM_R`[src]

Bit 20 - Incomplete isochronous IN transfer mask

`pub fn ipxfrm_iisooxfrm(&self) -> IPXFRM_IISOOXFRM_R`[src]

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

`pub fn prtim(&self) -> PRTIM_R`[src]

Bit 24 - Host port interrupt mask

`pub fn hcim(&self) -> HCIM_R`[src]

Bit 25 - Host channels interrupt mask

`pub fn ptxfem(&self) -> PTXFEM_R`[src]

Bit 26 - Periodic TxFIFO empty mask

`pub fn cidschgm(&self) -> CIDSCHGM_R`[src]

Bit 28 - Connector ID status change mask

`pub fn discint(&self) -> DISCINT_R`[src]

Bit 29 - Disconnect detected interrupt mask

`pub fn srqim(&self) -> SRQIM_R`[src]

Bit 30 - Session request/new session detected interrupt mask

`pub fn wuim(&self) -> WUIM_R`[src]

Bit 31 - Resume/remote wakeup detected interrupt mask

`pub fn rstdetm(&self) -> RSTDETM_R`[src]

Bit 23 - Reset detected interrupt mask

`pub fn lpmin(&self) -> LPMIN_R`[src]

Bit 27 - LPM interrupt mask

`impl R<u32, Reg<u32, _OTG_FS_GRXSTSR_DEVICE>>`[src]

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 0:3 - Endpoint number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`pub fn frmnum(&self) -> FRMNUM_R`[src]

Bits 21:24 - Frame number

`impl R<u32, Reg<u32, _OTG_FS_GRXSTSR_HOST>>`[src]

`pub fn chnum(&self) -> CHNUM_R`[src]

Bits 0:3 - Endpoint number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`impl R<u32, Reg<u32, _OTG_FS_GRXFSIZ>>`[src]

`pub fn rxfd(&self) -> RXFD_R`[src]

Bits 0:15 - RxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF0_DEVICE>>`[src]

`pub fn tx0fsa(&self) -> TX0FSA_R`[src]

Bits 0:15 - Endpoint 0 transmit RAM start address

`pub fn tx0fd(&self) -> TX0FD_R`[src]

Bits 16:31 - Endpoint 0 TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_HNPTXFSIZ_HOST>>`[src]

`pub fn nptxfsa(&self) -> NPTXFSA_R`[src]

Bits 0:15 - Non-periodic transmit RAM start address

`pub fn nptxfd(&self) -> NPTXFD_R`[src]

Bits 16:31 - Non-periodic TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_HNPTXSTS>>`[src]

`pub fn nptxfsav(&self) -> NPTXFSAV_R`[src]

Bits 0:15 - Non-periodic TxFIFO space available

`pub fn nptqxsav(&self) -> NPTQXSAV_R`[src]

Bits 16:23 - Non-periodic transmit request queue space available

`pub fn nptxqtop(&self) -> NPTXQTOP_R`[src]

Bits 24:30 - Top of the non-periodic transmit request queue

`impl R<u32, Reg<u32, _OTG_FS_GCCFG>>`[src]

`pub fn pwrdwn(&self) -> PWRDWN_R`[src]

Bit 16 - Power down

`pub fn bcden(&self) -> BCDEN_R`[src]

Bit 17 - Battery charging detector (BCD) enable

`pub fn dcden(&self) -> DCDEN_R`[src]

Bit 18 - Data contact detection (DCD) mode enable

`pub fn pden(&self) -> PDEN_R`[src]

Bit 19 - Primary detection (PD) mode enable

`pub fn sden(&self) -> SDEN_R`[src]

Bit 20 - Secondary detection (SD) mode enable

`pub fn vbden(&self) -> VBDEN_R`[src]

Bit 21 - USB VBUS detection enable

`pub fn dcdet(&self) -> DCDET_R`[src]

Bit 0 - Data contact detection (DCD) status

`pub fn pdet(&self) -> PDET_R`[src]

Bit 1 - Primary detection (PD) status

`pub fn sdet(&self) -> SDET_R`[src]

Bit 2 - Secondary detection (SD) status

`pub fn ps2det(&self) -> PS2DET_R`[src]

Bit 3 - DM pull-up detection status

`impl R<u32, Reg<u32, _OTG_FS_CID>>`[src]

`pub fn product_id(&self) -> PRODUCT_ID_R`[src]

Bits 0:31 - Product ID field

`impl R<u32, Reg<u32, _OTG_FS_HPTXFSIZ>>`[src]

`pub fn ptxsa(&self) -> PTXSA_R`[src]

Bits 0:15 - Host periodic TxFIFO start address

`pub fn ptxfsiz(&self) -> PTXFSIZ_R`[src]

Bits 16:31 - Host periodic TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF1>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF2>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFO3 transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF3>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFO4 transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_FS_GRXSTSP_DEVICE>>`[src]

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 0:3 - Endpoint number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`pub fn frmnum(&self) -> FRMNUM_R`[src]

Bits 21:24 - Frame number

`impl R<u32, Reg<u32, _OTG_FS_GRXSTSP_HOST>>`[src]

`pub fn chnum(&self) -> CHNUM_R`[src]

Bits 0:3 - Channel number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`impl R<u32, Reg<u32, _OTG_FS_GI2CCTL>>`[src]

`pub fn rwdata(&self) -> RWDATA_R`[src]

Bits 0:7 - I2C Read/Write Data

`pub fn regaddr(&self) -> REGADDR_R`[src]

Bits 8:15 - I2C Register Address

`pub fn addr(&self) -> ADDR_R`[src]

Bits 16:22 - I2C Address

`pub fn i2cen(&self) -> I2CEN_R`[src]

Bit 23 - I2C Enable

`pub fn ack(&self) -> ACK_R`[src]

Bit 24 - I2C ACK

`pub fn i2cdevadr(&self) -> I2CDEVADR_R`[src]

Bits 26:27 - I2C Device Address

`pub fn i2cdatse0(&self) -> I2CDATSE0_R`[src]

Bit 28 - I2C DatSe0 USB mode

`pub fn rw(&self) -> RW_R`[src]

Bit 30 - Read/Write Indicator

`pub fn bsydne(&self) -> BSYDNE_R`[src]

Bit 31 - I2C Busy/Done

`impl R<u32, Reg<u32, _OTG_FS_GPWRDN>>`[src]

`pub fn adpmen(&self) -> ADPMEN_R`[src]

Bit 0 - ADP module enable

`pub fn adpif(&self) -> ADPIF_R`[src]

Bit 23 - ADP interrupt flag

`impl R<u32, Reg<u32, _OTG_FS_GADPCTL>>`[src]

`pub fn prbdschg(&self) -> PRBDSCHG_R`[src]

Bits 0:1 - Probe discharge

`pub fn prbdelta(&self) -> PRBDELTA_R`[src]

Bits 2:3 - Probe delta

`pub fn prbper(&self) -> PRBPER_R`[src]

Bits 4:5 - Probe period

`pub fn rtim(&self) -> RTIM_R`[src]

Bits 6:16 - Ramp time

`pub fn enaprb(&self) -> ENAPRB_R`[src]

Bit 17 - Enable probe

`pub fn enasns(&self) -> ENASNS_R`[src]

Bit 18 - Enable sense

`pub fn adprst(&self) -> ADPRST_R`[src]

Bit 19 - ADP reset

`pub fn adpen(&self) -> ADPEN_R`[src]

Bit 20 - ADP enable

`pub fn adpprbif(&self) -> ADPPRBIF_R`[src]

Bit 21 - ADP probe interrupt flag

`pub fn adpsnsif(&self) -> ADPSNSIF_R`[src]

Bit 22 - ADP sense interrupt flag

`pub fn adptoif(&self) -> ADPTOIF_R`[src]

Bit 23 - ADP timeout interrupt flag

`pub fn adpprbim(&self) -> ADPPRBIM_R`[src]

Bit 24 - ADP probe interrupt mask

`pub fn adpsnsim(&self) -> ADPSNSIM_R`[src]

Bit 25 - ADP sense interrupt mask

`pub fn adptoim(&self) -> ADPTOIM_R`[src]

Bit 26 - ADP timeout interrupt mask

`pub fn ar(&self) -> AR_R`[src]

Bits 27:28 - Access request

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF4>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint Tx FIFO depth

`impl R<u32, Reg<u32, _OTG_FS_DIEPTXF5>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint Tx FIFO depth

`impl R<u32, Reg<u32, _OTG_FS_GLPMCFG>>`[src]

`pub fn lpmen(&self) -> LPMEN_R`[src]

Bit 0 - LPM support enable

`pub fn lpmack(&self) -> LPMACK_R`[src]

Bit 1 - LPM token acknowledge enable

`pub fn besl(&self) -> BESL_R`[src]

Bits 2:5 - Best effort service latency

`pub fn remwake(&self) -> REMWAKE_R`[src]

Bit 6 - bRemoteWake value

`pub fn l1ssen(&self) -> L1SSEN_R`[src]

Bit 7 - L1 Shallow Sleep enable

`pub fn beslthrs(&self) -> BESLTHRS_R`[src]

Bits 8:11 - BESL threshold

`pub fn l1dsen(&self) -> L1DSEN_R`[src]

Bit 12 - L1 deep sleep enable

`pub fn lpmrst(&self) -> LPMRST_R`[src]

Bits 13:14 - LPM response

`pub fn slpsts(&self) -> SLPSTS_R`[src]

Bit 15 - Port sleep status

`pub fn l1rsmok(&self) -> L1RSMOK_R`[src]

Bit 16 - Sleep State Resume OK

`pub fn lpmchidx(&self) -> LPMCHIDX_R`[src]

Bits 17:20 - LPM Channel Index

`pub fn lpmrcnt(&self) -> LPMRCNT_R`[src]

Bits 21:23 - LPM retry count

`pub fn sndlpm(&self) -> SNDLPM_R`[src]

Bit 24 - Send LPM transaction

`pub fn lpmrcntsts(&self) -> LPMRCNTSTS_R`[src]

Bits 25:27 - LPM retry count status

`pub fn enbesl(&self) -> ENBESL_R`[src]

Bit 28 - Enable best effort service latency

`impl R<u32, Reg<u32, _OTG_HS_GOTGCTL>>`[src]

`pub fn srqscs(&self) -> SRQSCS_R`[src]

Bit 0 - Session request success

`pub fn srq(&self) -> SRQ_R`[src]

Bit 1 - Session request

`pub fn hngscs(&self) -> HNGSCS_R`[src]

Bit 8 - Host negotiation success

`pub fn hnprq(&self) -> HNPRQ_R`[src]

Bit 9 - HNP request

`pub fn hshnpen(&self) -> HSHNPEN_R`[src]

Bit 10 - Host set HNP enable

`pub fn dhnpen(&self) -> DHNPEN_R`[src]

Bit 11 - Device HNP enabled

`pub fn cidsts(&self) -> CIDSTS_R`[src]

Bit 16 - Connector ID status

`pub fn dbct(&self) -> DBCT_R`[src]

Bit 17 - Long/short debounce time

`pub fn asvld(&self) -> ASVLD_R`[src]

Bit 18 - A-session valid

`pub fn bsvld(&self) -> BSVLD_R`[src]

Bit 19 - B-session valid

`pub fn ehen(&self) -> EHEN_R`[src]

Bit 12 - Embedded host enable

`impl R<u32, Reg<u32, _OTG_HS_GOTGINT>>`[src]

`pub fn sedet(&self) -> SEDET_R`[src]

Bit 2 - Session end detected

`pub fn srsschg(&self) -> SRSSCHG_R`[src]

Bit 8 - Session request success status change

`pub fn hnsschg(&self) -> HNSSCHG_R`[src]

Bit 9 - Host negotiation success status change

`pub fn hngdet(&self) -> HNGDET_R`[src]

Bit 17 - Host negotiation detected

`pub fn adtochg(&self) -> ADTOCHG_R`[src]

Bit 18 - A-device timeout change

`pub fn dbcdne(&self) -> DBCDNE_R`[src]

Bit 19 - Debounce done

`pub fn idchng(&self) -> IDCHNG_R`[src]

Bit 20 - ID input pin changed

`impl R<u32, Reg<u32, _OTG_HS_GAHBCFG>>`[src]

`pub fn gint(&self) -> GINT_R`[src]

Bit 0 - Global interrupt mask

`pub fn hbstlen(&self) -> HBSTLEN_R`[src]

Bits 1:4 - Burst length/type

`pub fn dmaen(&self) -> DMAEN_R`[src]

Bit 5 - DMA enable

`pub fn txfelvl(&self) -> TXFELVL_R`[src]

Bit 7 - TxFIFO empty level

`pub fn ptxfelvl(&self) -> PTXFELVL_R`[src]

Bit 8 - Periodic TxFIFO empty level

`impl R<u32, Reg<u32, _OTG_HS_GUSBCFG>>`[src]

`pub fn tocal(&self) -> TOCAL_R`[src]

Bits 0:2 - FS timeout calibration

`pub fn srpcap(&self) -> SRPCAP_R`[src]

Bit 8 - SRP-capable

`pub fn hnpcap(&self) -> HNPCAP_R`[src]

Bit 9 - HNP-capable

`pub fn trdt(&self) -> TRDT_R`[src]

Bits 10:13 - USB turnaround time

`pub fn phylpcs(&self) -> PHYLPCS_R`[src]

Bit 15 - PHY Low-power clock select

`pub fn ulpifsls(&self) -> ULPIFSLS_R`[src]

Bit 17 - ULPI FS/LS select

`pub fn ulpiar(&self) -> ULPIAR_R`[src]

Bit 18 - ULPI Auto-resume

`pub fn ulpicsm(&self) -> ULPICSM_R`[src]

Bit 19 - ULPI Clock SuspendM

`pub fn ulpievbusd(&self) -> ULPIEVBUSD_R`[src]

Bit 20 - ULPI External VBUS Drive

`pub fn ulpievbusi(&self) -> ULPIEVBUSI_R`[src]

Bit 21 - ULPI external VBUS indicator

`pub fn tsdps(&self) -> TSDPS_R`[src]

Bit 22 - TermSel DLine pulsing selection

`pub fn pcci(&self) -> PCCI_R`[src]

Bit 23 - Indicator complement

`pub fn ptci(&self) -> PTCI_R`[src]

Bit 24 - Indicator pass through

`pub fn ulpiipd(&self) -> ULPIIPD_R`[src]

Bit 25 - ULPI interface protect disable

`pub fn fhmod(&self) -> FHMOD_R`[src]

Bit 29 - Forced host mode

`pub fn fdmod(&self) -> FDMOD_R`[src]

Bit 30 - Forced peripheral mode

`impl R<u32, Reg<u32, _OTG_HS_GRSTCTL>>`[src]

`pub fn csrst(&self) -> CSRST_R`[src]

Bit 0 - Core soft reset

`pub fn hsrst(&self) -> HSRST_R`[src]

Bit 1 - HCLK soft reset

`pub fn fcrst(&self) -> FCRST_R`[src]

Bit 2 - Host frame counter reset

`pub fn rxfflsh(&self) -> RXFFLSH_R`[src]

Bit 4 - RxFIFO flush

`pub fn txfflsh(&self) -> TXFFLSH_R`[src]

Bit 5 - TxFIFO flush

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 6:10 - TxFIFO number

`pub fn ahbidl(&self) -> AHBIDL_R`[src]

Bit 31 - AHB master idle

`pub fn dmareq(&self) -> DMAREQ_R`[src]

Bit 30 - DMA request signal enabled for USB OTG HS

`impl R<u32, Reg<u32, _OTG_HS_GINTSTS>>`[src]

`pub fn cmod(&self) -> CMOD_R`[src]

Bit 0 - Current mode of operation

`pub fn mmis(&self) -> MMIS_R`[src]

Bit 1 - Mode mismatch interrupt

`pub fn otgint(&self) -> OTGINT_R`[src]

Bit 2 - OTG interrupt

`pub fn sof(&self) -> SOF_R`[src]

Bit 3 - Start of frame

`pub fn rxflvl(&self) -> RXFLVL_R`[src]

Bit 4 - RxFIFO nonempty

`pub fn nptxfe(&self) -> NPTXFE_R`[src]

Bit 5 - Nonperiodic TxFIFO empty

`pub fn ginakeff(&self) -> GINAKEFF_R`[src]

Bit 6 - Global IN nonperiodic NAK effective

`pub fn boutnakeff(&self) -> BOUTNAKEFF_R`[src]

Bit 7 - Global OUT NAK effective

`pub fn esusp(&self) -> ESUSP_R`[src]

Bit 10 - Early suspend

`pub fn usbsusp(&self) -> USBSUSP_R`[src]

Bit 11 - USB suspend

`pub fn usbrst(&self) -> USBRST_R`[src]

Bit 12 - USB reset

`pub fn enumdne(&self) -> ENUMDNE_R`[src]

Bit 13 - Enumeration done

`pub fn isoodrp(&self) -> ISOODRP_R`[src]

Bit 14 - Isochronous OUT packet dropped interrupt

`pub fn eopf(&self) -> EOPF_R`[src]

Bit 15 - End of periodic frame interrupt

`pub fn iepint(&self) -> IEPINT_R`[src]

Bit 18 - IN endpoint interrupt

`pub fn oepint(&self) -> OEPINT_R`[src]

Bit 19 - OUT endpoint interrupt

`pub fn iisoixfr(&self) -> IISOIXFR_R`[src]

Bit 20 - Incomplete isochronous IN transfer

`pub fn pxfr_incompisoout(&self) -> PXFR_INCOMPISOOUT_R`[src]

Bit 21 - Incomplete periodic transfer

`pub fn datafsusp(&self) -> DATAFSUSP_R`[src]

Bit 22 - Data fetch suspended

`pub fn hprtint(&self) -> HPRTINT_R`[src]

Bit 24 - Host port interrupt

`pub fn hcint(&self) -> HCINT_R`[src]

Bit 25 - Host channels interrupt

`pub fn ptxfe(&self) -> PTXFE_R`[src]

Bit 26 - Periodic TxFIFO empty

`pub fn cidschg(&self) -> CIDSCHG_R`[src]

Bit 28 - Connector ID status change

`pub fn discint(&self) -> DISCINT_R`[src]

Bit 29 - Disconnect detected interrupt

`pub fn srqint(&self) -> SRQINT_R`[src]

Bit 30 - Session request/new session detected interrupt

`pub fn wkuint(&self) -> WKUINT_R`[src]

Bit 31 - Resume/remote wakeup detected interrupt

`impl R<u32, Reg<u32, _OTG_HS_GINTMSK>>`[src]

`pub fn mmism(&self) -> MMISM_R`[src]

Bit 1 - Mode mismatch interrupt mask

`pub fn otgint(&self) -> OTGINT_R`[src]

Bit 2 - OTG interrupt mask

`pub fn sofm(&self) -> SOFM_R`[src]

Bit 3 - Start of frame mask

`pub fn rxflvlm(&self) -> RXFLVLM_R`[src]

Bit 4 - Receive FIFO nonempty mask

`pub fn nptxfem(&self) -> NPTXFEM_R`[src]

Bit 5 - Nonperiodic TxFIFO empty mask

`pub fn ginakeffm(&self) -> GINAKEFFM_R`[src]

Bit 6 - Global nonperiodic IN NAK effective mask

`pub fn gonakeffm(&self) -> GONAKEFFM_R`[src]

Bit 7 - Global OUT NAK effective mask

`pub fn esuspm(&self) -> ESUSPM_R`[src]

Bit 10 - Early suspend mask

`pub fn usbsuspm(&self) -> USBSUSPM_R`[src]

Bit 11 - USB suspend mask

`pub fn usbrst(&self) -> USBRST_R`[src]

Bit 12 - USB reset mask

`pub fn enumdnem(&self) -> ENUMDNEM_R`[src]

Bit 13 - Enumeration done mask

`pub fn isoodrpm(&self) -> ISOODRPM_R`[src]

Bit 14 - Isochronous OUT packet dropped interrupt mask

`pub fn eopfm(&self) -> EOPFM_R`[src]

Bit 15 - End of periodic frame interrupt mask

`pub fn iepint(&self) -> IEPINT_R`[src]

Bit 18 - IN endpoints interrupt mask

`pub fn oepint(&self) -> OEPINT_R`[src]

Bit 19 - OUT endpoints interrupt mask

`pub fn iisoixfrm(&self) -> IISOIXFRM_R`[src]

Bit 20 - Incomplete isochronous IN transfer mask

`pub fn pxfrm_iisooxfrm(&self) -> PXFRM_IISOOXFRM_R`[src]

Bit 21 - Incomplete periodic transfer mask

`pub fn fsuspm(&self) -> FSUSPM_R`[src]

Bit 22 - Data fetch suspended mask

`pub fn prtim(&self) -> PRTIM_R`[src]

Bit 24 - Host port interrupt mask

`pub fn hcim(&self) -> HCIM_R`[src]

Bit 25 - Host channels interrupt mask

`pub fn ptxfem(&self) -> PTXFEM_R`[src]

Bit 26 - Periodic TxFIFO empty mask

`pub fn cidschgm(&self) -> CIDSCHGM_R`[src]

Bit 28 - Connector ID status change mask

`pub fn discint(&self) -> DISCINT_R`[src]

Bit 29 - Disconnect detected interrupt mask

`pub fn srqim(&self) -> SRQIM_R`[src]

Bit 30 - Session request/new session detected interrupt mask

`pub fn wuim(&self) -> WUIM_R`[src]

Bit 31 - Resume/remote wakeup detected interrupt mask

`pub fn rstde(&self) -> RSTDE_R`[src]

Bit 23 - Reset detected interrupt mask

`pub fn lpmintm(&self) -> LPMINTM_R`[src]

Bit 27 - LPM interrupt mask

`impl R<u32, Reg<u32, _OTG_HS_GRXSTSR_HOST>>`[src]

`pub fn chnum(&self) -> CHNUM_R`[src]

Bits 0:3 - Channel number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`impl R<u32, Reg<u32, _OTG_HS_GRXSTSP_HOST>>`[src]

`pub fn chnum(&self) -> CHNUM_R`[src]

Bits 0:3 - Channel number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`impl R<u32, Reg<u32, _OTG_HS_GRXFSIZ>>`[src]

`pub fn rxfd(&self) -> RXFD_R`[src]

Bits 0:15 - RxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_HNPTXFSIZ_HOST>>`[src]

`pub fn nptxfsa(&self) -> NPTXFSA_R`[src]

Bits 0:15 - Nonperiodic transmit RAM start address

`pub fn nptxfd(&self) -> NPTXFD_R`[src]

Bits 16:31 - Nonperiodic TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF0_DEVICE>>`[src]

`pub fn tx0fsa(&self) -> TX0FSA_R`[src]

Bits 0:15 - Endpoint 0 transmit RAM start address

`pub fn tx0fd(&self) -> TX0FD_R`[src]

Bits 16:31 - Endpoint 0 TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_GNPTXSTS>>`[src]

`pub fn nptxfsav(&self) -> NPTXFSAV_R`[src]

Bits 0:15 - Nonperiodic TxFIFO space available

`pub fn nptqxsav(&self) -> NPTQXSAV_R`[src]

Bits 16:23 - Nonperiodic transmit request queue space available

`pub fn nptxqtop(&self) -> NPTXQTOP_R`[src]

Bits 24:30 - Top of the nonperiodic transmit request queue

`impl R<u32, Reg<u32, _OTG_HS_GCCFG>>`[src]

`pub fn pwrdwn(&self) -> PWRDWN_R`[src]

Bit 16 - Power down

`pub fn bcden(&self) -> BCDEN_R`[src]

Bit 17 - Battery charging detector (BCD) enable

`pub fn dcden(&self) -> DCDEN_R`[src]

Bit 18 - Data contact detection (DCD) mode enable

`pub fn pden(&self) -> PDEN_R`[src]

Bit 19 - Primary detection (PD) mode enable

`pub fn sden(&self) -> SDEN_R`[src]

Bit 20 - Secondary detection (SD) mode enable

`pub fn vbden(&self) -> VBDEN_R`[src]

Bit 21 - USB VBUS detection enable

`pub fn dcdet(&self) -> DCDET_R`[src]

Bit 0 - Data contact detection (DCD) status

`pub fn pdet(&self) -> PDET_R`[src]

Bit 1 - Primary detection (PD) status

`pub fn sdet(&self) -> SDET_R`[src]

Bit 2 - Secondary detection (SD) status

`pub fn ps2det(&self) -> PS2DET_R`[src]

Bit 3 - DM pull-up detection status

`impl R<u32, Reg<u32, _OTG_HS_CID>>`[src]

`pub fn product_id(&self) -> PRODUCT_ID_R`[src]

Bits 0:31 - Product ID field

`impl R<u32, Reg<u32, _OTG_HS_HPTXFSIZ>>`[src]

`pub fn ptxsa(&self) -> PTXSA_R`[src]

Bits 0:15 - Host periodic TxFIFO start address

`pub fn ptxfd(&self) -> PTXFD_R`[src]

Bits 16:31 - Host periodic TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF1>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF2>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF3>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF4>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF5>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF6>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_DIEPTXF7>>`[src]

`pub fn ineptxsa(&self) -> INEPTXSA_R`[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

`pub fn ineptxfd(&self) -> INEPTXFD_R`[src]

Bits 16:31 - IN endpoint TxFIFO depth

`impl R<u32, Reg<u32, _OTG_HS_GRXSTSR_DEVICE>>`[src]

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 0:3 - Endpoint number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`pub fn frmnum(&self) -> FRMNUM_R`[src]

Bits 21:24 - Frame number

`impl R<u32, Reg<u32, _OTG_HS_GRXSTSP_DEVICE>>`[src]

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 0:3 - Endpoint number

`pub fn bcnt(&self) -> BCNT_R`[src]

Bits 4:14 - Byte count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 15:16 - Data PID

`pub fn pktsts(&self) -> PKTSTS_R`[src]

Bits 17:20 - Packet status

`pub fn frmnum(&self) -> FRMNUM_R`[src]

Bits 21:24 - Frame number

`impl R<u32, Reg<u32, _OTG_HS_GLPMCFG>>`[src]

`pub fn lpmen(&self) -> LPMEN_R`[src]

Bit 0 - LPM support enable

`pub fn lpmack(&self) -> LPMACK_R`[src]

Bit 1 - LPM token acknowledge enable

`pub fn besl(&self) -> BESL_R`[src]

Bits 2:5 - Best effort service latency

`pub fn remwake(&self) -> REMWAKE_R`[src]

Bit 6 - bRemoteWake value

`pub fn l1ssen(&self) -> L1SSEN_R`[src]

Bit 7 - L1 Shallow Sleep enable

`pub fn beslthrs(&self) -> BESLTHRS_R`[src]

Bits 8:11 - BESL threshold

`pub fn l1dsen(&self) -> L1DSEN_R`[src]

Bit 12 - L1 deep sleep enable

`pub fn lpmrst(&self) -> LPMRST_R`[src]

Bits 13:14 - LPM response

`pub fn slpsts(&self) -> SLPSTS_R`[src]

Bit 15 - Port sleep status

`pub fn l1rsmok(&self) -> L1RSMOK_R`[src]

Bit 16 - Sleep State Resume OK

`pub fn lpmchidx(&self) -> LPMCHIDX_R`[src]

Bits 17:20 - LPM Channel Index

`pub fn lpmrcnt(&self) -> LPMRCNT_R`[src]

Bits 21:23 - LPM retry count

`pub fn sndlpm(&self) -> SNDLPM_R`[src]

Bit 24 - Send LPM transaction

`pub fn lpmrcntsts(&self) -> LPMRCNTSTS_R`[src]

Bits 25:27 - LPM retry count status

`pub fn enbesl(&self) -> ENBESL_R`[src]

Bit 28 - Enable best effort service latency

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn en(&self) -> EN_R`[src]

Bit 0 - Peripheral enable

`pub fn wrie(&self) -> WRIE_R`[src]

Bit 1 - Register write interrupt enable

`pub fn rdie(&self) -> RDIE_R`[src]

Bit 2 - Register Read Interrupt Enable

`pub fn eie(&self) -> EIE_R`[src]

Bit 3 - Error interrupt enable

`pub fn dpc(&self) -> DPC_R`[src]

Bit 7 - Disable Preamble Check

`pub fn port_address(&self) -> PORT_ADDRESS_R`[src]

Bits 8:12 - Slaves's address

`impl R<u32, Reg<u32, _WRFR>>`[src]

`pub fn wrf(&self) -> WRF_R`[src]

Bits 0:31 - Write flags for MDIO registers 0 to 31

`impl R<u32, Reg<u32, _CWRFR>>`[src]

`pub fn cwrf(&self) -> CWRF_R`[src]

Bits 0:31 - Clear the write flag

`impl R<u32, Reg<u32, _RDFR>>`[src]

`pub fn rdf(&self) -> RDF_R`[src]

Bits 0:31 - Read flags for MDIO registers 0 to 31

`impl R<u32, Reg<u32, _CRDFR>>`[src]

`pub fn crdf(&self) -> CRDF_R`[src]

Bits 0:31 - Clear the read flag

`impl R<u32, Reg<u32, _SR>>`[src]

`pub fn perf(&self) -> PERF_R`[src]

Bit 0 - Preamble error flag

`pub fn serf(&self) -> SERF_R`[src]

Bit 1 - Start error flag

`pub fn terf(&self) -> TERF_R`[src]

Bit 2 - Turnaround error flag

`impl R<u32, Reg<u32, _CLRFR>>`[src]

`pub fn cperf(&self) -> CPERF_R`[src]

Bit 0 - Clear the preamble error flag

`pub fn cserf(&self) -> CSERF_R`[src]

Bit 1 - Clear the start error flag

`pub fn cterf(&self) -> CTERF_R`[src]

Bit 2 - Clear the turnaround error flag

`impl R<u32, Reg<u32, _DINR>>`[src]

`pub fn din(&self) -> DIN_R`[src]

Bits 0:15 - Input data received from MDIO Master during write frames

`impl R<u32, Reg<u32, _DOUTR>>`[src]

`pub fn dout(&self) -> DOUT_R`[src]

Bits 0:15 - Output data sent to MDIO Master during read frames

`impl R<u32, Reg<u32, _DFSDM_CHCFG0R1>>`[src]

`pub fn sitp(&self) -> SITP_R`[src]

Bits 0:1 - Serial interface type for channel 0

`pub fn spicksel(&self) -> SPICKSEL_R`[src]

Bits 2:3 - SPI clock select for channel 0

`pub fn scden(&self) -> SCDEN_R`[src]

Bit 5 - Short-circuit detector enable on channel 0

`pub fn ckaben(&self) -> CKABEN_R`[src]

Bit 6 - Clock absence detector enable on channel 0

`pub fn chen(&self) -> CHEN_R`[src]

Bit 7 - Channel 0 enable

`pub fn chinsel(&self) -> CHINSEL_R`[src]

Bit 8 - Channel inputs selection

`pub fn datmpx(&self) -> DATMPX_R`[src]

Bits 12:13 - Input data multiplexer for channel 0

`pub fn datpack(&self) -> DATPACK_R`[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

`pub fn ckoutdiv(&self) -> CKOUTDIV_R`[src]

Bits 16:23 - Output serial clock divider

`pub fn ckoutsrc(&self) -> CKOUTSRC_R`[src]

Bit 30 - Output serial clock source selection

`pub fn dfsdmen(&self) -> DFSDMEN_R`[src]

Bit 31 - Global enable for DFSDM interface

`impl R<u32, Reg<u32, _DFSDM_CHCFG1R1>>`[src]

`pub fn sitp(&self) -> SITP_R`[src]

Bits 0:1 - Serial interface type for channel 1

`pub fn spicksel(&self) -> SPICKSEL_R`[src]

Bits 2:3 - SPI clock select for channel 1

`pub fn scden(&self) -> SCDEN_R`[src]

Bit 5 - Short-circuit detector enable on channel 1

`pub fn ckaben(&self) -> CKABEN_R`[src]

Bit 6 - Clock absence detector enable on channel 1

`pub fn chen(&self) -> CHEN_R`[src]

Bit 7 - Channel 1 enable

`pub fn chinsel(&self) -> CHINSEL_R`[src]

Bit 8 - Channel inputs selection

`pub fn datmpx(&self) -> DATMPX_R`[src]

Bits 12:13 - Input data multiplexer for channel 1

`pub fn datpack(&self) -> DATPACK_R`[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

`pub fn ckoutdiv(&self) -> CKOUTDIV_R`[src]

Bits 16:23 - Output serial clock divider

`pub fn ckoutsrc(&self) -> CKOUTSRC_R`[src]

Bit 30 - Output serial clock source selection

`pub fn dfsdmen(&self) -> DFSDMEN_R`[src]

Bit 31 - Global enable for DFSDM interface

`impl R<u32, Reg<u32, _DFSDM_CHCFG2R1>>`[src]

`pub fn sitp(&self) -> SITP_R`[src]

Bits 0:1 - Serial interface type for channel 2

`pub fn spicksel(&self) -> SPICKSEL_R`[src]

Bits 2:3 - SPI clock select for channel 2

`pub fn scden(&self) -> SCDEN_R`[src]

Bit 5 - Short-circuit detector enable on channel 2

`pub fn ckaben(&self) -> CKABEN_R`[src]

Bit 6 - Clock absence detector enable on channel 2

`pub fn chen(&self) -> CHEN_R`[src]

Bit 7 - Channel 2 enable

`pub fn chinsel(&self) -> CHINSEL_R`[src]

Bit 8 - Channel inputs selection

`pub fn datmpx(&self) -> DATMPX_R`[src]

Bits 12:13 - Input data multiplexer for channel 2

`pub fn datpack(&self) -> DATPACK_R`[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

`pub fn ckoutdiv(&self) -> CKOUTDIV_R`[src]

Bits 16:23 - Output serial clock divider

`pub fn ckoutsrc(&self) -> CKOUTSRC_R`[src]

Bit 30 - Output serial clock source selection

`pub fn dfsdmen(&self) -> DFSDMEN_R`[src]

Bit 31 - Global enable for DFSDM interface

`impl R<u32, Reg<u32, _DFSDM_CHCFG3R1>>`[src]

`pub fn sitp(&self) -> SITP_R`[src]

Bits 0:1 - Serial interface type for channel 3

`pub fn spicksel(&self) -> SPICKSEL_R`[src]

Bits 2:3 - SPI clock select for channel 3

`pub fn scden(&self) -> SCDEN_R`[src]

Bit 5 - Short-circuit detector enable on channel 3

`pub fn ckaben(&self) -> CKABEN_R`[src]

Bit 6 - Clock absence detector enable on channel 3

`pub fn chen(&self) -> CHEN_R`[src]

Bit 7 - Channel 3 enable

`pub fn chinsel(&self) -> CHINSEL_R`[src]

Bit 8 - Channel inputs selection

`pub fn datmpx(&self) -> DATMPX_R`[src]

Bits 12:13 - Input data multiplexer for channel 3

`pub fn datpack(&self) -> DATPACK_R`[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

`pub fn ckoutdiv(&self) -> CKOUTDIV_R`[src]

Bits 16:23 - Output serial clock divider

`pub fn ckoutsrc(&self) -> CKOUTSRC_R`[src]

Bit 30 - Output serial clock source selection

`pub fn dfsdmen(&self) -> DFSDMEN_R`[src]

Bit 31 - Global enable for DFSDM interface

`impl R<u32, Reg<u32, _DFSDM_CHCFG4R1>>`[src]

`pub fn sitp(&self) -> SITP_R`[src]

Bits 0:1 - Serial interface type for channel 4

`pub fn spicksel(&self) -> SPICKSEL_R`[src]

Bits 2:3 - SPI clock select for channel 4

`pub fn scden(&self) -> SCDEN_R`[src]

Bit 5 - Short-circuit detector enable on channel 4

`pub fn ckaben(&self) -> CKABEN_R`[src]

Bit 6 - Clock absence detector enable on channel 4

`pub fn chen(&self) -> CHEN_R`[src]

Bit 7 - Channel 4 enable

`pub fn chinsel(&self) -> CHINSEL_R`[src]

Bit 8 - Channel inputs selection

`pub fn datmpx(&self) -> DATMPX_R`[src]

Bits 12:13 - Input data multiplexer for channel 4

`pub fn datpack(&self) -> DATPACK_R`[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

`pub fn ckoutdiv(&self) -> CKOUTDIV_R`[src]

Bits 16:23 - Output serial clock divider

`pub fn ckoutsrc(&self) -> CKOUTSRC_R`[src]

Bit 30 - Output serial clock source selection

`pub fn dfsdmen(&self) -> DFSDMEN_R`[src]

Bit 31 - Global enable for DFSDM interface

`impl R<u32, Reg<u32, _DFSDM_CHCFG5R1>>`[src]

`pub fn sitp(&self) -> SITP_R`[src]

Bits 0:1 - Serial interface type for channel 5

`pub fn spicksel(&self) -> SPICKSEL_R`[src]

Bits 2:3 - SPI clock select for channel 5

`pub fn scden(&self) -> SCDEN_R`[src]

Bit 5 - Short-circuit detector enable on channel 5

`pub fn ckaben(&self) -> CKABEN_R`[src]

Bit 6 - Clock absence detector enable on channel 5

`pub fn chen(&self) -> CHEN_R`[src]

Bit 7 - Channel 5 enable

`pub fn chinsel(&self) -> CHINSEL_R`[src]

Bit 8 - Channel inputs selection

`pub fn datmpx(&self) -> DATMPX_R`[src]

Bits 12:13 - Input data multiplexer for channel 5

`pub fn datpack(&self) -> DATPACK_R`[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

`pub fn ckoutdiv(&self) -> CKOUTDIV_R`[src]

Bits 16:23 - Output serial clock divider

`pub fn ckoutsrc(&self) -> CKOUTSRC_R`[src]

Bit 30 - Output serial clock source selection

`pub fn dfsdmen(&self) -> DFSDMEN_R`[src]

Bit 31 - Global enable for DFSDM interface

`impl R<u32, Reg<u32, _DFSDM_CHCFG6R1>>`[src]

`pub fn sitp(&self) -> SITP_R`[src]

Bits 0:1 - Serial interface type for channel 6

`pub fn spicksel(&self) -> SPICKSEL_R`[src]

Bits 2:3 - SPI clock select for channel 6

`pub fn scden(&self) -> SCDEN_R`[src]

Bit 5 - Short-circuit detector enable on channel 6

`pub fn ckaben(&self) -> CKABEN_R`[src]

Bit 6 - Clock absence detector enable on channel 6

`pub fn chen(&self) -> CHEN_R`[src]

Bit 7 - Channel 6 enable

`pub fn chinsel(&self) -> CHINSEL_R`[src]

Bit 8 - Channel inputs selection

`pub fn datmpx(&self) -> DATMPX_R`[src]

Bits 12:13 - Input data multiplexer for channel 6

`pub fn datpack(&self) -> DATPACK_R`[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

`pub fn ckoutdiv(&self) -> CKOUTDIV_R`[src]

Bits 16:23 - Output serial clock divider

`pub fn ckoutsrc(&self) -> CKOUTSRC_R`[src]

Bit 30 - Output serial clock source selection

`pub fn dfsdmen(&self) -> DFSDMEN_R`[src]

Bit 31 - Global enable for DFSDM interface

`impl R<u32, Reg<u32, _DFSDM_CHCFG7R1>>`[src]

`pub fn sitp(&self) -> SITP_R`[src]

Bits 0:1 - Serial interface type for channel 7

`pub fn spicksel(&self) -> SPICKSEL_R`[src]

Bits 2:3 - SPI clock select for channel 7

`pub fn scden(&self) -> SCDEN_R`[src]

Bit 5 - Short-circuit detector enable on channel 7

`pub fn ckaben(&self) -> CKABEN_R`[src]

Bit 6 - Clock absence detector enable on channel 7

`pub fn chen(&self) -> CHEN_R`[src]

Bit 7 - Channel 7 enable

`pub fn chinsel(&self) -> CHINSEL_R`[src]

Bit 8 - Channel inputs selection

`pub fn datmpx(&self) -> DATMPX_R`[src]

Bits 12:13 - Input data multiplexer for channel 7

`pub fn datpack(&self) -> DATPACK_R`[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

`pub fn ckoutdiv(&self) -> CKOUTDIV_R`[src]

Bits 16:23 - Output serial clock divider

`pub fn ckoutsrc(&self) -> CKOUTSRC_R`[src]

Bit 30 - Output serial clock source selection

`pub fn dfsdmen(&self) -> DFSDMEN_R`[src]

Bit 31 - Global enable for DFSDM interface

`impl R<u32, Reg<u32, _DFSDM_CHCFG0R2>>`[src]

`pub fn dtrbs(&self) -> DTRBS_R`[src]

Bits 3:7 - Data right bit-shift for channel 0

`pub fn offset(&self) -> OFFSET_R`[src]

Bits 8:31 - 24-bit calibration offset for channel 0

`impl R<u32, Reg<u32, _DFSDM_CHCFG1R2>>`[src]

`pub fn dtrbs(&self) -> DTRBS_R`[src]

Bits 3:7 - Data right bit-shift for channel 1

`pub fn offset(&self) -> OFFSET_R`[src]

Bits 8:31 - 24-bit calibration offset for channel 1

`impl R<u32, Reg<u32, _DFSDM_CHCFG2R2>>`[src]

`pub fn dtrbs(&self) -> DTRBS_R`[src]

Bits 3:7 - Data right bit-shift for channel 2

`pub fn offset(&self) -> OFFSET_R`[src]

Bits 8:31 - 24-bit calibration offset for channel 2

`impl R<u32, Reg<u32, _DFSDM_CHCFG3R2>>`[src]

`pub fn dtrbs(&self) -> DTRBS_R`[src]

Bits 3:7 - Data right bit-shift for channel 3

`pub fn offset(&self) -> OFFSET_R`[src]

Bits 8:31 - 24-bit calibration offset for channel 3

`impl R<u32, Reg<u32, _DFSDM_CHCFG4R2>>`[src]

`pub fn dtrbs(&self) -> DTRBS_R`[src]

Bits 3:7 - Data right bit-shift for channel 4

`pub fn offset(&self) -> OFFSET_R`[src]

Bits 8:31 - 24-bit calibration offset for channel 4

`impl R<u32, Reg<u32, _DFSDM_CHCFG5R2>>`[src]

`pub fn dtrbs(&self) -> DTRBS_R`[src]

Bits 3:7 - Data right bit-shift for channel 5

`pub fn offset(&self) -> OFFSET_R`[src]

Bits 8:31 - 24-bit calibration offset for channel 5

`impl R<u32, Reg<u32, _DFSDM_CHCFG6R2>>`[src]

`pub fn dtrbs(&self) -> DTRBS_R`[src]

Bits 3:7 - Data right bit-shift for channel 6

`pub fn offset(&self) -> OFFSET_R`[src]

Bits 8:31 - 24-bit calibration offset for channel 6

`impl R<u32, Reg<u32, _DFSDM_CHCFG7R2>>`[src]

`pub fn dtrbs(&self) -> DTRBS_R`[src]

Bits 3:7 - Data right bit-shift for channel 7

`pub fn offset(&self) -> OFFSET_R`[src]

Bits 8:31 - 24-bit calibration offset for channel 7

`impl R<u32, Reg<u32, _DFSDM_AWSCD0R>>`[src]

`pub fn scdt(&self) -> SCDT_R`[src]

Bits 0:7 - short-circuit detector threshold for channel 0

`pub fn bkscd(&self) -> BKSCD_R`[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 0

`pub fn awfosr(&self) -> AWFOSR_R`[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 0

`pub fn awford(&self) -> AWFORD_R`[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 0

`impl R<u32, Reg<u32, _DFSDM_AWSCD1R>>`[src]

`pub fn scdt(&self) -> SCDT_R`[src]

Bits 0:7 - short-circuit detector threshold for channel 1

`pub fn bkscd(&self) -> BKSCD_R`[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 1

`pub fn awfosr(&self) -> AWFOSR_R`[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 1

`pub fn awford(&self) -> AWFORD_R`[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 1

`impl R<u32, Reg<u32, _DFSDM_AWSCD2R>>`[src]

`pub fn scdt(&self) -> SCDT_R`[src]

Bits 0:7 - short-circuit detector threshold for channel 2

`pub fn bkscd(&self) -> BKSCD_R`[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 2

`pub fn awfosr(&self) -> AWFOSR_R`[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 2

`pub fn awford(&self) -> AWFORD_R`[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 2

`impl R<u32, Reg<u32, _DFSDM_AWSCD3R>>`[src]

`pub fn scdt(&self) -> SCDT_R`[src]

Bits 0:7 - short-circuit detector threshold for channel 3

`pub fn bkscd(&self) -> BKSCD_R`[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 3

`pub fn awfosr(&self) -> AWFOSR_R`[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 3

`pub fn awford(&self) -> AWFORD_R`[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 3

`impl R<u32, Reg<u32, _DFSDM_AWSCD4R>>`[src]

`pub fn scdt(&self) -> SCDT_R`[src]

Bits 0:7 - short-circuit detector threshold for channel 4

`pub fn bkscd(&self) -> BKSCD_R`[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 4

`pub fn awfosr(&self) -> AWFOSR_R`[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 4

`pub fn awford(&self) -> AWFORD_R`[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 4

`impl R<u32, Reg<u32, _DFSDM_AWSCD5R>>`[src]

`pub fn scdt(&self) -> SCDT_R`[src]

Bits 0:7 - short-circuit detector threshold for channel 5

`pub fn bkscd(&self) -> BKSCD_R`[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 5

`pub fn awfosr(&self) -> AWFOSR_R`[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 5

`pub fn awford(&self) -> AWFORD_R`[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 5

`impl R<u32, Reg<u32, _DFSDM_AWSCD6R>>`[src]

`pub fn scdt(&self) -> SCDT_R`[src]

Bits 0:7 - short-circuit detector threshold for channel 6

`pub fn bkscd(&self) -> BKSCD_R`[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 6

`pub fn awfosr(&self) -> AWFOSR_R`[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 6

`pub fn awford(&self) -> AWFORD_R`[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 6

`impl R<u32, Reg<u32, _DFSDM_AWSCD7R>>`[src]

`pub fn scdt(&self) -> SCDT_R`[src]

Bits 0:7 - short-circuit detector threshold for channel 7

`pub fn bkscd(&self) -> BKSCD_R`[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 7

`pub fn awfosr(&self) -> AWFOSR_R`[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 7

`pub fn awford(&self) -> AWFORD_R`[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 7

`impl R<u32, Reg<u32, _DFSDM_CHWDAT0R>>`[src]

`pub fn wdata(&self) -> WDATA_R`[src]

Bits 0:15 - Input channel y watchdog data

`impl R<u32, Reg<u32, _DFSDM_CHWDAT1R>>`[src]

`pub fn wdata(&self) -> WDATA_R`[src]

Bits 0:15 - Input channel y watchdog data

`impl R<u32, Reg<u32, _DFSDM_CHWDAT2R>>`[src]

`pub fn wdata(&self) -> WDATA_R`[src]

Bits 0:15 - Input channel y watchdog data

`impl R<u32, Reg<u32, _DFSDM_CHWDAT3R>>`[src]

`pub fn wdata(&self) -> WDATA_R`[src]

Bits 0:15 - Input channel y watchdog data

`impl R<u32, Reg<u32, _DFSDM_CHWDAT4R>>`[src]

`pub fn wdata(&self) -> WDATA_R`[src]

Bits 0:15 - Input channel y watchdog data

`impl R<u32, Reg<u32, _DFSDM_CHWDAT5R>>`[src]

`pub fn wdata(&self) -> WDATA_R`[src]

Bits 0:15 - Input channel y watchdog data

`impl R<u32, Reg<u32, _DFSDM_CHWDAT6R>>`[src]

`pub fn wdata(&self) -> WDATA_R`[src]

Bits 0:15 - Input channel y watchdog data

`impl R<u32, Reg<u32, _DFSDM_CHWDAT7R>>`[src]

`pub fn wdata(&self) -> WDATA_R`[src]

Bits 0:15 - Input channel y watchdog data

`impl R<u32, Reg<u32, _DFSDM_CHDATIN0R>>`[src]

`pub fn indat0(&self) -> INDAT0_R`[src]

Bits 0:15 - Input data for channel 0

`pub fn indat1(&self) -> INDAT1_R`[src]

Bits 16:31 - Input data for channel 1

`impl R<u32, Reg<u32, _DFSDM_CHDATIN1R>>`[src]

`pub fn indat0(&self) -> INDAT0_R`[src]

Bits 0:15 - Input data for channel 1

`pub fn indat1(&self) -> INDAT1_R`[src]

Bits 16:31 - Input data for channel 2

`impl R<u32, Reg<u32, _DFSDM_CHDATIN2R>>`[src]

`pub fn indat0(&self) -> INDAT0_R`[src]

Bits 0:15 - Input data for channel 2

`pub fn indat1(&self) -> INDAT1_R`[src]

Bits 16:31 - Input data for channel 3

`impl R<u32, Reg<u32, _DFSDM_CHDATIN3R>>`[src]

`pub fn indat0(&self) -> INDAT0_R`[src]

Bits 0:15 - Input data for channel 3

`pub fn indat1(&self) -> INDAT1_R`[src]

Bits 16:31 - Input data for channel 4

`impl R<u32, Reg<u32, _DFSDM_CHDATIN4R>>`[src]

`pub fn indat0(&self) -> INDAT0_R`[src]

Bits 0:15 - Input data for channel 4

`pub fn indat1(&self) -> INDAT1_R`[src]

Bits 16:31 - Input data for channel 5

`impl R<u32, Reg<u32, _DFSDM_CHDATIN5R>>`[src]

`pub fn indat0(&self) -> INDAT0_R`[src]

Bits 0:15 - Input data for channel 5

`pub fn indat1(&self) -> INDAT1_R`[src]

Bits 16:31 - Input data for channel 6

`impl R<u32, Reg<u32, _DFSDM_CHDATIN6R>>`[src]

`pub fn indat0(&self) -> INDAT0_R`[src]

Bits 0:15 - Input data for channel 6

`pub fn indat1(&self) -> INDAT1_R`[src]

Bits 16:31 - Input data for channel 7

`impl R<u32, Reg<u32, _DFSDM_CHDATIN7R>>`[src]

`pub fn indat0(&self) -> INDAT0_R`[src]

Bits 0:15 - Input data for channel 7

`pub fn indat1(&self) -> INDAT1_R`[src]

Bits 16:31 - Input data for channel 8

`impl R<u32, Reg<u32, _DFSDM0_CR1>>`[src]

`pub fn dfen(&self) -> DFEN_R`[src]

Bit 0 - DFSDM enable

`pub fn jswstart(&self) -> JSWSTART_R`[src]

Bit 1 - Start a conversion of the injected group of channels

`pub fn jsync(&self) -> JSYNC_R`[src]

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

`pub fn jscan(&self) -> JSCAN_R`[src]

Bit 4 - Scanning conversion mode for injected conversions

`pub fn jdmaen(&self) -> JDMAEN_R`[src]

Bit 5 - DMA channel enabled to read data for the injected channel group

`pub fn jextsel(&self) -> JEXTSEL_R`[src]

Bits 8:12 - Trigger signal selection for launching injected conversions

`pub fn jexten(&self) -> JEXTEN_R`[src]

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

`pub fn rswstart(&self) -> RSWSTART_R`[src]

Bit 17 - Software start of a conversion on the regular channel

`pub fn rcont(&self) -> RCONT_R`[src]

Bit 18 - Continuous mode selection for regular conversions

`pub fn rsync(&self) -> RSYNC_R`[src]

Bit 19 - Launch regular conversion synchronously with DFSDM0

`pub fn rdmaen(&self) -> RDMAEN_R`[src]

Bit 21 - DMA channel enabled to read data for the regular conversion

`pub fn rch(&self) -> RCH_R`[src]

Bits 24:26 - Regular channel selection

`pub fn fast(&self) -> FAST_R`[src]

Bit 29 - Fast conversion mode selection for regular conversions

`pub fn awfsel(&self) -> AWFSEL_R`[src]

Bit 30 - Analog watchdog fast mode select

`impl R<u32, Reg<u32, _DFSDM1_CR1>>`[src]

`pub fn dfen(&self) -> DFEN_R`[src]

Bit 0 - DFSDM enable

`pub fn jswstart(&self) -> JSWSTART_R`[src]

Bit 1 - Start a conversion of the injected group of channels

`pub fn jsync(&self) -> JSYNC_R`[src]

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

`pub fn jscan(&self) -> JSCAN_R`[src]

Bit 4 - Scanning conversion mode for injected conversions

`pub fn jdmaen(&self) -> JDMAEN_R`[src]

Bit 5 - DMA channel enabled to read data for the injected channel group

`pub fn jextsel(&self) -> JEXTSEL_R`[src]

Bits 8:12 - Trigger signal selection for launching injected conversions

`pub fn jexten(&self) -> JEXTEN_R`[src]

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

`pub fn rswstart(&self) -> RSWSTART_R`[src]

Bit 17 - Software start of a conversion on the regular channel

`pub fn rcont(&self) -> RCONT_R`[src]

Bit 18 - Continuous mode selection for regular conversions

`pub fn rsync(&self) -> RSYNC_R`[src]

Bit 19 - Launch regular conversion synchronously with DFSDM0

`pub fn rdmaen(&self) -> RDMAEN_R`[src]

Bit 21 - DMA channel enabled to read data for the regular conversion

`pub fn rch(&self) -> RCH_R`[src]

Bits 24:26 - Regular channel selection

`pub fn fast(&self) -> FAST_R`[src]

Bit 29 - Fast conversion mode selection for regular conversions

`pub fn awfsel(&self) -> AWFSEL_R`[src]

Bit 30 - Analog watchdog fast mode select

`impl R<u32, Reg<u32, _DFSDM2_CR1>>`[src]

`pub fn dfen(&self) -> DFEN_R`[src]

Bit 0 - DFSDM enable

`pub fn jswstart(&self) -> JSWSTART_R`[src]

Bit 1 - Start a conversion of the injected group of channels

`pub fn jsync(&self) -> JSYNC_R`[src]

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

`pub fn jscan(&self) -> JSCAN_R`[src]

Bit 4 - Scanning conversion mode for injected conversions

`pub fn jdmaen(&self) -> JDMAEN_R`[src]

Bit 5 - DMA channel enabled to read data for the injected channel group

`pub fn jextsel(&self) -> JEXTSEL_R`[src]

Bits 8:12 - Trigger signal selection for launching injected conversions

`pub fn jexten(&self) -> JEXTEN_R`[src]

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

`pub fn rswstart(&self) -> RSWSTART_R`[src]

Bit 17 - Software start of a conversion on the regular channel

`pub fn rcont(&self) -> RCONT_R`[src]

Bit 18 - Continuous mode selection for regular conversions

`pub fn rsync(&self) -> RSYNC_R`[src]

Bit 19 - Launch regular conversion synchronously with DFSDM0

`pub fn rdmaen(&self) -> RDMAEN_R`[src]

Bit 21 - DMA channel enabled to read data for the regular conversion

`pub fn rch(&self) -> RCH_R`[src]

Bits 24:26 - Regular channel selection

`pub fn fast(&self) -> FAST_R`[src]

Bit 29 - Fast conversion mode selection for regular conversions

`pub fn awfsel(&self) -> AWFSEL_R`[src]

Bit 30 - Analog watchdog fast mode select

`impl R<u32, Reg<u32, _DFSDM3_CR1>>`[src]

`pub fn dfen(&self) -> DFEN_R`[src]

Bit 0 - DFSDM enable

`pub fn jswstart(&self) -> JSWSTART_R`[src]

Bit 1 - Start a conversion of the injected group of channels

`pub fn jsync(&self) -> JSYNC_R`[src]

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

`pub fn jscan(&self) -> JSCAN_R`[src]

Bit 4 - Scanning conversion mode for injected conversions

`pub fn jdmaen(&self) -> JDMAEN_R`[src]

Bit 5 - DMA channel enabled to read data for the injected channel group

`pub fn jextsel(&self) -> JEXTSEL_R`[src]

Bits 8:12 - Trigger signal selection for launching injected conversions

`pub fn jexten(&self) -> JEXTEN_R`[src]

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

`pub fn rswstart(&self) -> RSWSTART_R`[src]

Bit 17 - Software start of a conversion on the regular channel

`pub fn rcont(&self) -> RCONT_R`[src]

Bit 18 - Continuous mode selection for regular conversions

`pub fn rsync(&self) -> RSYNC_R`[src]

Bit 19 - Launch regular conversion synchronously with DFSDM0

`pub fn rdmaen(&self) -> RDMAEN_R`[src]

Bit 21 - DMA channel enabled to read data for the regular conversion

`pub fn rch(&self) -> RCH_R`[src]

Bits 24:26 - Regular channel selection

`pub fn fast(&self) -> FAST_R`[src]

Bit 29 - Fast conversion mode selection for regular conversions

`pub fn awfsel(&self) -> AWFSEL_R`[src]

Bit 30 - Analog watchdog fast mode select

`impl R<u32, Reg<u32, _DFSDM0_CR2>>`[src]

`pub fn jeocie(&self) -> JEOCIE_R`[src]

Bit 0 - Injected end of conversion interrupt enable

`pub fn reocie(&self) -> REOCIE_R`[src]

Bit 1 - Regular end of conversion interrupt enable

`pub fn jovrie(&self) -> JOVRIE_R`[src]

Bit 2 - Injected data overrun interrupt enable

`pub fn rovrie(&self) -> ROVRIE_R`[src]

Bit 3 - Regular data overrun interrupt enable

`pub fn awdie(&self) -> AWDIE_R`[src]

Bit 4 - Analog watchdog interrupt enable

`pub fn scdie(&self) -> SCDIE_R`[src]

Bit 5 - Short-circuit detector interrupt enable

`pub fn ckabie(&self) -> CKABIE_R`[src]

Bit 6 - Clock absence interrupt enable

`pub fn exch(&self) -> EXCH_R`[src]

Bits 8:15 - Extremes detector channel selection

`pub fn awdch(&self) -> AWDCH_R`[src]

Bits 16:23 - Analog watchdog channel selection

`impl R<u32, Reg<u32, _DFSDM1_CR2>>`[src]

`pub fn jeocie(&self) -> JEOCIE_R`[src]

Bit 0 - Injected end of conversion interrupt enable

`pub fn reocie(&self) -> REOCIE_R`[src]

Bit 1 - Regular end of conversion interrupt enable

`pub fn jovrie(&self) -> JOVRIE_R`[src]

Bit 2 - Injected data overrun interrupt enable

`pub fn rovrie(&self) -> ROVRIE_R`[src]

Bit 3 - Regular data overrun interrupt enable

`pub fn awdie(&self) -> AWDIE_R`[src]

Bit 4 - Analog watchdog interrupt enable

`pub fn scdie(&self) -> SCDIE_R`[src]

Bit 5 - Short-circuit detector interrupt enable

`pub fn ckabie(&self) -> CKABIE_R`[src]

Bit 6 - Clock absence interrupt enable

`pub fn exch(&self) -> EXCH_R`[src]

Bits 8:15 - Extremes detector channel selection

`pub fn awdch(&self) -> AWDCH_R`[src]

Bits 16:23 - Analog watchdog channel selection

`impl R<u32, Reg<u32, _DFSDM2_CR2>>`[src]

`pub fn jeocie(&self) -> JEOCIE_R`[src]

Bit 0 - Injected end of conversion interrupt enable

`pub fn reocie(&self) -> REOCIE_R`[src]

Bit 1 - Regular end of conversion interrupt enable

`pub fn jovrie(&self) -> JOVRIE_R`[src]

Bit 2 - Injected data overrun interrupt enable

`pub fn rovrie(&self) -> ROVRIE_R`[src]

Bit 3 - Regular data overrun interrupt enable

`pub fn awdie(&self) -> AWDIE_R`[src]

Bit 4 - Analog watchdog interrupt enable

`pub fn scdie(&self) -> SCDIE_R`[src]

Bit 5 - Short-circuit detector interrupt enable

`pub fn ckabie(&self) -> CKABIE_R`[src]

Bit 6 - Clock absence interrupt enable

`pub fn exch(&self) -> EXCH_R`[src]

Bits 8:15 - Extremes detector channel selection

`pub fn awdch(&self) -> AWDCH_R`[src]

Bits 16:23 - Analog watchdog channel selection

`impl R<u32, Reg<u32, _DFSDM3_CR2>>`[src]

`pub fn jeocie(&self) -> JEOCIE_R`[src]

Bit 0 - Injected end of conversion interrupt enable

`pub fn reocie(&self) -> REOCIE_R`[src]

Bit 1 - Regular end of conversion interrupt enable

`pub fn jovrie(&self) -> JOVRIE_R`[src]

Bit 2 - Injected data overrun interrupt enable

`pub fn rovrie(&self) -> ROVRIE_R`[src]

Bit 3 - Regular data overrun interrupt enable

`pub fn awdie(&self) -> AWDIE_R`[src]

Bit 4 - Analog watchdog interrupt enable

`pub fn scdie(&self) -> SCDIE_R`[src]

Bit 5 - Short-circuit detector interrupt enable

`pub fn ckabie(&self) -> CKABIE_R`[src]

Bit 6 - Clock absence interrupt enable

`pub fn exch(&self) -> EXCH_R`[src]

Bits 8:15 - Extremes detector channel selection

`pub fn awdch(&self) -> AWDCH_R`[src]

Bits 16:23 - Analog watchdog channel selection

`impl R<u32, Reg<u32, _DFSDM0_ISR>>`[src]

`pub fn jeocf(&self) -> JEOCF_R`[src]

Bit 0 - End of injected conversion flag

`pub fn reocf(&self) -> REOCF_R`[src]

Bit 1 - End of regular conversion flag

`pub fn jovrf(&self) -> JOVRF_R`[src]

Bit 2 - Injected conversion overrun flag

`pub fn rovrf(&self) -> ROVRF_R`[src]

Bit 3 - Regular conversion overrun flag

`pub fn awdf(&self) -> AWDF_R`[src]

Bit 4 - Analog watchdog

`pub fn jcip(&self) -> JCIP_R`[src]

Bit 13 - Injected conversion in progress status

`pub fn rcip(&self) -> RCIP_R`[src]

Bit 14 - Regular conversion in progress status

`pub fn ckabf(&self) -> CKABF_R`[src]

Bits 16:23 - Clock absence flag

`pub fn scdf(&self) -> SCDF_R`[src]

Bits 24:31 - short-circuit detector flag

`impl R<u32, Reg<u32, _DFSDM1_ISR>>`[src]

`pub fn jeocf(&self) -> JEOCF_R`[src]

Bit 0 - End of injected conversion flag

`pub fn reocf(&self) -> REOCF_R`[src]

Bit 1 - End of regular conversion flag

`pub fn jovrf(&self) -> JOVRF_R`[src]

Bit 2 - Injected conversion overrun flag

`pub fn rovrf(&self) -> ROVRF_R`[src]

Bit 3 - Regular conversion overrun flag

`pub fn awdf(&self) -> AWDF_R`[src]

Bit 4 - Analog watchdog

`pub fn jcip(&self) -> JCIP_R`[src]

Bit 13 - Injected conversion in progress status

`pub fn rcip(&self) -> RCIP_R`[src]

Bit 14 - Regular conversion in progress status

`pub fn ckabf(&self) -> CKABF_R`[src]

Bits 16:23 - Clock absence flag

`pub fn scdf(&self) -> SCDF_R`[src]

Bits 24:31 - short-circuit detector flag

`impl R<u32, Reg<u32, _DFSDM2_ISR>>`[src]

`pub fn jeocf(&self) -> JEOCF_R`[src]

Bit 0 - End of injected conversion flag

`pub fn reocf(&self) -> REOCF_R`[src]

Bit 1 - End of regular conversion flag

`pub fn jovrf(&self) -> JOVRF_R`[src]

Bit 2 - Injected conversion overrun flag

`pub fn rovrf(&self) -> ROVRF_R`[src]

Bit 3 - Regular conversion overrun flag

`pub fn awdf(&self) -> AWDF_R`[src]

Bit 4 - Analog watchdog

`pub fn jcip(&self) -> JCIP_R`[src]

Bit 13 - Injected conversion in progress status

`pub fn rcip(&self) -> RCIP_R`[src]

Bit 14 - Regular conversion in progress status

`pub fn ckabf(&self) -> CKABF_R`[src]

Bits 16:23 - Clock absence flag

`pub fn scdf(&self) -> SCDF_R`[src]

Bits 24:31 - short-circuit detector flag

`impl R<u32, Reg<u32, _DFSDM3_ISR>>`[src]

`pub fn jeocf(&self) -> JEOCF_R`[src]

Bit 0 - End of injected conversion flag

`pub fn reocf(&self) -> REOCF_R`[src]

Bit 1 - End of regular conversion flag

`pub fn jovrf(&self) -> JOVRF_R`[src]

Bit 2 - Injected conversion overrun flag

`pub fn rovrf(&self) -> ROVRF_R`[src]

Bit 3 - Regular conversion overrun flag

`pub fn awdf(&self) -> AWDF_R`[src]

Bit 4 - Analog watchdog

`pub fn jcip(&self) -> JCIP_R`[src]

Bit 13 - Injected conversion in progress status

`pub fn rcip(&self) -> RCIP_R`[src]

Bit 14 - Regular conversion in progress status

`pub fn ckabf(&self) -> CKABF_R`[src]

Bits 16:23 - Clock absence flag

`pub fn scdf(&self) -> SCDF_R`[src]

Bits 24:31 - short-circuit detector flag

`impl R<u32, Reg<u32, _DFSDM0_ICR>>`[src]

`pub fn clrjovrf(&self) -> CLRJOVRF_R`[src]

Bit 2 - Clear the injected conversion overrun flag

`pub fn clrrovrf(&self) -> CLRROVRF_R`[src]

Bit 3 - Clear the regular conversion overrun flag

`pub fn clrckabf(&self) -> CLRCKABF_R`[src]

Bits 16:23 - Clear the clock absence flag

`pub fn clrscdf(&self) -> CLRSCDF_R`[src]

Bits 24:31 - Clear the short-circuit detector flag

`impl R<u32, Reg<u32, _DFSDM1_ICR>>`[src]

`pub fn clrjovrf(&self) -> CLRJOVRF_R`[src]

Bit 2 - Clear the injected conversion overrun flag

`pub fn clrrovrf(&self) -> CLRROVRF_R`[src]

Bit 3 - Clear the regular conversion overrun flag

`pub fn clrckabf(&self) -> CLRCKABF_R`[src]

Bits 16:23 - Clear the clock absence flag

`pub fn clrscdf(&self) -> CLRSCDF_R`[src]

Bits 24:31 - Clear the short-circuit detector flag

`impl R<u32, Reg<u32, _DFSDM2_ICR>>`[src]

`pub fn clrjovrf(&self) -> CLRJOVRF_R`[src]

Bit 2 - Clear the injected conversion overrun flag

`pub fn clrrovrf(&self) -> CLRROVRF_R`[src]

Bit 3 - Clear the regular conversion overrun flag

`pub fn clrckabf(&self) -> CLRCKABF_R`[src]

Bits 16:23 - Clear the clock absence flag

`pub fn clrscdf(&self) -> CLRSCDF_R`[src]

Bits 24:31 - Clear the short-circuit detector flag

`impl R<u32, Reg<u32, _DFSDM3_ICR>>`[src]

`pub fn clrjovrf(&self) -> CLRJOVRF_R`[src]

Bit 2 - Clear the injected conversion overrun flag

`pub fn clrrovrf(&self) -> CLRROVRF_R`[src]

Bit 3 - Clear the regular conversion overrun flag

`pub fn clrckabf(&self) -> CLRCKABF_R`[src]

Bits 16:23 - Clear the clock absence flag

`pub fn clrscdf(&self) -> CLRSCDF_R`[src]

Bits 24:31 - Clear the short-circuit detector flag

`impl R<u32, Reg<u32, _DFSDM0_JCHGR>>`[src]

`pub fn jchg(&self) -> JCHG_R`[src]

Bits 0:7 - Injected channel group selection

`impl R<u32, Reg<u32, _DFSDM1_JCHGR>>`[src]

`pub fn jchg(&self) -> JCHG_R`[src]

Bits 0:7 - Injected channel group selection

`impl R<u32, Reg<u32, _DFSDM2_JCHGR>>`[src]

`pub fn jchg(&self) -> JCHG_R`[src]

Bits 0:7 - Injected channel group selection

`impl R<u32, Reg<u32, _DFSDM3_JCHGR>>`[src]

`pub fn jchg(&self) -> JCHG_R`[src]

Bits 0:7 - Injected channel group selection

`impl R<u32, Reg<u32, _DFSDM0_FCR>>`[src]

`pub fn iosr(&self) -> IOSR_R`[src]

Bits 0:7 - Integrator oversampling ratio (averaging length)

`pub fn fosr(&self) -> FOSR_R`[src]

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

`pub fn ford(&self) -> FORD_R`[src]

Bits 29:31 - Sinc filter order

`impl R<u32, Reg<u32, _DFSDM1_FCR>>`[src]

`pub fn iosr(&self) -> IOSR_R`[src]

Bits 0:7 - Integrator oversampling ratio (averaging length)

`pub fn fosr(&self) -> FOSR_R`[src]

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

`pub fn ford(&self) -> FORD_R`[src]

Bits 29:31 - Sinc filter order

`impl R<u32, Reg<u32, _DFSDM2_FCR>>`[src]

`pub fn iosr(&self) -> IOSR_R`[src]

Bits 0:7 - Integrator oversampling ratio (averaging length)

`pub fn fosr(&self) -> FOSR_R`[src]

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

`pub fn ford(&self) -> FORD_R`[src]

Bits 29:31 - Sinc filter order

`impl R<u32, Reg<u32, _DFSDM3_FCR>>`[src]

`pub fn iosr(&self) -> IOSR_R`[src]

Bits 0:7 - Integrator oversampling ratio (averaging length)

`pub fn fosr(&self) -> FOSR_R`[src]

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

`pub fn ford(&self) -> FORD_R`[src]

Bits 29:31 - Sinc filter order

`impl R<u32, Reg<u32, _DFSDM0_JDATAR>>`[src]

`pub fn jdatach(&self) -> JDATACH_R`[src]

Bits 0:2 - Injected channel most recently converted

`pub fn jdata(&self) -> JDATA_R`[src]

Bits 8:31 - Injected group conversion data

`impl R<u32, Reg<u32, _DFSDM1_JDATAR>>`[src]

`pub fn jdatach(&self) -> JDATACH_R`[src]

Bits 0:2 - Injected channel most recently converted

`pub fn jdata(&self) -> JDATA_R`[src]

Bits 8:31 - Injected group conversion data

`impl R<u32, Reg<u32, _DFSDM2_JDATAR>>`[src]

`pub fn jdatach(&self) -> JDATACH_R`[src]

Bits 0:2 - Injected channel most recently converted

`pub fn jdata(&self) -> JDATA_R`[src]

Bits 8:31 - Injected group conversion data

`impl R<u32, Reg<u32, _DFSDM3_JDATAR>>`[src]

`pub fn jdatach(&self) -> JDATACH_R`[src]

Bits 0:2 - Injected channel most recently converted

`pub fn jdata(&self) -> JDATA_R`[src]

Bits 8:31 - Injected group conversion data

`impl R<u32, Reg<u32, _DFSDM0_RDATAR>>`[src]

`pub fn rdatach(&self) -> RDATACH_R`[src]

Bits 0:2 - Regular channel most recently converted

`pub fn rpend(&self) -> RPEND_R`[src]

Bit 4 - Regular channel pending data

`pub fn rdata(&self) -> RDATA_R`[src]

Bits 8:31 - Regular channel conversion data

`impl R<u32, Reg<u32, _DFSDM1_RDATAR>>`[src]

`pub fn rdatach(&self) -> RDATACH_R`[src]

Bits 0:2 - Regular channel most recently converted

`pub fn rpend(&self) -> RPEND_R`[src]

Bit 4 - Regular channel pending data

`pub fn rdata(&self) -> RDATA_R`[src]

Bits 8:31 - Regular channel conversion data

`impl R<u32, Reg<u32, _DFSDM2_RDATAR>>`[src]

`pub fn rdatach(&self) -> RDATACH_R`[src]

Bits 0:2 - Regular channel most recently converted

`pub fn rpend(&self) -> RPEND_R`[src]

Bit 4 - Regular channel pending data

`pub fn rdata(&self) -> RDATA_R`[src]

Bits 8:31 - Regular channel conversion data

`impl R<u32, Reg<u32, _DFSDM3_RDATAR>>`[src]

`pub fn rdatach(&self) -> RDATACH_R`[src]

Bits 0:2 - Regular channel most recently converted

`pub fn rpend(&self) -> RPEND_R`[src]

Bit 4 - Regular channel pending data

`pub fn rdata(&self) -> RDATA_R`[src]

Bits 8:31 - Regular channel conversion data

`impl R<u32, Reg<u32, _DFSDM0_AWHTR>>`[src]

`pub fn bkawh(&self) -> BKAWH_R`[src]

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

`pub fn awht(&self) -> AWHT_R`[src]

Bits 8:31 - Analog watchdog high threshold

`impl R<u32, Reg<u32, _DFSDM1_AWHTR>>`[src]

`pub fn bkawh(&self) -> BKAWH_R`[src]

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

`pub fn awht(&self) -> AWHT_R`[src]

Bits 8:31 - Analog watchdog high threshold

`impl R<u32, Reg<u32, _DFSDM2_AWHTR>>`[src]

`pub fn bkawh(&self) -> BKAWH_R`[src]

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

`pub fn awht(&self) -> AWHT_R`[src]

Bits 8:31 - Analog watchdog high threshold

`impl R<u32, Reg<u32, _DFSDM3_AWHTR>>`[src]

`pub fn bkawh(&self) -> BKAWH_R`[src]

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

`pub fn awht(&self) -> AWHT_R`[src]

Bits 8:31 - Analog watchdog high threshold

`impl R<u32, Reg<u32, _DFSDM0_AWLTR>>`[src]

`pub fn bkawl(&self) -> BKAWL_R`[src]

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

`pub fn awlt(&self) -> AWLT_R`[src]

Bits 8:31 - Analog watchdog low threshold

`impl R<u32, Reg<u32, _DFSDM1_AWLTR>>`[src]

`pub fn bkawl(&self) -> BKAWL_R`[src]

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

`pub fn awlt(&self) -> AWLT_R`[src]

Bits 8:31 - Analog watchdog low threshold

`impl R<u32, Reg<u32, _DFSDM2_AWLTR>>`[src]

`pub fn bkawl(&self) -> BKAWL_R`[src]

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

`pub fn awlt(&self) -> AWLT_R`[src]

Bits 8:31 - Analog watchdog low threshold

`impl R<u32, Reg<u32, _DFSDM3_AWLTR>>`[src]

`pub fn bkawl(&self) -> BKAWL_R`[src]

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

`pub fn awlt(&self) -> AWLT_R`[src]

Bits 8:31 - Analog watchdog low threshold

`impl R<u32, Reg<u32, _DFSDM0_AWSR>>`[src]

`pub fn awltf(&self) -> AWLTF_R`[src]

Bits 0:7 - Analog watchdog low threshold flag

`pub fn awhtf(&self) -> AWHTF_R`[src]

Bits 8:15 - Analog watchdog high threshold flag

`impl R<u32, Reg<u32, _DFSDM1_AWSR>>`[src]

`pub fn awltf(&self) -> AWLTF_R`[src]

Bits 0:7 - Analog watchdog low threshold flag

`pub fn awhtf(&self) -> AWHTF_R`[src]

Bits 8:15 - Analog watchdog high threshold flag

`impl R<u32, Reg<u32, _DFSDM2_AWSR>>`[src]

`pub fn awltf(&self) -> AWLTF_R`[src]

Bits 0:7 - Analog watchdog low threshold flag

`pub fn awhtf(&self) -> AWHTF_R`[src]

Bits 8:15 - Analog watchdog high threshold flag

`impl R<u32, Reg<u32, _DFSDM3_AWSR>>`[src]

`pub fn awltf(&self) -> AWLTF_R`[src]

Bits 0:7 - Analog watchdog low threshold flag

`pub fn awhtf(&self) -> AWHTF_R`[src]

Bits 8:15 - Analog watchdog high threshold flag

`impl R<u32, Reg<u32, _DFSDM0_AWCFR>>`[src]

`pub fn clrawltf(&self) -> CLRAWLTF_R`[src]

Bits 0:7 - Clear the analog watchdog low threshold flag

`pub fn clrawhtf(&self) -> CLRAWHTF_R`[src]

Bits 8:15 - Clear the analog watchdog high threshold flag

`impl R<u32, Reg<u32, _DFSDM1_AWCFR>>`[src]

`pub fn clrawltf(&self) -> CLRAWLTF_R`[src]

Bits 0:7 - Clear the analog watchdog low threshold flag

`pub fn clrawhtf(&self) -> CLRAWHTF_R`[src]

Bits 8:15 - Clear the analog watchdog high threshold flag

`impl R<u32, Reg<u32, _DFSDM2_AWCFR>>`[src]

`pub fn clrawltf(&self) -> CLRAWLTF_R`[src]

Bits 0:7 - Clear the analog watchdog low threshold flag

`pub fn clrawhtf(&self) -> CLRAWHTF_R`[src]

Bits 8:15 - Clear the analog watchdog high threshold flag

`impl R<u32, Reg<u32, _DFSDM3_AWCFR>>`[src]

`pub fn clrawltf(&self) -> CLRAWLTF_R`[src]

Bits 0:7 - Clear the analog watchdog low threshold flag

`pub fn clrawhtf(&self) -> CLRAWHTF_R`[src]

Bits 8:15 - Clear the analog watchdog high threshold flag

`impl R<u32, Reg<u32, _DFSDM0_EXMAX>>`[src]

`pub fn exmaxch(&self) -> EXMAXCH_R`[src]

Bits 0:2 - Extremes detector maximum data channel

`pub fn exmax(&self) -> EXMAX_R`[src]

Bits 8:31 - Extremes detector maximum value

`impl R<u32, Reg<u32, _DFSDM1_EXMAX>>`[src]

`pub fn exmaxch(&self) -> EXMAXCH_R`[src]

Bits 0:2 - Extremes detector maximum data channel

`pub fn exmax(&self) -> EXMAX_R`[src]

Bits 8:31 - Extremes detector maximum value

`impl R<u32, Reg<u32, _DFSDM2_EXMAX>>`[src]

`pub fn exmaxch(&self) -> EXMAXCH_R`[src]

Bits 0:2 - Extremes detector maximum data channel

`pub fn exmax(&self) -> EXMAX_R`[src]

Bits 8:31 - Extremes detector maximum value

`impl R<u32, Reg<u32, _DFSDM3_EXMAX>>`[src]

`pub fn exmaxch(&self) -> EXMAXCH_R`[src]

Bits 0:2 - Extremes detector maximum data channel

`pub fn exmax(&self) -> EXMAX_R`[src]

Bits 8:31 - Extremes detector maximum value

`impl R<u32, Reg<u32, _DFSDM0_EXMIN>>`[src]

`pub fn exminch(&self) -> EXMINCH_R`[src]

Bits 0:2 - Extremes detector minimum data channel

`pub fn exmin(&self) -> EXMIN_R`[src]

Bits 8:31 - Extremes detector minimum value

`impl R<u32, Reg<u32, _DFSDM1_EXMIN>>`[src]

`pub fn exminch(&self) -> EXMINCH_R`[src]

Bits 0:2 - Extremes detector minimum data channel

`pub fn exmin(&self) -> EXMIN_R`[src]

Bits 8:31 - Extremes detector minimum value

`impl R<u32, Reg<u32, _DFSDM2_EXMIN>>`[src]

`pub fn exminch(&self) -> EXMINCH_R`[src]

Bits 0:2 - Extremes detector minimum data channel

`pub fn exmin(&self) -> EXMIN_R`[src]

Bits 8:31 - Extremes detector minimum value

`impl R<u32, Reg<u32, _DFSDM3_EXMIN>>`[src]

`pub fn exminch(&self) -> EXMINCH_R`[src]

Bits 0:2 - Extremes detector minimum data channel

`pub fn exmin(&self) -> EXMIN_R`[src]

Bits 8:31 - Extremes detector minimum value

`impl R<u32, Reg<u32, _DFSDM0_CNVTIMR>>`[src]

`pub fn cnvcnt(&self) -> CNVCNT_R`[src]

Bits 4:31 - 28-bit timer counting conversion time

`impl R<u32, Reg<u32, _DFSDM1_CNVTIMR>>`[src]

`pub fn cnvcnt(&self) -> CNVCNT_R`[src]

Bits 4:31 - 28-bit timer counting conversion time

`impl R<u32, Reg<u32, _DFSDM2_CNVTIMR>>`[src]

`pub fn cnvcnt(&self) -> CNVCNT_R`[src]

Bits 4:31 - 28-bit timer counting conversion time

`impl R<u32, Reg<u32, _DFSDM3_CNVTIMR>>`[src]

`pub fn cnvcnt(&self) -> CNVCNT_R`[src]

Bits 4:31 - 28-bit timer counting conversion time

`impl R<u32, Reg<u32, _JPEG_CONFR1>>`[src]

`pub fn nf(&self) -> NF_R`[src]

Bits 0:1 - Number of color components

`pub fn de(&self) -> DE_R`[src]

Bit 3 - Decoding Enable

`pub fn colorspace(&self) -> COLORSPACE_R`[src]

Bits 4:5 - Color Space

`pub fn ns(&self) -> NS_R`[src]

Bits 6:7 - Number of components for Scan

`pub fn hdr(&self) -> HDR_R`[src]

Bit 8 - Header Processing

`pub fn ysize(&self) -> YSIZE_R`[src]

Bits 16:31 - Y Size

`impl R<u32, Reg<u32, _JPEG_CONFR2>>`[src]

`pub fn nmcu(&self) -> NMCU_R`[src]

Bits 0:25 - Number of MCU

Bit 4 - Output FIFO Not Empty Interrupt Enable

`pub fn eocie(&self) -> EOCIE_R`[src]

Bit 5 - End of Conversion Interrupt Enable

`pub fn hpdie(&self) -> HPDIE_R`[src]

Bit 6 - Header Parsing Done Interrupt Enable

`pub fn idmaen(&self) -> IDMAEN_R`[src]

Bit 11 - Input DMA Enable

`pub fn odmaen(&self) -> ODMAEN_R`[src]

Bit 12 - Output DMA Enable

`pub fn iff(&self) -> IFF_R`[src]

Bit 13 - Input FIFO Flush

`pub fn off(&self) -> OFF_R`[src]

Bit 14 - Output FIFO Flush

`impl R<u32, Reg<u32, _JPEG_SR>>`[src]

`pub fn iftf(&self) -> IFTF_R`[src]

Bit 1 - Input FIFO Threshold Flag

`pub fn ifnff(&self) -> IFNFF_R`[src]

Bit 2 - Input FIFO Not Full Flag

`pub fn oftf(&self) -> OFTF_R`[src]

Bit 3 - Output FIFO Threshold Flag

`pub fn ofnef(&self) -> OFNEF_R`[src]

Bit 4 - Output FIFO Not Empty Flag

`pub fn eocf(&self) -> EOCF_R`[src]

Bit 5 - End of Conversion Flag

`pub fn hpdf(&self) -> HPDF_R`[src]

`pub fn is_almost_full(&self) -> bool`[src]

Checks if the value of the field is ALMOSTFULL

`impl R<u32, Reg<u32, _MMCCR>>`[src]

`pub fn cr(&self) -> CR_R`[src]

Bit 0 - Counter reset

`pub fn csr(&self) -> CSR_R`[src]

Bit 1 - Counter stop rollover

`pub fn ror(&self) -> ROR_R`[src]

`impl R<u32, Reg<u32, _MMCTIMR>>`[src]

`pub fn tgfscm(&self) -> TGFSCM_R`[src]

Bit 14 - Transmitted good frames single collision mask

`pub fn tgfmscm(&self) -> TGFMSCM_R`[src]

Bit 15 - Transmitted good frames more than single collision mask

`pub fn tgfm(&self) -> TGFM_R`[src]

Bit 16 - Transmitted good frames mask

`impl R<u32, Reg<u32, _MMCTGFSCCR>>`[src]

`pub fn tgfscc(&self) -> TGFSCC_R`[src]

Bits 0:31 - Transmitted good frames single collision counter

`impl R<u32, Reg<u32, _MMCTGFMSCCR>>`[src]

`pub fn tgfmscc(&self) -> TGFMSCC_R`[src]

Bits 0:31 - TGFMSCC

`impl R<u32, Reg<u32, _MMCTGFCR>>`[src]

`pub fn tgfc(&self) -> TGFC_R`[src]

Bits 0:31 - HTL

`impl R<u32, Reg<u32, _MMCRFCECR>>`[src]

`pub fn rfcfc(&self) -> RFCFC_R`[src]

Bits 0:31 - RFCFC

`impl R<u32, Reg<u32, _MMCRFAECR>>`[src]

`pub fn rfaec(&self) -> RFAEC_R`[src]

Bits 0:31 - RFAEC

`impl R<u32, Reg<u32, _MMCRGUFCR>>`[src]

`pub fn rgufc(&self) -> RGUFC_R`[src]

Bits 0:31 - RGUFC

`impl R<u32, Reg<u32, _PTPTSCR>>`[src]

`pub fn tse(&self) -> TSE_R`[src]

Bit 0 - TSE

`pub fn tsfcu(&self) -> TSFCU_R`[src]

Bit 1 - TSFCU

`pub fn tsptppsv2e(&self) -> TSPTPPSV2E_R`[src]

Bit 10 - TSPTPPSV2E

`pub fn tssptpoefe(&self) -> TSSPTPOEFE_R`[src]

Bit 11 - TSSPTPOEFE

`pub fn tssipv6fe(&self) -> TSSIPV6FE_R`[src]

Bit 12 - TSSIPV6FE

`pub fn tssipv4fe(&self) -> TSSIPV4FE_R`[src]

Bit 13 - TSSIPV4FE

`pub fn tsseme(&self) -> TSSEME_R`[src]

Bit 14 - TSSEME

`pub fn tssmrme(&self) -> TSSMRME_R`[src]

Bit 15 - TSSMRME

`pub fn tscnt(&self) -> TSCNT_R`[src]

Bits 16:17 - TSCNT

`pub fn tspffmae(&self) -> TSPFFMAE_R`[src]

Bit 18 - TSPFFMAE

`pub fn tssti(&self) -> TSSTI_R`[src]

Bit 2 - TSSTI

`pub fn tsstu(&self) -> TSSTU_R`[src]

Bit 3 - TSSTU

`pub fn tsite(&self) -> TSITE_R`[src]

Bit 4 - TSITE

`pub fn ttsaru(&self) -> TTSARU_R`[src]

Bit 5 - TTSARU

`pub fn tssarfe(&self) -> TSSARFE_R`[src]

Bit 8 - TSSARFE

`pub fn tsssr(&self) -> TSSSR_R`[src]

Bit 9 - TSSSR

`impl R<u32, Reg<u32, _PTPSSIR>>`[src]

`pub fn stssi(&self) -> STSSI_R`[src]

Bits 0:7 - STSSI

`impl R<u32, Reg<u32, _PTPTSHR>>`[src]

`pub fn sts(&self) -> STS_R`[src]

Bits 0:31 - STS

`impl R<u32, Reg<u32, _PTPTSLR>>`[src]

`pub fn stss(&self) -> STSS_R`[src]

Bits 0:30 - STSS

`pub fn stpns(&self) -> STPNS_R`[src]

Bit 31 - STPNS

`impl R<u32, Reg<u32, _PTPTSHUR>>`[src]

`pub fn tsus(&self) -> TSUS_R`[src]

Bits 0:31 - TSUS

`impl R<u32, Reg<u32, _PTPTSLUR>>`[src]

`pub fn tsuss(&self) -> TSUSS_R`[src]

Bits 0:30 - TSUSS

`pub fn tsupns(&self) -> TSUPNS_R`[src]

Bit 31 - TSUPNS

`impl R<u32, Reg<u32, _PTPTSAR>>`[src]

`pub fn tsa(&self) -> TSA_R`[src]

Bits 0:31 - TSA

`impl R<u32, Reg<u32, _PTPTTHR>>`[src]

`pub fn ttsh(&self) -> TTSH_R`[src]

Bits 0:31 - 0

`impl R<u32, Reg<u32, _PTPTTLR>>`[src]

`pub fn ttsl(&self) -> TTSL_R`[src]

Bits 0:31 - TTSL

`impl R<u32, Reg<u32, _PTPTSSR>>`[src]

`pub fn tsso(&self) -> TSSO_R`[src]

Bit 0 - TSSO

`pub fn tsttr(&self) -> TSTTR_R`[src]

Bit 1 - TSTTR

`impl R<u32, Reg<u32, _PTPPPSCR>>`[src]

`pub fn tsso(&self) -> TSSO_R`[src]

Bit 0 - TSSO

`pub fn tsttr(&self) -> TSTTR_R`[src]

Bit 1 - TSTTR

Get enumerated values variant

`pub fn is_pbl1(&self) -> bool`[src]

Checks if the value of the field is PBL1

`pub fn is_pbl2(&self) -> bool`[src]

Checks if the value of the field is PBL2

`pub fn is_pbl4(&self) -> bool`[src]

Checks if the value of the field is PBL4

`pub fn is_pbl8(&self) -> bool`[src]

Checks if the value of the field is PBL8

`pub fn is_pbl16(&self) -> bool`[src]

Checks if the value of the field is PBL16

`pub fn is_pbl32(&self) -> bool`[src]

Checks if the value of the field is PBL32

`impl R<u8, PM_A>`[src]

`pub fn variant(&self) -> PM_A`[src]

Get enumerated values variant

`pub fn is_one_to_one(&self) -> bool`[src]

Checks if the value of the field is ONETOONE

`pub fn is_two_to_one(&self) -> bool`[src]

Checks if the value of the field is TWOTOONE

`pub fn is_three_to_one(&self) -> bool`[src]

Checks if the value of the field is THREETOONE

`pub fn is_four_to_one(&self) -> bool`[src]

Checks if the value of the field is FOURTOONE

`impl R<bool, FB_A>`[src]

`pub fn variant(&self) -> FB_A`[src]

Get enumerated values variant

`pub fn is_variable(&self) -> bool`[src]

Checks if the value of the field is VARIABLE

`pub fn is_fixed(&self) -> bool`[src]

Checks if the value of the field is FIXED

`impl R<u8, RDP_A>`[src]

`pub fn variant(&self) -> Variant<u8, RDP_A>`[src]

Get enumerated values variant

`pub fn is_rdp1(&self) -> bool`[src]

Checks if the value of the field is RDP1

`pub fn is_rdp2(&self) -> bool`[src]

Checks if the value of the field is RDP2

`pub fn is_rdp4(&self) -> bool`[src]

`pub fn edfe(&self) -> EDFE_R`[src]

Bit 7 - Enhanced descriptor format enable

`pub fn pbl(&self) -> PBL_R`[src]

Bits 8:13 - Programmable burst length

`pub fn pm(&self) -> PM_R`[src]

Bits 14:15 - Rx-Tx priority ratio

`pub fn fb(&self) -> FB_R`[src]

Bit 16 - Fixed burst

`pub fn rdp(&self) -> RDP_R`[src]

Bits 17:22 - Rx DMA PBL

`pub fn usp(&self) -> USP_R`[src]

Bit 23 - Use separate PBL

`pub fn fpm(&self) -> FPM_R`[src]

Bit 24 - 4xPBL mode

`pub fn aab(&self) -> AAB_R`[src]

Bit 25 - Address-aligned beats

`pub fn mb(&self) -> MB_R`[src]

Bit 26 - Mixed burst

`impl R<u32, TPD_A>`[src]

`pub fn variant(&self) -> Variant<u32, TPD_A>`[src]

Get enumerated values variant

`pub fn is_poll(&self) -> bool`[src]

Checks if the value of the field is POLL

`impl R<u32, Reg<u32, _DMATPDR>>`[src]

`pub fn tpd(&self) -> TPD_R`[src]

Bits 0:31 - Transmit poll demand

`impl R<u32, RPD_A>`[src]

`pub fn variant(&self) -> Variant<u32, RPD_A>`[src]

Get enumerated values variant

`pub fn is_poll(&self) -> bool`[src]

Checks if the value of the field is POLL

`impl R<u32, Reg<u32, _DMARPDR>>`[src]

`pub fn rpd(&self) -> RPD_R`[src]

Bits 0:31 - Receive poll demand

`impl R<u32, Reg<u32, _DMARDLAR>>`[src]

`pub fn srl(&self) -> SRL_R`[src]

Bits 0:31 - Start of receive list

`impl R<u32, Reg<u32, _DMATDLAR>>`[src]

`pub fn stl(&self) -> STL_R`[src]

Bits 0:31 - Start of transmit list

`impl R<u8, RPS_A>`[src]

`pub fn variant(&self) -> Variant<u8, RPS_A>`[src]

Get enumerated values variant

`pub fn is_stopped(&self) -> bool`[src]

Checks if the value of the field is STOPPED

`pub fn is_running_fetching(&self) -> bool`[src]

Checks if the value of the field is RUNNINGFETCHING

`pub fn is_running_waiting(&self) -> bool`[src]

Checks if the value of the field is RUNNINGWAITING

`pub fn is_suspended(&self) -> bool`[src]

Checks if the value of the field is SUSPENDED

`pub fn is_running_writing(&self) -> bool`[src]

Checks if the value of the field is RUNNINGWRITING

`impl R<u8, TPS_A>`[src]

`pub fn variant(&self) -> Variant<u8, TPS_A>`[src]

Get enumerated values variant

`pub fn is_stopped(&self) -> bool`[src]

Checks if the value of the field is STOPPED

`pub fn is_running_fetching(&self) -> bool`[src]

Checks if the value of the field is RUNNINGFETCHING

`pub fn is_running_waiting(&self) -> bool`[src]

Checks if the value of the field is RUNNINGWAITING

`pub fn is_running_reading(&self) -> bool`[src]

Checks if the value of the field is RUNNINGREADING

`pub fn is_suspended(&self) -> bool`[src]

Checks if the value of the field is SUSPENDED

`pub fn is_running(&self) -> bool`[src]

Checks if the value of the field is RUNNING

`impl R<u32, Reg<u32, _DMASR>>`[src]

`pub fn ts(&self) -> TS_R`[src]

Bit 0 - Transmit status

`pub fn tpss(&self) -> TPSS_R`[src]

Bit 1 - Transmit process stopped status

`pub fn tbus(&self) -> TBUS_R`[src]

Bit 2 - Transmit buffer unavailable status

`pub fn tjts(&self) -> TJTS_R`[src]

Bit 3 - Transmit jabber timeout status

`pub fn ros(&self) -> ROS_R`[src]

Bit 4 - Receive overflow status

`pub fn tus(&self) -> TUS_R`[src]

Bit 5 - Transmit underflow status

`pub fn rs(&self) -> RS_R`[src]

Bit 6 - Receive status

`pub fn rbus(&self) -> RBUS_R`[src]

Bit 7 - Receive buffer unavailable status

`pub fn rpss(&self) -> RPSS_R`[src]

Bit 8 - Receive process stopped status

`pub fn pwts(&self) -> PWTS_R`[src]

Bit 9 - PWTS

`pub fn ets(&self) -> ETS_R`[src]

Bit 10 - Early transmit status

`pub fn fbes(&self) -> FBES_R`[src]

Bit 13 - Fatal bus error status

`pub fn ers(&self) -> ERS_R`[src]

Bit 14 - Early receive status

`pub fn ais(&self) -> AIS_R`[src]

Bit 15 - Abnormal interrupt summary

`pub fn nis(&self) -> NIS_R`[src]

Bit 16 - Normal interrupt summary

`pub fn rps(&self) -> RPS_R`[src]

Bits 17:19 - Receive process state

`pub fn tps(&self) -> TPS_R`[src]

Bits 20:22 - Transmit process state

`pub fn ebs(&self) -> EBS_R`[src]

Bits 23:25 - Error bits status

`pub fn mmcs(&self) -> MMCS_R`[src]

Bit 27 - MMC status

`pub fn pmts(&self) -> PMTS_R`[src]

Bit 28 - PMT status

`pub fn tsts(&self) -> TSTS_R`[src]

Bit 29 - Time stamp trigger status

`impl R<bool, SR_A>`[src]

`pub fn variant(&self) -> SR_A`[src]

Get enumerated values variant

`pub fn is_stopped(&self) -> bool`[src]

Checks if the value of the field is STOPPED

`pub fn is_started(&self) -> bool`[src]

Checks if the value of the field is STARTED

`impl R<u8, RTC_A>`[src]

`pub fn variant(&self) -> RTC_A`[src]

Get enumerated values variant

`pub fn is_rtc64(&self) -> bool`[src]

Checks if the value of the field is RTC64

`pub fn is_rtc32(&self) -> bool`[src]

Checks if the value of the field is RTC32

`pub fn is_ttc64(&self) -> bool`[src]

Checks if the value of the field is TTC64

`pub fn is_ttc128(&self) -> bool`[src]

Checks if the value of the field is TTC128

`pub fn is_ttc192(&self) -> bool`[src]

Checks if the value of the field is TTC192

`pub fn is_ttc256(&self) -> bool`[src]

Checks if the value of the field is TTC256

`pub fn is_ttc40(&self) -> bool`[src]

Checks if the value of the field is TTC40

`pub fn is_ttc32(&self) -> bool`[src]

Checks if the value of the field is TTC32

`pub fn is_ttc24(&self) -> bool`[src]

Checks if the value of the field is TTC24

`pub fn is_ttc16(&self) -> bool`[src]

Checks if the value of the field is TTC16

Bit 1 - Start/stop receive

`pub fn osf(&self) -> OSF_R`[src]

Bit 2 - Operate on second frame

`pub fn rtc(&self) -> RTC_R`[src]

Bits 3:4 - Receive threshold control

`pub fn fugf(&self) -> FUGF_R`[src]

Bit 6 - Forward undersized good frames

`pub fn fef(&self) -> FEF_R`[src]

Bit 7 - Forward error frames

`pub fn st(&self) -> ST_R`[src]

Bit 13 - Start/stop transmission

`pub fn ttc(&self) -> TTC_R`[src]

Bits 14:16 - Transmit threshold control

`pub fn ftf(&self) -> FTF_R`[src]

Bit 20 - Flush transmit FIFO

`pub fn tsf(&self) -> TSF_R`[src]

Bit 21 - Transmit store and forward

`pub fn dfrf(&self) -> DFRF_R`[src]

Bit 24 - Disable flushing of received frames

`pub fn rsf(&self) -> RSF_R`[src]

Bit 25 - Receive store and forward

`pub fn dtcefd(&self) -> DTCEFD_R`[src]

Bit 26 - Dropping of TCP/IP checksum error frames disable

`impl R<u32, Reg<u32, _DMAIER>>`[src]

`pub fn tie(&self) -> TIE_R`[src]

Bit 0 - Transmit interrupt enable

`pub fn tpsie(&self) -> TPSIE_R`[src]

Bit 1 - Transmit process stopped interrupt enable

`pub fn tbuie(&self) -> TBUIE_R`[src]

Bit 2 - Transmit buffer unavailable interrupt enable

`pub fn tjtie(&self) -> TJTIE_R`[src]

Bit 3 - Transmit jabber timeout interrupt enable

`pub fn roie(&self) -> ROIE_R`[src]

Bit 4 - Receive overflow interrupt enable

`pub fn tuie(&self) -> TUIE_R`[src]

Bit 5 - Transmit underflow interrupt enable

`pub fn rie(&self) -> RIE_R`[src]

Bit 6 - Receive interrupt enable

`pub fn rbuie(&self) -> RBUIE_R`[src]

Bit 7 - Receive buffer unavailable interrupt enable

`pub fn rpsie(&self) -> RPSIE_R`[src]

Bit 8 - Receive process stopped interrupt enable

`pub fn rwtie(&self) -> RWTIE_R`[src]

Bit 9 - Receive watchdog timeout interrupt enable

`pub fn etie(&self) -> ETIE_R`[src]

Bit 10 - Early transmit interrupt enable

`pub fn fbeie(&self) -> FBEIE_R`[src]

Bit 13 - Fatal bus error interrupt enable

`pub fn erie(&self) -> ERIE_R`[src]

Bit 14 - Early receive interrupt enable

`pub fn aise(&self) -> AISE_R`[src]

Bit 15 - Abnormal interrupt summary enable

`pub fn nise(&self) -> NISE_R`[src]

Bit 16 - Normal interrupt summary enable

`impl R<u32, Reg<u32, _DMAMFBOCR>>`[src]

`pub fn mfc(&self) -> MFC_R`[src]

Bits 0:15 - Missed frames by the controller

`pub fn omfc(&self) -> OMFC_R`[src]

Bit 16 - Overflow bit for missed frame counter

`pub fn mfa(&self) -> MFA_R`[src]

Bits 17:27 - Missed frames by the application

`pub fn ofoc(&self) -> OFOC_R`[src]

Bit 28 - Overflow bit for FIFO overflow counter

`impl R<u32, Reg<u32, _DMARSWTR>>`[src]

`pub fn rswtc(&self) -> RSWTC_R`[src]

Bits 0:7 - Receive status watchdog timer count

`impl R<u32, Reg<u32, _DMACHTDR>>`[src]

`pub fn htdap(&self) -> HTDAP_R`[src]

Bits 0:31 - Host transmit descriptor address pointer

`impl R<u32, Reg<u32, _DMACHRDR>>`[src]

`pub fn hrdap(&self) -> HRDAP_R`[src]

Bits 0:31 - Host receive descriptor address pointer

`impl R<u32, Reg<u32, _DMACHTBAR>>`[src]

`pub fn htbap(&self) -> HTBAP_R`[src]

Bits 0:31 - Host transmit buffer address pointer

`impl R<u32, Reg<u32, _DMACHRBAR>>`[src]

`pub fn hrbap(&self) -> HRBAP_R`[src]

Bits 0:31 - Host receive buffer address pointer

`impl R<u32, Reg<u32, _OTG_FS_HCFG>>`[src]

`pub fn fslspcs(&self) -> FSLSPCS_R`[src]

Bits 0:1 - FS/LS PHY clock select

`pub fn fslss(&self) -> FSLSS_R`[src]

Bit 2 - FS- and LS-only support

`impl R<u32, Reg<u32, _OTG_FS_HFIR>>`[src]

`pub fn frivl(&self) -> FRIVL_R`[src]

Bits 0:15 - Frame interval

`impl R<u32, Reg<u32, _OTG_FS_HFNUM>>`[src]

`pub fn frnum(&self) -> FRNUM_R`[src]

Bits 0:15 - Frame number

`pub fn ftrem(&self) -> FTREM_R`[src]

Bits 16:31 - Frame time remaining

`impl R<u32, Reg<u32, _OTG_FS_HPTXSTS>>`[src]

`pub fn ptxfsavl(&self) -> PTXFSAVL_R`[src]

Bits 0:15 - Periodic transmit data FIFO space available

`pub fn ptxqsav(&self) -> PTXQSAV_R`[src]

Bits 16:23 - Periodic transmit request queue space available

`pub fn ptxqtop(&self) -> PTXQTOP_R`[src]

Bits 24:31 - Top of the periodic transmit request queue

`impl R<u32, Reg<u32, _OTG_FS_HAINT>>`[src]

`pub fn haint(&self) -> HAINT_R`[src]

Bits 0:15 - Channel interrupts

`impl R<u32, Reg<u32, _OTG_FS_HAINTMSK>>`[src]

`pub fn haintm(&self) -> HAINTM_R`[src]

Bits 0:15 - Channel interrupt mask

`impl R<u32, Reg<u32, _OTG_FS_HPRT>>`[src]

`pub fn pcsts(&self) -> PCSTS_R`[src]

Bit 0 - Port connect status

`pub fn pcdet(&self) -> PCDET_R`[src]

Bit 1 - Port connect detected

`pub fn pena(&self) -> PENA_R`[src]

Bit 2 - Port enable

`pub fn penchng(&self) -> PENCHNG_R`[src]

Bit 3 - Port enable/disable change

`pub fn poca(&self) -> POCA_R`[src]

Bit 4 - Port overcurrent active

`pub fn pocchng(&self) -> POCCHNG_R`[src]

Bit 5 - Port overcurrent change

`pub fn pres(&self) -> PRES_R`[src]

Bit 6 - Port resume

`pub fn psusp(&self) -> PSUSP_R`[src]

Bit 7 - Port suspend

`pub fn prst(&self) -> PRST_R`[src]

Bit 8 - Port reset

`pub fn plsts(&self) -> PLSTS_R`[src]

Bits 10:11 - Port line status

`pub fn ppwr(&self) -> PPWR_R`[src]

Bit 12 - Port power

`pub fn ptctl(&self) -> PTCTL_R`[src]

Bits 13:16 - Port test control

`pub fn pspd(&self) -> PSPD_R`[src]

Bits 17:18 - Port speed

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR0>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR1>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR2>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR3>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR4>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR5>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR6>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR7>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCINT0>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT1>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT2>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT3>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT4>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT5>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT6>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINT7>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK0>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK1>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK2>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK3>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK4>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK5>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK6>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK7>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCINT8>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK8>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCTSIZ8>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR9>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCINT9>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK9>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCTSIZ9>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR10>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCINT10>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK10>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCTSIZ10>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_FS_HCCHAR11>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 20:21 - Multicount

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_FS_HCINT11>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_FS_HCINTMSK11>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_FS_HCTSIZ11>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_FS_DCFG>>`[src]

`pub fn dspd(&self) -> DSPD_R`[src]

Bits 0:1 - Device speed

`pub fn nzlsohsk(&self) -> NZLSOHSK_R`[src]

Bit 2 - Non-zero-length status OUT handshake

`pub fn dad(&self) -> DAD_R`[src]

Bits 4:10 - Device address

`pub fn pfivl(&self) -> PFIVL_R`[src]

Bits 11:12 - Periodic frame interval

`impl R<u32, Reg<u32, _OTG_FS_DCTL>>`[src]

`pub fn rwusig(&self) -> RWUSIG_R`[src]

Bit 0 - Remote wakeup signaling

`pub fn sdis(&self) -> SDIS_R`[src]

Bit 1 - Soft disconnect

`pub fn ginsts(&self) -> GINSTS_R`[src]

Bit 2 - Global IN NAK status

`pub fn gonsts(&self) -> GONSTS_R`[src]

Bit 3 - Global OUT NAK status

`pub fn tctl(&self) -> TCTL_R`[src]

Bits 4:6 - Test control

`pub fn sginak(&self) -> SGINAK_R`[src]

Bit 7 - Set global IN NAK

`pub fn cginak(&self) -> CGINAK_R`[src]

Bit 8 - Clear global IN NAK

`pub fn sgonak(&self) -> SGONAK_R`[src]

Bit 9 - Set global OUT NAK

`pub fn cgonak(&self) -> CGONAK_R`[src]

Bit 10 - Clear global OUT NAK

`pub fn poprgdne(&self) -> POPRGDNE_R`[src]

Bit 11 - Power-on programming done

`impl R<u32, Reg<u32, _OTG_FS_DSTS>>`[src]

`pub fn suspsts(&self) -> SUSPSTS_R`[src]

Bit 0 - Suspend status

`pub fn enumspd(&self) -> ENUMSPD_R`[src]

Bits 1:2 - Enumerated speed

`pub fn eerr(&self) -> EERR_R`[src]

Bit 3 - Erratic error

`pub fn fnsof(&self) -> FNSOF_R`[src]

Bits 8:21 - Frame number of the received SOF

`impl R<u32, Reg<u32, _OTG_FS_DIEPMSK>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed interrupt mask

`pub fn epdm(&self) -> EPDM_R`[src]

Bit 1 - Endpoint disabled interrupt mask

`pub fn tom(&self) -> TOM_R`[src]

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

`pub fn ittxfemsk(&self) -> ITTXFEMSK_R`[src]

Bit 4 - IN token received when TxFIFO empty mask

`pub fn inepnmm(&self) -> INEPNMM_R`[src]

Bit 5 - IN token received with EP mismatch mask

`pub fn inepnem(&self) -> INEPNEM_R`[src]

Bit 6 - IN endpoint NAK effective mask

`impl R<u32, Reg<u32, _OTG_FS_DOEPMSK>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed interrupt mask

`pub fn epdm(&self) -> EPDM_R`[src]

Bit 1 - Endpoint disabled interrupt mask

`pub fn stupm(&self) -> STUPM_R`[src]

Bit 3 - SETUP phase done mask

`pub fn otepdm(&self) -> OTEPDM_R`[src]

Bit 4 - OUT token received when endpoint disabled mask

`impl R<u32, Reg<u32, _OTG_FS_DAINT>>`[src]

`pub fn iepint(&self) -> IEPINT_R`[src]

Bits 0:15 - IN endpoint interrupt bits

`pub fn oepint(&self) -> OEPINT_R`[src]

Bits 16:31 - OUT endpoint interrupt bits

`impl R<u32, Reg<u32, _OTG_FS_DAINTMSK>>`[src]

`pub fn iepm(&self) -> IEPM_R`[src]

Bits 0:15 - IN EP interrupt mask bits

`pub fn oepint(&self) -> OEPINT_R`[src]

Bits 16:31 - OUT endpoint interrupt bits

`impl R<u32, Reg<u32, _OTG_FS_DVBUSDIS>>`[src]

`pub fn vbusdt(&self) -> VBUSDT_R`[src]

Bits 0:15 - Device VBUS discharge time

`impl R<u32, Reg<u32, _OTG_FS_DVBUSPULSE>>`[src]

`pub fn dvbusp(&self) -> DVBUSP_R`[src]

Bits 0:11 - Device VBUS pulsing time

`impl R<u32, Reg<u32, _OTG_FS_DIEPEMPMSK>>`[src]

`pub fn ineptxfem(&self) -> INEPTXFEM_R`[src]

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL0>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:1 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL1>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TXFNUM

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL2>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TXFNUM

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL3>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TXFNUM

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL0>>`[src]

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - SNPM

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:1 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL1>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - SNPM

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL2>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - SNPM

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL3>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ0>>`[src]

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:20 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:6 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ0>>`[src]

`pub fn stupcnt(&self) -> STUPCNT_R`[src]

Bits 29:30 - SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bit 19 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:6 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ1>>`[src]

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 29:30 - Multi count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ2>>`[src]

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 29:30 - Multi count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ3>>`[src]

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 29:30 - Multi count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS0>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS1>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS2>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS3>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ1>>`[src]

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ2>>`[src]

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ3>>`[src]

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL4>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TXFNUM

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DIEPINT4>>`[src]

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - TXFE

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - INEPNE

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - ITTXFE

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - TOC

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - EPDISD

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - XFRC

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ4>>`[src]

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 29:30 - Multi count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS4>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DIEPCTL5>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TXFNUM

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DIEPINT5>>`[src]

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - TXFE

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - INEPNE

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - ITTXFE

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - TOC

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - EPDISD

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - XFRC

`impl R<u32, Reg<u32, _OTG_FS_DIEPTSIZ55>>`[src]

`pub fn mcnt(&self) -> MCNT_R`[src]

Bits 29:30 - Multi count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DTXFSTS55>>`[src]

`pub fn ineptfsav(&self) -> INEPTFSAV_R`[src]

Bits 0:15 - IN endpoint TxFIFO space available

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL4>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - SNPM

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPINT4>>`[src]

`pub fn b2bstup(&self) -> B2BSTUP_R`[src]

Bit 6 - B2BSTUP

`pub fn otepdis(&self) -> OTEPDIS_R`[src]

Bit 4 - OTEPDIS

`pub fn stup(&self) -> STUP_R`[src]

Bit 3 - STUP

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - EPDISD

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - XFRC

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ4>>`[src]

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_DOEPCTL5>>`[src]

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - EPENA

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - EPDIS

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - Stall

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - SNPM

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - EPTYP

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAKSTS

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - EONUM/DPID

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USBAEP

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - MPSIZ

`impl R<u32, Reg<u32, _OTG_FS_DOEPINT5>>`[src]

`pub fn b2bstup(&self) -> B2BSTUP_R`[src]

Bit 6 - B2BSTUP

`pub fn otepdis(&self) -> OTEPDIS_R`[src]

Bit 4 - OTEPDIS

`pub fn stup(&self) -> STUP_R`[src]

Bit 3 - STUP

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - EPDISD

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - XFRC

`impl R<u32, Reg<u32, _OTG_FS_DOEPTSIZ5>>`[src]

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`impl R<u32, Reg<u32, _OTG_FS_PCGCCTL>>`[src]

`pub fn stppclk(&self) -> STPPCLK_R`[src]

Bit 0 - Stop PHY clock

`pub fn gatehclk(&self) -> GATEHCLK_R`[src]

Bit 1 - Gate HCLK

`pub fn physusp(&self) -> PHYSUSP_R`[src]

Bit 4 - PHY Suspended

`impl R<u32, Reg<u32, _OTG_HS_HCFG>>`[src]

`pub fn fslspcs(&self) -> FSLSPCS_R`[src]

Bits 0:1 - FS/LS PHY clock select

`pub fn fslss(&self) -> FSLSS_R`[src]

Bit 2 - FS- and LS-only support

`impl R<u32, Reg<u32, _OTG_HS_HFIR>>`[src]

`pub fn frivl(&self) -> FRIVL_R`[src]

Bits 0:15 - Frame interval

`impl R<u32, Reg<u32, _OTG_HS_HFNUM>>`[src]

`pub fn frnum(&self) -> FRNUM_R`[src]

Bits 0:15 - Frame number

`pub fn ftrem(&self) -> FTREM_R`[src]

Bits 16:31 - Frame time remaining

`impl R<u32, Reg<u32, _OTG_HS_HPTXSTS>>`[src]

`pub fn ptxfsavl(&self) -> PTXFSAVL_R`[src]

Bits 0:15 - Periodic transmit data FIFO space available

`pub fn ptxqsav(&self) -> PTXQSAV_R`[src]

Bits 16:23 - Periodic transmit request queue space available

`pub fn ptxqtop(&self) -> PTXQTOP_R`[src]

Bits 24:31 - Top of the periodic transmit request queue

`impl R<u32, Reg<u32, _OTG_HS_HAINT>>`[src]

`pub fn haint(&self) -> HAINT_R`[src]

Bits 0:15 - Channel interrupts

`impl R<u32, Reg<u32, _OTG_HS_HAINTMSK>>`[src]

`pub fn haintm(&self) -> HAINTM_R`[src]

Bits 0:15 - Channel interrupt mask

`impl R<u32, Reg<u32, _OTG_HS_HPRT>>`[src]

`pub fn pcsts(&self) -> PCSTS_R`[src]

Bit 0 - Port connect status

`pub fn pcdet(&self) -> PCDET_R`[src]

Bit 1 - Port connect detected

`pub fn pena(&self) -> PENA_R`[src]

Bit 2 - Port enable

`pub fn penchng(&self) -> PENCHNG_R`[src]

Bit 3 - Port enable/disable change

`pub fn poca(&self) -> POCA_R`[src]

Bit 4 - Port overcurrent active

`pub fn pocchng(&self) -> POCCHNG_R`[src]

Bit 5 - Port overcurrent change

`pub fn pres(&self) -> PRES_R`[src]

Bit 6 - Port resume

`pub fn psusp(&self) -> PSUSP_R`[src]

Bit 7 - Port suspend

`pub fn prst(&self) -> PRST_R`[src]

Bit 8 - Port reset

`pub fn plsts(&self) -> PLSTS_R`[src]

Bits 10:11 - Port line status

`pub fn ppwr(&self) -> PPWR_R`[src]

Bit 12 - Port power

`pub fn ptctl(&self) -> PTCTL_R`[src]

Bits 13:16 - Port test control

`pub fn pspd(&self) -> PSPD_R`[src]

Bits 17:18 - Port speed

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR0>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR1>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR2>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR3>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR4>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR5>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR6>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR7>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR8>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR9>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR10>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR11>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT0>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT1>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT2>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT3>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT4>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT5>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT6>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT7>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT8>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT9>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT10>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT11>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCINT0>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT1>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT2>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT3>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT4>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT5>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT6>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT7>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT8>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT9>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT10>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINT11>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK0>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK1>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK2>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK3>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK4>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK5>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK6>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK7>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK8>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK9>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK10>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error mask

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error mask

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK11>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - response received interrupt mask

`pub fn txerrm(&self) -> TXERRM_R`[src]

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR12>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT12>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCINT12>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK12>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCTSIZ12>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_HS_HCDMA12>>`[src]

`pub fn dmaaddr(&self) -> DMAADDR_R`[src]

Bits 0:31 - DMA address

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR13>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT13>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCINT13>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK13>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALLM response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCTSIZ13>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_HS_HCDMA13>>`[src]

`pub fn dmaaddr(&self) -> DMAADDR_R`[src]

Bits 0:31 - DMA address

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR14>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT14>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCINT14>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK14>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stallm(&self) -> STALLM_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAKM response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACKM response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCTSIZ14>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_HS_HCDMA14>>`[src]

`pub fn dmaaddr(&self) -> DMAADDR_R`[src]

Bits 0:31 - DMA address

`impl R<u32, Reg<u32, _OTG_HS_HCCHAR15>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn epnum(&self) -> EPNUM_R`[src]

Bits 11:14 - Endpoint number

`pub fn epdir(&self) -> EPDIR_R`[src]

Bit 15 - Endpoint direction

`pub fn lsdev(&self) -> LSDEV_R`[src]

Bit 17 - Low-speed device

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn mc(&self) -> MC_R`[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

`pub fn dad(&self) -> DAD_R`[src]

Bits 22:28 - Device address

`pub fn oddfrm(&self) -> ODDFRM_R`[src]

Bit 29 - Odd frame

`pub fn chdis(&self) -> CHDIS_R`[src]

Bit 30 - Channel disable

`pub fn chena(&self) -> CHENA_R`[src]

Bit 31 - Channel enable

`impl R<u32, Reg<u32, _OTG_HS_HCSPLT15>>`[src]

`pub fn prtaddr(&self) -> PRTADDR_R`[src]

Bits 0:6 - Port address

`pub fn hubaddr(&self) -> HUBADDR_R`[src]

Bits 7:13 - Hub address

`pub fn xactpos(&self) -> XACTPOS_R`[src]

Bits 14:15 - XACTPOS

`pub fn complsplt(&self) -> COMPLSPLT_R`[src]

Bit 16 - Do complete split

`pub fn spliten(&self) -> SPLITEN_R`[src]

Bit 31 - Split enable

`impl R<u32, Reg<u32, _OTG_HS_HCINT15>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed

`pub fn chh(&self) -> CHH_R`[src]

Bit 1 - Channel halted

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 4 - NAK response received interrupt

`pub fn ack(&self) -> ACK_R`[src]

Bit 5 - ACK response received/transmitted interrupt

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerr(&self) -> TXERR_R`[src]

Bit 7 - Transaction error

`pub fn bberr(&self) -> BBERR_R`[src]

Bit 8 - Babble error

`pub fn frmor(&self) -> FRMOR_R`[src]

Bit 9 - Frame overrun

`pub fn dterr(&self) -> DTERR_R`[src]

Bit 10 - Data toggle error

`impl R<u32, Reg<u32, _OTG_HS_HCINTMSK15>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed mask

`pub fn chhm(&self) -> CHHM_R`[src]

Bit 1 - Channel halted mask

`pub fn ahberr(&self) -> AHBERR_R`[src]

Bit 2 - AHB error

`pub fn stall(&self) -> STALL_R`[src]

Bit 3 - STALL response received interrupt mask

`pub fn nakm(&self) -> NAKM_R`[src]

Bit 4 - NAK response received interrupt mask

`pub fn ackm(&self) -> ACKM_R`[src]

Bit 5 - ACK response received/transmitted interrupt mask

`pub fn nyet(&self) -> NYET_R`[src]

Bit 6 - Response received interrupt

`pub fn txerrm(&self) -> TXERRM_R`[src]

Bit 7 - Transaction error

`pub fn bberrm(&self) -> BBERRM_R`[src]

Bit 8 - Babble error

`pub fn frmorm(&self) -> FRMORM_R`[src]

Bit 9 - Frame overrun mask

`pub fn dterrm(&self) -> DTERRM_R`[src]

Bit 10 - Data toggle error mask

`impl R<u32, Reg<u32, _OTG_HS_HCTSIZ15>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn dpid(&self) -> DPID_R`[src]

Bits 29:30 - Data PID

`impl R<u32, Reg<u32, _OTG_HS_HCDMA15>>`[src]

`pub fn dmaaddr(&self) -> DMAADDR_R`[src]

Bits 0:31 - DMA address

`impl R<u32, Reg<u32, _OTG_HS_DCFG>>`[src]

`pub fn dspd(&self) -> DSPD_R`[src]

Bits 0:1 - Device speed

`pub fn nzlsohsk(&self) -> NZLSOHSK_R`[src]

Bit 2 - Nonzero-length status OUT handshake

`pub fn dad(&self) -> DAD_R`[src]

Bits 4:10 - Device address

`pub fn pfivl(&self) -> PFIVL_R`[src]

Bits 11:12 - Periodic (micro)frame interval

`pub fn perschivl(&self) -> PERSCHIVL_R`[src]

Bits 24:25 - Periodic scheduling interval

`impl R<u32, Reg<u32, _OTG_HS_DCTL>>`[src]

`pub fn rwusig(&self) -> RWUSIG_R`[src]

Bit 0 - Remote wakeup signaling

`pub fn sdis(&self) -> SDIS_R`[src]

Bit 1 - Soft disconnect

`pub fn ginsts(&self) -> GINSTS_R`[src]

Bit 2 - Global IN NAK status

`pub fn gonsts(&self) -> GONSTS_R`[src]

Bit 3 - Global OUT NAK status

`pub fn tctl(&self) -> TCTL_R`[src]

Bits 4:6 - Test control

`pub fn poprgdne(&self) -> POPRGDNE_R`[src]

Bit 11 - Power-on programming done

`impl R<u32, Reg<u32, _OTG_HS_DSTS>>`[src]

`pub fn suspsts(&self) -> SUSPSTS_R`[src]

Bit 0 - Suspend status

`pub fn enumspd(&self) -> ENUMSPD_R`[src]

Bits 1:2 - Enumerated speed

`pub fn eerr(&self) -> EERR_R`[src]

Bit 3 - Erratic error

`pub fn fnsof(&self) -> FNSOF_R`[src]

Bits 8:21 - Frame number of the received SOF

`impl R<u32, Reg<u32, _OTG_HS_DIEPMSK>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed interrupt mask

`pub fn epdm(&self) -> EPDM_R`[src]

Bit 1 - Endpoint disabled interrupt mask

`pub fn tom(&self) -> TOM_R`[src]

Bit 3 - Timeout condition mask (nonisochronous endpoints)

`pub fn ittxfemsk(&self) -> ITTXFEMSK_R`[src]

Bit 4 - IN token received when TxFIFO empty mask

`pub fn inepnmm(&self) -> INEPNMM_R`[src]

Bit 5 - IN token received with EP mismatch mask

`pub fn inepnem(&self) -> INEPNEM_R`[src]

Bit 6 - IN endpoint NAK effective mask

`pub fn txfurm(&self) -> TXFURM_R`[src]

Bit 8 - FIFO underrun mask

`pub fn bim(&self) -> BIM_R`[src]

Bit 9 - BNA interrupt mask

`impl R<u32, Reg<u32, _OTG_HS_DOEPMSK>>`[src]

`pub fn xfrcm(&self) -> XFRCM_R`[src]

Bit 0 - Transfer completed interrupt mask

`pub fn epdm(&self) -> EPDM_R`[src]

Bit 1 - Endpoint disabled interrupt mask

`pub fn stupm(&self) -> STUPM_R`[src]

Bit 3 - SETUP phase done mask

`pub fn otepdm(&self) -> OTEPDM_R`[src]

Bit 4 - OUT token received when endpoint disabled mask

`pub fn b2bstup(&self) -> B2BSTUP_R`[src]

Bit 6 - Back-to-back SETUP packets received mask

`pub fn opem(&self) -> OPEM_R`[src]

Bit 8 - OUT packet error mask

`pub fn boim(&self) -> BOIM_R`[src]

Bit 9 - BNA interrupt mask

`impl R<u32, Reg<u32, _OTG_HS_DAINT>>`[src]

`pub fn iepint(&self) -> IEPINT_R`[src]

Bits 0:15 - IN endpoint interrupt bits

`pub fn oepint(&self) -> OEPINT_R`[src]

Bits 16:31 - OUT endpoint interrupt bits

`impl R<u32, Reg<u32, _OTG_HS_DAINTMSK>>`[src]

`pub fn iepm(&self) -> IEPM_R`[src]

Bits 0:15 - IN EP interrupt mask bits

`pub fn oepm(&self) -> OEPM_R`[src]

Bits 16:31 - OUT EP interrupt mask bits

`impl R<u32, Reg<u32, _OTG_HS_DVBUSDIS>>`[src]

`pub fn vbusdt(&self) -> VBUSDT_R`[src]

Bits 0:15 - Device VBUS discharge time

`impl R<u32, Reg<u32, _OTG_HS_DVBUSPULSE>>`[src]

`pub fn dvbusp(&self) -> DVBUSP_R`[src]

Bits 0:11 - Device VBUS pulsing time

`impl R<u32, Reg<u32, _OTG_HS_DTHRCTL>>`[src]

`pub fn nonisothren(&self) -> NONISOTHREN_R`[src]

Bit 0 - Nonisochronous IN endpoints threshold enable

`pub fn isothren(&self) -> ISOTHREN_R`[src]

Bit 1 - ISO IN endpoint threshold enable

`pub fn txthrlen(&self) -> TXTHRLEN_R`[src]

Bits 2:10 - Transmit threshold length

`pub fn rxthren(&self) -> RXTHREN_R`[src]

Bit 16 - Receive threshold enable

`pub fn rxthrlen(&self) -> RXTHRLEN_R`[src]

Bits 17:25 - Receive threshold length

`pub fn arpen(&self) -> ARPEN_R`[src]

Bit 27 - Arbiter parking enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPEMPMSK>>`[src]

`pub fn ineptxfem(&self) -> INEPTXFEM_R`[src]

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

`impl R<u32, Reg<u32, _OTG_HS_DEACHINT>>`[src]

`pub fn iep1int(&self) -> IEP1INT_R`[src]

Bit 1 - IN endpoint 1interrupt bit

`pub fn oep1int(&self) -> OEP1INT_R`[src]

Bit 17 - OUT endpoint 1 interrupt bit

`impl R<u32, Reg<u32, _OTG_HS_DEACHINTMSK>>`[src]

`pub fn iep1intm(&self) -> IEP1INTM_R`[src]

Bit 1 - IN Endpoint 1 interrupt mask bit

`pub fn oep1intm(&self) -> OEP1INTM_R`[src]

Bit 17 - OUT Endpoint 1 interrupt mask bit

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL0>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL1>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL2>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL3>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL4>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL5>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL6>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPCTL7>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even/odd frame

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn txfnum(&self) -> TXFNUM_R`[src]

Bits 22:25 - TxFIFO number

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT0>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT1>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT2>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT3>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT4>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT5>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT6>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPINT7>>`[src]

`pub fn xfrc(&self) -> XFRC_R`[src]

Bit 0 - Transfer completed interrupt

`pub fn epdisd(&self) -> EPDISD_R`[src]

Bit 1 - Endpoint disabled interrupt

`pub fn toc(&self) -> TOC_R`[src]

Bit 3 - Timeout condition

`pub fn ittxfe(&self) -> ITTXFE_R`[src]

Bit 4 - IN token received when TxFIFO is empty

`pub fn inepne(&self) -> INEPNE_R`[src]

Bit 6 - IN endpoint NAK effective

`pub fn txfe(&self) -> TXFE_R`[src]

Bit 7 - Transmit FIFO empty

`pub fn txfifoudrn(&self) -> TXFIFOUDRN_R`[src]

Bit 8 - Transmit Fifo Underrun

`pub fn bna(&self) -> BNA_R`[src]

Bit 9 - Buffer not available interrupt

`pub fn pktdrpsts(&self) -> PKTDRPSTS_R`[src]

Bit 11 - Packet dropped status

`pub fn berr(&self) -> BERR_R`[src]

Bit 12 - Babble error interrupt

`pub fn nak(&self) -> NAK_R`[src]

Bit 13 - NAK interrupt

`impl R<u32, Reg<u32, _OTG_HS_DIEPTSIZ0>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bit 15 - USB active endpoint

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL1>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even odd frame/Endpoint data PID

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL2>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even odd frame/Endpoint data PID

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL3>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL5>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even odd frame/Endpoint data PID

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL6>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even odd frame/Endpoint data PID

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPCTL7>>`[src]

`pub fn mpsiz(&self) -> MPSIZ_R`[src]

Bits 0:10 - Maximum packet size

`pub fn usbaep(&self) -> USBAEP_R`[src]

Bit 15 - USB active endpoint

`pub fn eonum_dpid(&self) -> EONUM_DPID_R`[src]

Bit 16 - Even odd frame/Endpoint data PID

`pub fn naksts(&self) -> NAKSTS_R`[src]

Bit 17 - NAK status

`pub fn eptyp(&self) -> EPTYP_R`[src]

Bits 18:19 - Endpoint type

`pub fn snpm(&self) -> SNPM_R`[src]

Bit 20 - Snoop mode

`pub fn stall(&self) -> STALL_R`[src]

Bit 21 - STALL handshake

`pub fn epdis(&self) -> EPDIS_R`[src]

Bit 30 - Endpoint disable

`pub fn epena(&self) -> EPENA_R`[src]

Bit 31 - Endpoint enable

`impl R<u32, Reg<u32, _OTG_HS_DOEPTSIZ5>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`impl R<u32, Reg<u32, _OTG_HS_DOEPTSIZ6>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`impl R<u32, Reg<u32, _OTG_HS_DOEPTSIZ7>>`[src]

`pub fn xfrsiz(&self) -> XFRSIZ_R`[src]

Bits 0:18 - Transfer size

`pub fn pktcnt(&self) -> PKTCNT_R`[src]

Bits 19:28 - Packet count

`pub fn rxdpid_stupcnt(&self) -> RXDPID_STUPCNT_R`[src]

Bits 29:30 - Received data PID/SETUP packet count

`impl R<u32, Reg<u32, _OTG_HS_PCGCR>>`[src]

`pub fn stppclk(&self) -> STPPCLK_R`[src]

Bit 0 - Stop PHY clock

`pub fn gatehclk(&self) -> GATEHCLK_R`[src]

Bit 1 - Gate HCLK

`pub fn physusp(&self) -> PHYSUSP_R`[src]

Bit 4 - PHY suspended

`impl R<u32, Reg<u32, _DSI_VR>>`[src]

`pub fn version(&self) -> VERSION_R`[src]

Bits 0:31 - Version of the DSI Host

`impl R<u32, Reg<u32, _DSI_CR>>`[src]

`pub fn en(&self) -> EN_R`[src]

Bit 0 - Enable

`impl R<u32, Reg<u32, _DSI_CCR>>`[src]

`pub fn txeckdiv(&self) -> TXECKDIV_R`[src]

Bits 0:7 - TX Escape Clock Division

`pub fn tockdiv(&self) -> TOCKDIV_R`[src]

Bits 8:15 - Timeout Clock Division

`impl R<u32, Reg<u32, _DSI_LVCIDR>>`[src]

`pub fn vcid(&self) -> VCID_R`[src]

Bits 0:1 - Virtual Channel ID

`impl R<u32, Reg<u32, _DSI_LCOLCR>>`[src]

`pub fn colc(&self) -> COLC_R`[src]

Bits 0:3 - Color Coding

`pub fn lpe(&self) -> LPE_R`[src]

Bit 8 - Loosely Packet Enable

`impl R<u32, Reg<u32, _DSI_LPCR>>`[src]

`pub fn dep(&self) -> DEP_R`[src]

Bit 0 - Data Enable Polarity

`pub fn vsp(&self) -> VSP_R`[src]

Bit 1 - VSYNC Polarity

`pub fn hsp(&self) -> HSP_R`[src]

Bit 2 - HSYNC Polarity

`impl R<u32, Reg<u32, _DSI_LPMCR>>`[src]

`pub fn vlpsize(&self) -> VLPSIZE_R`[src]

Bits 0:7 - VACT Largest Packet Size

`pub fn lpsize(&self) -> LPSIZE_R`[src]

Bits 16:23 - Largest Packet Size

`impl R<u32, Reg<u32, _DSI_PCR>>`[src]

`pub fn ettxe(&self) -> ETTXE_R`[src]

Bit 0 - EoTp Transmission Enable

`pub fn etrxe(&self) -> ETRXE_R`[src]

Bit 1 - EoTp Reception Enable

`pub fn btae(&self) -> BTAE_R`[src]

Bit 2 - Bus Turn Around Enable

`pub fn eccrxe(&self) -> ECCRXE_R`[src]

Bit 3 - ECC Reception Enable

`pub fn crcrxe(&self) -> CRCRXE_R`[src]

Bit 4 - CRC Reception Enable

`impl R<u32, Reg<u32, _DSI_GVCIDR>>`[src]

`pub fn vcid(&self) -> VCID_R`[src]

Bits 0:1 - Virtual Channel ID

`impl R<u32, Reg<u32, _DSI_MCR>>`[src]

`pub fn cmdm(&self) -> CMDM_R`[src]

Bit 0 - Command mode

`impl R<u32, Reg<u32, _DSI_VMCR>>`[src]

`pub fn vmt(&self) -> VMT_R`[src]

Bits 0:1 - Video mode Type

`pub fn lpvsae(&self) -> LPVSAE_R`[src]

Bit 8 - Low-Power Vertical Sync Active Enable

`pub fn lpvbpe(&self) -> LPVBPE_R`[src]

Bit 9 - Low-power Vertical Back-Porch Enable

`pub fn lpvfpe(&self) -> LPVFPE_R`[src]

Bit 10 - Low-power Vertical Front-porch Enable

`pub fn lpvae(&self) -> LPVAE_R`[src]

Bit 11 - Low-Power Vertical Active Enable

`pub fn lphbpe(&self) -> LPHBPE_R`[src]

Bit 12 - Low-Power Horizontal Back-Porch Enable

`pub fn lphfpe(&self) -> LPHFPE_R`[src]

Bit 13 - Low-Power Horizontal Front-Porch Enable

`pub fn fbtaae(&self) -> FBTAAE_R`[src]

Bit 14 - Frame Bus-Turn-Around Acknowledge Enable

`pub fn lpce(&self) -> LPCE_R`[src]

Bit 15 - Low-Power Command Enable

`pub fn pge(&self) -> PGE_R`[src]

Bit 16 - Pattern Generator Enable

`pub fn pgm(&self) -> PGM_R`[src]

Bit 20 - Pattern Generator mode

`pub fn pgo(&self) -> PGO_R`[src]

Bit 24 - Pattern Generator Orientation

`impl R<u32, Reg<u32, _DSI_VPCR>>`[src]

`pub fn vpsize(&self) -> VPSIZE_R`[src]

Bits 0:13 - Video Packet Size

`impl R<u32, Reg<u32, _DSI_VCCR>>`[src]

`pub fn numc(&self) -> NUMC_R`[src]

Bits 0:12 - Number of Chunks

`impl R<u32, Reg<u32, _DSI_VNPCR>>`[src]

`pub fn npsize(&self) -> NPSIZE_R`[src]

Bits 0:12 - Null Packet Size

`impl R<u32, Reg<u32, _DSI_VHSACR>>`[src]

`pub fn hsa(&self) -> HSA_R`[src]

Bits 0:11 - Horizontal Synchronism Active duration

`impl R<u32, Reg<u32, _DSI_VHBPCR>>`[src]

`pub fn hbp(&self) -> HBP_R`[src]

Bits 0:11 - Horizontal Back-Porch duration

`impl R<u32, Reg<u32, _DSI_VLCR>>`[src]

`pub fn hline(&self) -> HLINE_R`[src]

Bits 0:14 - Horizontal Line duration

`impl R<u32, Reg<u32, _DSI_VVSACR>>`[src]

`pub fn vsa(&self) -> VSA_R`[src]

Bits 0:9 - Vertical Synchronism Active duration

`impl R<u32, Reg<u32, _DSI_VVBPCR>>`[src]

`pub fn vbp(&self) -> VBP_R`[src]

Bits 0:9 - Vertical Back-Porch duration

`impl R<u32, Reg<u32, _DSI_VVFPCR>>`[src]

`pub fn vfp(&self) -> VFP_R`[src]

Bits 0:9 - Vertical Front-Porch duration

`impl R<u32, Reg<u32, _DSI_VVACR>>`[src]

`pub fn va(&self) -> VA_R`[src]

Bits 0:13 - Vertical Active duration

`impl R<u32, Reg<u32, _DSI_LCCR>>`[src]

`pub fn cmdsize(&self) -> CMDSIZE_R`[src]

Bits 0:15 - Command Size

`impl R<u32, Reg<u32, _DSI_CMCR>>`[src]

`pub fn teare(&self) -> TEARE_R`[src]

Bit 0 - Tearing Effect Acknowledge Request Enable

`pub fn are(&self) -> ARE_R`[src]

Bit 1 - Acknowledge Request Enable

`pub fn gsw0tx(&self) -> GSW0TX_R`[src]

Bit 8 - Generic Short Write Zero parameters Transmission

`pub fn gsw1tx(&self) -> GSW1TX_R`[src]

Bit 9 - Generic Short Write One parameters Transmission

`pub fn gsw2tx(&self) -> GSW2TX_R`[src]

Bit 10 - Generic Short Write Two parameters Transmission

`pub fn gsr0tx(&self) -> GSR0TX_R`[src]

Bit 11 - Generic Short Read Zero parameters Transmission

`pub fn gsr1tx(&self) -> GSR1TX_R`[src]

Bit 12 - Generic Short Read One parameters Transmission

`pub fn gsr2tx(&self) -> GSR2TX_R`[src]

Bit 13 - Generic Short Read Two parameters Transmission

`pub fn glwtx(&self) -> GLWTX_R`[src]

Bit 14 - Generic Long Write Transmission

`pub fn dsw0tx(&self) -> DSW0TX_R`[src]

Bit 16 - DCS Short Write Zero parameter Transmission

`pub fn dsw1tx(&self) -> DSW1TX_R`[src]

Bit 17 - DCS Short Read One parameter Transmission

`pub fn dsr0tx(&self) -> DSR0TX_R`[src]

Bit 18 - DCS Short Read Zero parameter Transmission

`pub fn dlwtx(&self) -> DLWTX_R`[src]

Bit 19 - DCS Long Write Transmission

`pub fn mrdps(&self) -> MRDPS_R`[src]

Bit 24 - Maximum Read Packet Size

`impl R<u32, Reg<u32, _DSI_GHCR>>`[src]

`pub fn dt(&self) -> DT_R`[src]

Bits 0:5 - Type

`pub fn vcid(&self) -> VCID_R`[src]

Bits 6:7 - Channel

`pub fn wclsb(&self) -> WCLSB_R`[src]

Bits 8:15 - WordCount LSB

`pub fn wcmsb(&self) -> WCMSB_R`[src]

Bits 16:23 - WordCount MSB

`impl R<u32, Reg<u32, _DSI_GPDR>>`[src]

`pub fn data1(&self) -> DATA1_R`[src]

Bits 0:7 - Payload Byte 1

`pub fn data2(&self) -> DATA2_R`[src]

Bits 8:15 - Payload Byte 2

`pub fn data3(&self) -> DATA3_R`[src]

Bits 16:23 - Payload Byte 3

`pub fn data4(&self) -> DATA4_R`[src]

Bits 24:31 - Payload Byte 4

`impl R<u32, Reg<u32, _DSI_GPSR>>`[src]

`pub fn cmdfe(&self) -> CMDFE_R`[src]

Bit 0 - Command FIFO Empty

`pub fn cmdff(&self) -> CMDFF_R`[src]

Bit 1 - Command FIFO Full

`pub fn pwrfe(&self) -> PWRFE_R`[src]

Bit 2 - Payload Write FIFO Empty

`pub fn pwrff(&self) -> PWRFF_R`[src]

Bit 3 - Payload Write FIFO Full

`pub fn prdfe(&self) -> PRDFE_R`[src]

Bit 4 - Payload Read FIFO Empty

`pub fn prdff(&self) -> PRDFF_R`[src]

Bit 5 - Payload Read FIFO Full

`pub fn rcb(&self) -> RCB_R`[src]

Bit 6 - Read Command Busy

`impl R<u32, Reg<u32, _DSI_TCCR0>>`[src]

`pub fn lprx_tocnt(&self) -> LPRX_TOCNT_R`[src]

Bits 0:15 - Low-power Reception Timeout Counter

`pub fn hstx_tocnt(&self) -> HSTX_TOCNT_R`[src]

Bits 16:31 - High-Speed Transmission Timeout Counter

`impl R<u32, Reg<u32, _DSI_TCCR1>>`[src]

`pub fn hsrd_tocnt(&self) -> HSRD_TOCNT_R`[src]

Bits 0:15 - High-Speed Read Timeout Counter

`impl R<u32, Reg<u32, _DSI_TCCR2>>`[src]

`pub fn lprd_tocnt(&self) -> LPRD_TOCNT_R`[src]

Bits 0:15 - Low-Power Read Timeout Counter

`impl R<u32, Reg<u32, _DSI_TCCR3>>`[src]

`pub fn hswr_tocnt(&self) -> HSWR_TOCNT_R`[src]

Bits 0:15 - High-Speed Write Timeout Counter

`pub fn pm(&self) -> PM_R`[src]

Bit 24 - Presp mode

`impl R<u32, Reg<u32, _DSI_TCCR4>>`[src]

`pub fn lswr_tocnt(&self) -> LSWR_TOCNT_R`[src]

Bits 0:15 - Low-Power Write Timeout Counter

`impl R<u32, Reg<u32, _DSI_TCCR5>>`[src]

`pub fn bta_tocnt(&self) -> BTA_TOCNT_R`[src]

Bits 0:15 - Bus-Turn-Around Timeout Counter

`impl R<u32, Reg<u32, _DSI_CLCR>>`[src]

`pub fn dpcc(&self) -> DPCC_R`[src]

Bit 0 - D-PHY Clock Control

`pub fn acr(&self) -> ACR_R`[src]

Bit 1 - Automatic Clock lane Control

`impl R<u32, Reg<u32, _DSI_CLTCR>>`[src]

`pub fn lp2hs_time(&self) -> LP2HS_TIME_R`[src]

Bits 0:9 - Low-Power to High-Speed Time

`pub fn hs2lp_time(&self) -> HS2LP_TIME_R`[src]

Bits 16:25 - High-Speed to Low-Power Time

`impl R<u32, Reg<u32, _DSI_DLTCR>>`[src]

`pub fn mrd_time(&self) -> MRD_TIME_R`[src]

Bits 0:14 - Maximum Read Time

`pub fn lp2hs_time(&self) -> LP2HS_TIME_R`[src]

Bits 16:23 - Low-Power To High-Speed Time

`pub fn hs2lp_time(&self) -> HS2LP_TIME_R`[src]

Bits 24:31 - High-Speed To Low-Power Time

`impl R<u32, Reg<u32, _DSI_PCTLR>>`[src]

`pub fn den(&self) -> DEN_R`[src]

Bit 1 - Digital Enable

`pub fn cke(&self) -> CKE_R`[src]

Bit 2 - Clock Enable

`impl R<u32, Reg<u32, _DSI_PCONFR>>`[src]

`pub fn nl(&self) -> NL_R`[src]

Bits 0:1 - Number of Lanes

`pub fn sw_time(&self) -> SW_TIME_R`[src]

Bits 8:15 - Stop Wait Time

`impl R<u32, Reg<u32, _DSI_PUCR>>`[src]

`pub fn urcl(&self) -> URCL_R`[src]

Bit 0 - ULPS Request on Clock Lane

`pub fn uecl(&self) -> UECL_R`[src]

Bit 1 - ULPS Exit on Clock Lane

`pub fn urdl(&self) -> URDL_R`[src]

Bit 2 - ULPS Request on Data Lane

`pub fn uedl(&self) -> UEDL_R`[src]

Bit 3 - ULPS Exit on Data Lane

`impl R<u32, Reg<u32, _DSI_PTTCR>>`[src]

`pub fn tx_trig(&self) -> TX_TRIG_R`[src]

Bits 0:3 - Transmission Trigger

`impl R<u32, Reg<u32, _DSI_PSR>>`[src]

`pub fn pd(&self) -> PD_R`[src]

Bit 1 - PHY Direction

`pub fn pssc(&self) -> PSSC_R`[src]

Bit 2 - PHY Stop State Clock lane

`pub fn uanc(&self) -> UANC_R`[src]

Bit 3 - ULPS Active Not Clock lane

`pub fn pss0(&self) -> PSS0_R`[src]

Bit 4 - PHY Stop State lane 0

`pub fn uan0(&self) -> UAN0_R`[src]

Bit 5 - ULPS Active Not lane 1

`pub fn rue0(&self) -> RUE0_R`[src]

Bit 6 - RX ULPS Escape lane 0

`pub fn pss1(&self) -> PSS1_R`[src]

Bit 7 - PHY Stop State lane 1

`pub fn uan1(&self) -> UAN1_R`[src]

Bit 8 - ULPS Active Not lane 1

`impl R<u32, Reg<u32, _DSI_ISR0>>`[src]

`pub fn ae0(&self) -> AE0_R`[src]

Bit 0 - Acknowledge Error 0

`pub fn ae1(&self) -> AE1_R`[src]

Bit 1 - Acknowledge Error 1

`pub fn ae2(&self) -> AE2_R`[src]

Bit 2 - Acknowledge Error 2

`pub fn ae3(&self) -> AE3_R`[src]

Bit 3 - Acknowledge Error 3

`pub fn ae4(&self) -> AE4_R`[src]

Bit 4 - Acknowledge Error 4

`pub fn ae5(&self) -> AE5_R`[src]

Bit 5 - Acknowledge Error 5

`pub fn ae6(&self) -> AE6_R`[src]

Bit 6 - Acknowledge Error 6

`pub fn ae7(&self) -> AE7_R`[src]

Bit 7 - Acknowledge Error 7

`pub fn ae8(&self) -> AE8_R`[src]

Bit 8 - Acknowledge Error 8

`pub fn ae9(&self) -> AE9_R`[src]

Bit 9 - Acknowledge Error 9

`pub fn ae10(&self) -> AE10_R`[src]

Bit 10 - Acknowledge Error 10

`pub fn ae11(&self) -> AE11_R`[src]

Bit 11 - Acknowledge Error 11

`pub fn ae12(&self) -> AE12_R`[src]

Bit 12 - Acknowledge Error 12

`pub fn ae13(&self) -> AE13_R`[src]

Bit 13 - Acknowledge Error 13

`pub fn ae14(&self) -> AE14_R`[src]

Bit 14 - Acknowledge Error 14

`pub fn ae15(&self) -> AE15_R`[src]

Bit 15 - Acknowledge Error 15

`pub fn pe0(&self) -> PE0_R`[src]

Bit 16 - PHY Error 0

`pub fn pe1(&self) -> PE1_R`[src]

Bit 17 - PHY Error 1

`pub fn pe2(&self) -> PE2_R`[src]

Bit 18 - PHY Error 2

`pub fn pe3(&self) -> PE3_R`[src]

Bit 19 - PHY Error 3

`pub fn pe4(&self) -> PE4_R`[src]

Bit 20 - PHY Error 4

`impl R<u32, Reg<u32, _DSI_ISR1>>`[src]

`pub fn tohstx(&self) -> TOHSTX_R`[src]

Bit 0 - Timeout High-Speed Transmission

`pub fn tolprx(&self) -> TOLPRX_R`[src]

Bit 1 - Timeout Low-Power Reception

`pub fn eccse(&self) -> ECCSE_R`[src]

Bit 2 - ECC Single-bit Error

`pub fn eccme(&self) -> ECCME_R`[src]

Bit 3 - ECC Multi-bit Error

`pub fn crce(&self) -> CRCE_R`[src]

Bit 4 - CRC Error

`pub fn pse(&self) -> PSE_R`[src]

Bit 5 - Packet Size Error

`pub fn eotpe(&self) -> EOTPE_R`[src]

Bit 6 - EoTp Error

`pub fn lpwre(&self) -> LPWRE_R`[src]

Bit 7 - LTDC Payload Write Error

`pub fn gcwre(&self) -> GCWRE_R`[src]

Bit 8 - Generic Command Write Error

`pub fn gpwre(&self) -> GPWRE_R`[src]

Bit 9 - Generic Payload Write Error

`pub fn gptxe(&self) -> GPTXE_R`[src]

Bit 10 - Generic Payload Transmit Error

`pub fn gprde(&self) -> GPRDE_R`[src]

Bit 11 - Generic Payload Read Error

`pub fn gprxe(&self) -> GPRXE_R`[src]

Bit 12 - Generic Payload Receive Error

`impl R<u32, Reg<u32, _DSI_IER0>>`[src]

`pub fn ae0ie(&self) -> AE0IE_R`[src]

Bit 0 - Acknowledge Error 0 Interrupt Enable

`pub fn ae1ie(&self) -> AE1IE_R`[src]

Bit 1 - Acknowledge Error 1 Interrupt Enable

`pub fn ae2ie(&self) -> AE2IE_R`[src]

Bit 2 - Acknowledge Error 2 Interrupt Enable

`pub fn ae3ie(&self) -> AE3IE_R`[src]

Bit 3 - Acknowledge Error 3 Interrupt Enable

`pub fn ae4ie(&self) -> AE4IE_R`[src]

Bit 4 - Acknowledge Error 4 Interrupt Enable

`pub fn ae5ie(&self) -> AE5IE_R`[src]

Bit 5 - Acknowledge Error 5 Interrupt Enable

`pub fn ae6ie(&self) -> AE6IE_R`[src]

Bit 6 - Acknowledge Error 6 Interrupt Enable

`pub fn ae7ie(&self) -> AE7IE_R`[src]

Bit 7 - Acknowledge Error 7 Interrupt Enable

`pub fn ae8ie(&self) -> AE8IE_R`[src]

Bit 8 - Acknowledge Error 8 Interrupt Enable

`pub fn ae9ie(&self) -> AE9IE_R`[src]

Bit 9 - Acknowledge Error 9 Interrupt Enable

`pub fn ae10ie(&self) -> AE10IE_R`[src]

Bit 10 - Acknowledge Error 10 Interrupt Enable

`pub fn ae11ie(&self) -> AE11IE_R`[src]

Bit 11 - Acknowledge Error 11 Interrupt Enable

`pub fn ae12ie(&self) -> AE12IE_R`[src]

Bit 12 - Acknowledge Error 12 Interrupt Enable

`pub fn ae13ie(&self) -> AE13IE_R`[src]

Bit 13 - Acknowledge Error 13 Interrupt Enable

`pub fn ae14ie(&self) -> AE14IE_R`[src]

Bit 14 - Acknowledge Error 14 Interrupt Enable

`pub fn ae15ie(&self) -> AE15IE_R`[src]

Bit 15 - Acknowledge Error 15 Interrupt Enable

`pub fn pe0ie(&self) -> PE0IE_R`[src]

Bit 16 - PHY Error 0 Interrupt Enable

`pub fn pe1ie(&self) -> PE1IE_R`[src]

Bit 17 - PHY Error 1 Interrupt Enable

`pub fn pe2ie(&self) -> PE2IE_R`[src]

Bit 18 - PHY Error 2 Interrupt Enable

`pub fn pe3ie(&self) -> PE3IE_R`[src]

Bit 19 - PHY Error 3 Interrupt Enable

`pub fn pe4ie(&self) -> PE4IE_R`[src]

Bit 20 - PHY Error 4 Interrupt Enable

`impl R<u32, Reg<u32, _DSI_IER1>>`[src]

`pub fn tohstxie(&self) -> TOHSTXIE_R`[src]

Bit 0 - Timeout High-Speed Transmission Interrupt Enable

`pub fn tolprxie(&self) -> TOLPRXIE_R`[src]

Bit 1 - Timeout Low-Power Reception Interrupt Enable

`pub fn eccseie(&self) -> ECCSEIE_R`[src]

Bit 2 - ECC Single-bit Error Interrupt Enable

`pub fn eccmeie(&self) -> ECCMEIE_R`[src]

Bit 3 - ECC Multi-bit Error Interrupt Enable

`pub fn crceie(&self) -> CRCEIE_R`[src]

Bit 4 - CRC Error Interrupt Enable

`pub fn pseie(&self) -> PSEIE_R`[src]

Bit 5 - Packet Size Error Interrupt Enable

`pub fn eotpeie(&self) -> EOTPEIE_R`[src]

Bit 6 - EoTp Error Interrupt Enable

`pub fn lpwreie(&self) -> LPWREIE_R`[src]

Bit 7 - LTDC Payload Write Error Interrupt Enable

`pub fn gcwreie(&self) -> GCWREIE_R`[src]

Bit 8 - Generic Command Write Error Interrupt Enable

`pub fn gpwreie(&self) -> GPWREIE_R`[src]

Bit 9 - Generic Payload Write Error Interrupt Enable

`pub fn gptxeie(&self) -> GPTXEIE_R`[src]

Bit 10 - Generic Payload Transmit Error Interrupt Enable

`pub fn gprdeie(&self) -> GPRDEIE_R`[src]

Bit 11 - Generic Payload Read Error Interrupt Enable

`pub fn gprxeie(&self) -> GPRXEIE_R`[src]

Bit 12 - Generic Payload Receive Error Interrupt Enable

`impl R<u32, Reg<u32, _DSI_VSCR>>`[src]

`pub fn en(&self) -> EN_R`[src]

Bit 0 - Enable

`pub fn ur(&self) -> UR_R`[src]

Bit 8 - Update Register

`impl R<u32, Reg<u32, _DSI_LCVCIDR>>`[src]

`pub fn vcid(&self) -> VCID_R`[src]

Bits 0:1 - Virtual Channel ID

`impl R<u32, Reg<u32, _DSI_LCCCR>>`[src]

`pub fn colc(&self) -> COLC_R`[src]

Bits 0:3 - Color Coding

`pub fn lpe(&self) -> LPE_R`[src]

Bit 8 - Loosely Packed Enable

`impl R<u32, Reg<u32, _DSI_LPMCCR>>`[src]

`pub fn vlpsize(&self) -> VLPSIZE_R`[src]

Bits 0:7 - VACT Largest Packet Size

`pub fn lpsize(&self) -> LPSIZE_R`[src]

Bits 16:23 - Largest Packet Size

`impl R<u32, Reg<u32, _DSI_VMCCR>>`[src]

`pub fn vmt(&self) -> VMT_R`[src]

Bits 0:1 - Video mode Type

`pub fn lpvsae(&self) -> LPVSAE_R`[src]

Bit 2 - Low-Power Vertical Sync time Enable

`pub fn lpvbpe(&self) -> LPVBPE_R`[src]

Bit 3 - Low-power Vertical Back-Porch Enable

`pub fn lpvfpe(&self) -> LPVFPE_R`[src]

Bit 4 - Low-power Vertical Front-Porch Enable

`pub fn lpvae(&self) -> LPVAE_R`[src]

Bit 5 - Low-Power Vertical Active Enable

`pub fn lphbpe(&self) -> LPHBPE_R`[src]

Bit 6 - Low-power Horizontal Back-Porch Enable

`pub fn lphfe(&self) -> LPHFE_R`[src]

Bit 7 - Low-Power Horizontal Front-Porch Enable

`pub fn fbtaae(&self) -> FBTAAE_R`[src]

Bit 8 - Frame BTA Acknowledge Enable

`pub fn lpce(&self) -> LPCE_R`[src]

Bit 9 - Low-Power Command Enable

`impl R<u32, Reg<u32, _DSI_VPCCR>>`[src]

`pub fn vpsize(&self) -> VPSIZE_R`[src]

Bits 0:13 - Video Packet Size

`impl R<u32, Reg<u32, _DSI_VCCCR>>`[src]

`pub fn numc(&self) -> NUMC_R`[src]

Bits 0:12 - Number of Chunks

`impl R<u32, Reg<u32, _DSI_VNPCCR>>`[src]

`pub fn npsize(&self) -> NPSIZE_R`[src]

Bits 0:12 - Null Packet Size

`impl R<u32, Reg<u32, _DSI_VHSACCR>>`[src]

`pub fn hsa(&self) -> HSA_R`[src]

Bits 0:11 - Horizontal Synchronism Active duration

`impl R<u32, Reg<u32, _DSI_VHBPCCR>>`[src]

`pub fn hbp(&self) -> HBP_R`[src]

Bits 0:11 - Horizontal Back-Porch duration

`impl R<u32, Reg<u32, _DSI_VLCCR>>`[src]

`pub fn hline(&self) -> HLINE_R`[src]

Bits 0:14 - Horizontal Line duration

`impl R<u32, Reg<u32, _DSI_VVSACCR>>`[src]

`pub fn vsa(&self) -> VSA_R`[src]

Bits 0:9 - Vertical Synchronism Active duration

`impl R<u32, Reg<u32, _DSI_VVBPCCR>>`[src]

`pub fn vbp(&self) -> VBP_R`[src]

Bits 0:9 - Vertical Back-Porch duration

`impl R<u32, Reg<u32, _DSI_VVFPCCR>>`[src]

`pub fn vfp(&self) -> VFP_R`[src]

Bits 0:9 - Vertical Front-Porch duration

`impl R<u32, Reg<u32, _DSI_VVACCR>>`[src]

`pub fn va(&self) -> VA_R`[src]

Bits 0:13 - Vertical Active duration

`impl R<u32, Reg<u32, _DSI_WCFGR>>`[src]

`pub fn vspol(&self) -> VSPOL_R`[src]

Bit 7 - VSync Polarity

`pub fn ar(&self) -> AR_R`[src]

Bit 6 - Automatic Refresh

`pub fn tepol(&self) -> TEPOL_R`[src]

Bit 5 - TE Polarity

`pub fn tesrc(&self) -> TESRC_R`[src]

Bit 4 - TE Source

`pub fn colmux(&self) -> COLMUX_R`[src]

Bits 1:3 - Color Multiplexing

`pub fn dsim(&self) -> DSIM_R`[src]

Bit 0 - DSI Mode

`impl R<u32, Reg<u32, _DSI_WCR>>`[src]

`pub fn dsien(&self) -> DSIEN_R`[src]

Bit 3 - DSI Enable

`pub fn ltdcen(&self) -> LTDCEN_R`[src]

Bit 2 - LTDC Enable

`pub fn shtdn(&self) -> SHTDN_R`[src]

Bit 1 - Shutdown

`pub fn colm(&self) -> COLM_R`[src]

Bit 0 - Color Mode

`impl R<u32, Reg<u32, _DSI_WIER>>`[src]

`pub fn rrie(&self) -> RRIE_R`[src]

Bit 13 - Regulator Ready Interrupt Enable

`pub fn plluie(&self) -> PLLUIE_R`[src]

Bit 10 - PLL Unlock Interrupt Enable

`pub fn plllie(&self) -> PLLLIE_R`[src]

Bit 9 - PLL Lock Interrupt Enable

`pub fn erie(&self) -> ERIE_R`[src]

Bit 1 - End of Refresh Interrupt Enable

`pub fn teie(&self) -> TEIE_R`[src]

Bit 0 - Tearing Effect Interrupt Enable

`impl R<u32, Reg<u32, _DSI_WISR>>`[src]

`pub fn rrif(&self) -> RRIF_R`[src]

Bit 13 - Regulator Ready Interrupt Flag

`pub fn rrs(&self) -> RRS_R`[src]

Bit 12 - Regulator Ready Status

`pub fn plluif(&self) -> PLLUIF_R`[src]

Bit 10 - PLL Unlock Interrupt Flag

`pub fn plllif(&self) -> PLLLIF_R`[src]

Bit 9 - PLL Lock Interrupt Flag

`pub fn pllls(&self) -> PLLLS_R`[src]

Bit 8 - PLL Lock Status

`pub fn busy(&self) -> BUSY_R`[src]

Bit 2 - Busy Flag

`pub fn erif(&self) -> ERIF_R`[src]

Bit 1 - End of Refresh Interrupt Flag

`pub fn teif(&self) -> TEIF_R`[src]

Bit 0 - Tearing Effect Interrupt Flag

`impl R<u32, Reg<u32, _DSI_WIFCR>>`[src]

`pub fn crrif(&self) -> CRRIF_R`[src]

Bit 13 - Clear Regulator Ready Interrupt Flag

`pub fn cplluif(&self) -> CPLLUIF_R`[src]

Bit 10 - Clear PLL Unlock Interrupt Flag

`pub fn cplllif(&self) -> CPLLLIF_R`[src]

Bit 9 - Clear PLL Lock Interrupt Flag

`pub fn cerif(&self) -> CERIF_R`[src]

Bit 1 - Clear End of Refresh Interrupt Flag

`pub fn cteif(&self) -> CTEIF_R`[src]

Bit 0 - Clear Tearing Effect Interrupt Flag

`impl R<u32, Reg<u32, _DSI_WPCR1>>`[src]

`pub fn tclkposten(&self) -> TCLKPOSTEN_R`[src]

Bit 27 - custom time for tCLK-POST Enable

`pub fn tlpxcen(&self) -> TLPXCEN_R`[src]

Bit 26 - custom time for tLPX for Clock lane Enable

`pub fn thsexiten(&self) -> THSEXITEN_R`[src]

Bit 25 - custom time for tHS-EXIT Enable

`pub fn tlpxden(&self) -> TLPXDEN_R`[src]

Bit 24 - custom time for tLPX for Data lanes Enable

`pub fn thszeroen(&self) -> THSZEROEN_R`[src]

Bit 23 - custom time for tHS-ZERO Enable

`pub fn thstrailen(&self) -> THSTRAILEN_R`[src]

Bit 22 - custom time for tHS-TRAIL Enable

`pub fn thsprepen(&self) -> THSPREPEN_R`[src]

Bit 21 - custom time for tHS-PREPARE Enable

`pub fn tclkzeroen(&self) -> TCLKZEROEN_R`[src]

Bit 20 - custom time for tCLK-ZERO Enable

`pub fn tclkprepen(&self) -> TCLKPREPEN_R`[src]

Bit 19 - custom time for tCLK-PREPARE Enable

`pub fn pden(&self) -> PDEN_R`[src]

Bit 18 - Pull-Down Enable

`pub fn tddl(&self) -> TDDL_R`[src]

Bit 16 - Turn Disable Data Lanes

`pub fn cdoffdl(&self) -> CDOFFDL_R`[src]

Bit 14 - Contention Detection OFF on Data Lanes

`pub fn ftxsmdl(&self) -> FTXSMDL_R`[src]

Bit 13 - Force in TX Stop Mode the Data Lanes

`pub fn ftxsmcl(&self) -> FTXSMCL_R`[src]

Bit 12 - Force in TX Stop Mode the Clock Lane

`pub fn hsidl1(&self) -> HSIDL1_R`[src]

Bit 11 - Invert the High-Speed data signal on Data Lane 1

`pub fn hsidl0(&self) -> HSIDL0_R`[src]

Bit 10 - Invert the Hight-Speed data signal on Data Lane 0

`pub fn hsicl(&self) -> HSICL_R`[src]

Bit 9 - Invert Hight-Speed data signal on Clock Lane

`pub fn swdl1(&self) -> SWDL1_R`[src]

Bit 8 - Swap Data Lane 1 pins

`pub fn swdl0(&self) -> SWDL0_R`[src]

Bit 7 - Swap Data Lane 0 pins

`pub fn swcl(&self) -> SWCL_R`[src]

Bit 6 - Swap Clock Lane pins

`pub fn uix4(&self) -> UIX4_R`[src]

Bits 0:5 - Unit Interval multiplied by 4

`impl R<u32, Reg<u32, _DSI_WPCR2>>`[src]

`pub fn lprxft(&self) -> LPRXFT_R`[src]

Bits 25:26 - Low-Power RX low-pass Filtering Tuning

`pub fn flprxlpm(&self) -> FLPRXLPM_R`[src]

Bit 22 - Forces LP Receiver in Low-Power Mode

`pub fn hstxsrcdl(&self) -> HSTXSRCDL_R`[src]

Bits 18:19 - High-Speed Transmission Slew Rate Control on Data Lanes

`pub fn hstxsrccl(&self) -> HSTXSRCCL_R`[src]

Bits 16:17 - High-Speed Transmission Slew Rate Control on Clock Lane

`pub fn sdcc(&self) -> SDCC_R`[src]

Bit 12 - SDD Control

`pub fn lpsrdl(&self) -> LPSRDL_R`[src]

Bits 8:9 - Low-Power transmission Slew Rate Compensation on Data Lanes

`pub fn lpsrcl(&self) -> LPSRCL_R`[src]

Bits 6:7 - Low-Power transmission Slew Rate Compensation on Clock Lane

`pub fn hstxdll(&self) -> HSTXDLL_R`[src]

Bits 2:3 - High-Speed Transmission Delay on Data Lanes

`pub fn hstxdcl(&self) -> HSTXDCL_R`[src]

Bits 0:1 - High-Speed Transmission Delay on Clock Lane

`impl R<u32, Reg<u32, _DSI_WPCR3>>`[src]

`pub fn thstrail(&self) -> THSTRAIL_R`[src]

Bits 24:31 - tHSTRAIL

`pub fn thsprep(&self) -> THSPREP_R`[src]

Bits 16:23 - tHS-PREPARE

`pub fn tclkzeo(&self) -> TCLKZEO_R`[src]

Bits 8:15 - tCLK-ZERO

`pub fn tclkprep(&self) -> TCLKPREP_R`[src]

Bits 0:7 - tCLK-PREPARE

`impl R<u32, Reg<u32, _DSI_WPCR4>>`[src]

`pub fn tlpxc(&self) -> TLPXC_R`[src]

Bits 24:31 - tLPXC for Clock lane

`pub fn thsexit(&self) -> THSEXIT_R`[src]

Bits 16:23 - tHSEXIT

`pub fn tlpxd(&self) -> TLPXD_R`[src]

Bits 8:15 - tLPX for Data lanes

`pub fn thszero(&self) -> THSZERO_R`[src]

Bits 0:7 - tHS-ZERO

`impl R<u32, Reg<u32, _DSI_WPCR5>>`[src]

`pub fn thszero(&self) -> THSZERO_R`[src]

Bits 0:7 - tCLK-POST

`impl R<u32, Reg<u32, _DSI_WRPCR>>`[src]

`pub fn regen(&self) -> REGEN_R`[src]

Bit 24 - Regulator Enable

`pub fn odf(&self) -> ODF_R`[src]

Bits 16:17 - PLL Output Division Factor

`pub fn idf(&self) -> IDF_R`[src]

Bits 11:14 - PLL Input Division Factor

`pub fn ndiv(&self) -> NDIV_R`[src]

Bits 2:8 - PLL Loop Division Factor

`pub fn pllen(&self) -> PLLEN_R`[src]

Bit 0 - PLL Enable

`impl R<u32, Reg<u32, _CSR>>`[src]

`pub fn enable(&self) -> ENABLE_R`[src]

Bit 0 - Counter enable

`pub fn tickint(&self) -> TICKINT_R`[src]

Bit 1 - SysTick exception request enable

`pub fn clksource(&self) -> CLKSOURCE_R`[src]

Bit 2 - Clock source selection

`pub fn countflag(&self) -> COUNTFLAG_R`[src]

Bit 16 - COUNTFLAG

`impl R<u32, Reg<u32, _RVR>>`[src]

`pub fn reload(&self) -> RELOAD_R`[src]

Bits 0:23 - RELOAD value

`impl R<u32, Reg<u32, _CVR>>`[src]

`pub fn current(&self) -> CURRENT_R`[src]

Bits 0:23 - Current counter value

`impl R<u32, Reg<u32, _CALIB>>`[src]

`pub fn tenms(&self) -> TENMS_R`[src]

Bits 0:23 - Calibration value

`pub fn skew(&self) -> SKEW_R`[src]

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

`pub fn noref(&self) -> NOREF_R`[src]

Bit 31 - NOREF flag. Reads as zero

`impl R<u32, Reg<u32, _STIR>>`[src]

`pub fn intid(&self) -> INTID_R`[src]

Bits 0:8 - Software generated interrupt ID

`impl R<u32, Reg<u32, _CPACR>>`[src]

`pub fn cp(&self) -> CP_R`[src]

Bits 20:23 - CP

`impl R<u32, Reg<u32, _ACTRL>>`[src]

`pub fn disfold(&self) -> DISFOLD_R`[src]

Bit 2 - DISFOLD

`pub fn fpexcodis(&self) -> FPEXCODIS_R`[src]

Bit 10 - FPEXCODIS

`pub fn disramode(&self) -> DISRAMODE_R`[src]

Bit 11 - DISRAMODE

`pub fn disitmatbflush(&self) -> DISITMATBFLUSH_R`[src]

Bit 12 - DISITMATBFLUSH

`impl R<u32, Reg<u32, _CLIDR>>`[src]

`pub fn cl1(&self) -> CL1_R`[src]

Bits 0:2 - CL1

`pub fn cl2(&self) -> CL2_R`[src]

Bits 3:5 - CL2

`pub fn cl3(&self) -> CL3_R`[src]

Bits 6:8 - CL3

`pub fn cl4(&self) -> CL4_R`[src]

Bits 9:11 - CL4

`pub fn cl5(&self) -> CL5_R`[src]

Bits 12:14 - CL5

`pub fn cl6(&self) -> CL6_R`[src]

Bits 15:17 - CL6

`pub fn cl7(&self) -> CL7_R`[src]

Bits 18:20 - CL7

`pub fn lo_uis(&self) -> LOUIS_R`[src]

Bits 21:23 - LoUIS

`pub fn lo_c(&self) -> LOC_R`[src]

Bits 24:26 - LoC

`pub fn lo_u(&self) -> LOU_R`[src]

Bits 27:29 - LoU

`impl R<u32, Reg<u32, _CTR>>`[src]

`pub fn _imin_line(&self) -> _IMINLINE_R`[src]

Bits 0:3 - IminLine

`pub fn dmin_line(&self) -> DMINLINE_R`[src]

Bits 16:19 - DMinLine

`pub fn erg(&self) -> ERG_R`[src]

Bits 20:23 - ERG

`pub fn cwg(&self) -> CWG_R`[src]

Bits 24:27 - CWG

`pub fn format(&self) -> FORMAT_R`[src]

Bits 29:31 - Format

`impl R<u32, Reg<u32, _CCSIDR>>`[src]

`pub fn line_size(&self) -> LINESIZE_R`[src]

Bits 0:2 - LineSize

`pub fn associativity(&self) -> ASSOCIATIVITY_R`[src]

Bits 3:12 - Associativity

`pub fn num_sets(&self) -> NUMSETS_R`[src]

Bits 13:27 - NumSets

`pub fn wa(&self) -> WA_R`[src]

Bit 28 - WA

`pub fn ra(&self) -> RA_R`[src]

Bit 29 - RA

`pub fn wb(&self) -> WB_R`[src]

Bit 30 - WB

`pub fn wt(&self) -> WT_R`[src]

Bit 31 - WT

`impl R<u32, Reg<u32, _ITCMCR>>`[src]

`pub fn en(&self) -> EN_R`[src]

Bit 0 - EN

`pub fn rmw(&self) -> RMW_R`[src]

Bit 1 - RMW

`pub fn reten(&self) -> RETEN_R`[src]

Bit 2 - RETEN

`pub fn sz(&self) -> SZ_R`[src]

Bits 3:6 - SZ

`impl R<u32, Reg<u32, _DTCMCR>>`[src]

`pub fn en(&self) -> EN_R`[src]

Bit 0 - EN

`pub fn rmw(&self) -> RMW_R`[src]

Bit 1 - RMW

`pub fn reten(&self) -> RETEN_R`[src]

Bit 2 - RETEN

`pub fn sz(&self) -> SZ_R`[src]

Bits 3:6 - SZ

`impl R<u32, Reg<u32, _AHBPCR>>`[src]

`pub fn en(&self) -> EN_R`[src]

Bit 0 - EN

`pub fn sz(&self) -> SZ_R`[src]

Bits 1:3 - SZ

`impl R<u32, Reg<u32, _CACR>>`[src]

`pub fn siwt(&self) -> SIWT_R`[src]

Bit 0 - SIWT

`pub fn eccen(&self) -> ECCEN_R`[src]

Bit 1 - ECCEN

`pub fn forcewt(&self) -> FORCEWT_R`[src]

Bit 2 - FORCEWT

`impl R<u32, Reg<u32, _AHBSCR>>`[src]

`pub fn ctl(&self) -> CTL_R`[src]

Bits 0:1 - CTL

`pub fn tpri(&self) -> TPRI_R`[src]

Bits 2:10 - TPRI

`pub fn initcount(&self) -> INITCOUNT_R`[src]

Bits 11:15 - INITCOUNT

`impl R<u32, Reg<u32, _ABFSR>>`[src]

`pub fn itcm(&self) -> ITCM_R`[src]

Bit 0 - ITCM

`pub fn dtcm(&self) -> DTCM_R`[src]

Bit 1 - DTCM

`pub fn ahbp(&self) -> AHBP_R`[src]

`pub fn jeoc3(&self) -> JEOC3_R`[src]

Bit 18 - Injected channel end of conversion of ADC3

`pub fn eoc3(&self) -> EOC3_R`[src]

Bit 17 - End of conversion of ADC3

`pub fn awd3(&self) -> AWD3_R`[src]

Bit 16 - Analog watchdog flag of ADC3

`pub fn ovr2(&self) -> OVR2_R`[src]

Bit 13 - Overrun flag of ADC2

`pub fn strt2(&self) -> STRT2_R`[src]

Bit 12 - Regular channel Start flag of ADC2

`pub fn jstrt2(&self) -> JSTRT2_R`[src]

Bit 11 - Injected channel Start flag of ADC2

`pub fn jeoc2(&self) -> JEOC2_R`[src]

Bit 10 - Injected channel end of conversion of ADC2

`pub fn eoc2(&self) -> EOC2_R`[src]

Bit 9 - End of conversion of ADC2

`pub fn awd2(&self) -> AWD2_R`[src]

Bit 8 - Analog watchdog flag of ADC2

`pub fn ovr1(&self) -> OVR1_R`[src]

Bit 5 - Overrun flag of ADC1

`pub fn strt1(&self) -> STRT1_R`[src]

Bit 4 - Regular channel Start flag of ADC1

`pub fn jstrt1(&self) -> JSTRT1_R`[src]

Bit 3 - Injected channel Start flag of ADC1

`pub fn jeoc1(&self) -> JEOC1_R`[src]

Bit 2 - Injected channel end of conversion of ADC1

`pub fn eoc1(&self) -> EOC1_R`[src]

Bit 1 - End of conversion of ADC1

`pub fn awd1(&self) -> AWD1_R`[src]

Bit 0 - Analog watchdog flag of ADC1

`impl R<bool, TSVREFE_A>`[src]

`pub fn variant(&self) -> TSVREFE_A`[src]

Get enumerated values variant

`pub fn is_disabled(&self) -> bool`[src]

Checks if the value of the field is DISABLED

`pub fn is_enabled(&self) -> bool`[src]

Checks if the value of the field is ENABLED

Checks if the value of the field is SINGLE

`pub fn is_continuous(&self) -> bool`[src]

Checks if the value of the field is CONTINUOUS

`impl R<u8, MULTI_A>`[src]

`pub fn variant(&self) -> Variant<u8, MULTI_A>`[src]

Get enumerated values variant

`pub fn is_independent(&self) -> bool`[src]

Checks if the value of the field is INDEPENDENT

`pub fn is_dual_rj(&self) -> bool`[src]

Checks if the value of the field is DUALRJ

`pub fn is_dual_ra(&self) -> bool`[src]

Checks if the value of the field is DUALRA

`pub fn is_dual_j(&self) -> bool`[src]

Checks if the value of the field is DUALJ

`pub fn is_dual_r(&self) -> bool`[src]

Checks if the value of the field is DUALR

`pub fn is_dual_i(&self) -> bool`[src]

Checks if the value of the field is DUALI

`pub fn is_dual_a(&self) -> bool`[src]

Checks if the value of the field is DUALA

`pub fn is_triple_rj(&self) -> bool`[src]

Checks if the value of the field is TRIPLERJ

`pub fn is_triple_ra(&self) -> bool`[src]

Checks if the value of the field is TRIPLERA

`pub fn is_triple_j(&self) -> bool`[src]

Checks if the value of the field is TRIPLEJ

`pub fn is_triple_r(&self) -> bool`[src]

Checks if the value of the field is TRIPLER

`pub fn is_triple_i(&self) -> bool`[src]

Checks if the value of the field is TRIPLEI

`pub fn is_triple_a(&self) -> bool`[src]

Checks if the value of the field is TRIPLEA

`impl R<u32, Reg<u32, _CCR>>`[src]

`pub fn tsvrefe(&self) -> TSVREFE_R`[src]

Bit 23 - Temperature sensor and V_REFINT enable

`pub fn vbate(&self) -> VBATE_R`[src]

Bit 22 - V_BAT enable

`pub fn adcpre(&self) -> ADCPRE_R`[src]

Bits 16:17 - ADC prescaler

`pub fn dma(&self) -> DMA_R`[src]

Bits 14:15 - Direct memory access mode for multi ADC mode

`pub fn dds(&self) -> DDS_R`[src]

Bit 13 - DMA disable selection (for multi-ADC mode)

`pub fn delay(&self) -> DELAY_R`[src]

Bits 8:11 - Delay between 2 sampling phases

`pub fn multi(&self) -> MULTI_R`[src]

Bits 0:3 - Multi ADC mode selection

`impl R<u32, Reg<u32, _CDR>>`[src]

`pub fn data2(&self) -> DATA2_R`[src]

Bits 16:31 - 2nd data item of a pair of regular conversions

`pub fn data1(&self) -> DATA1_R`[src]

Bits 0:15 - 1st data item of a pair of regular conversions

`impl R<u32, Reg<u32, _IDCODE>>`[src]

`pub fn dev_id(&self) -> DEV_ID_R`[src]

Bits 0:11 - DEV_ID

`pub fn rev_id(&self) -> REV_ID_R`[src]

Bits 16:31 - REV_ID

`impl R<u32, Reg<u32, _CR>>`[src]

`pub fn dbg_sleep(&self) -> DBG_SLEEP_R`[src]

Bit 0 - DBG_SLEEP

`pub fn dbg_stop(&self) -> DBG_STOP_R`[src]

Bit 1 - DBG_STOP

`pub fn dbg_standby(&self) -> DBG_STANDBY_R`[src]

Bit 2 - DBG_STANDBY

`pub fn trace_ioen(&self) -> TRACE_IOEN_R`[src]

Bit 5 - TRACE_IOEN

`pub fn trace_mode(&self) -> TRACE_MODE_R`[src]

Bits 6:7 - TRACE_MODE

`impl R<u32, Reg<u32, _APB1_FZ>>`[src]

`pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R`[src]

Bit 0 - DBG_TIM2_STOP

`pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R`[src]

Bit 1 - DBG_TIM3_STOP

`pub fn dbg_tim4_stop(&self) -> DBG_TIM4_STOP_R`[src]

Bit 2 - DBG_TIM4_STOP

`pub fn dbg_tim5_stop(&self) -> DBG_TIM5_STOP_R`[src]

Bit 3 - DBG_TIM5_STOP

`pub fn dbg_tim6_stop(&self) -> DBG_TIM6_STOP_R`[src]

Bit 4 - DBG_TIM6_STOP

`pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R`[src]

Bit 5 - DBG_TIM7_STOP

`pub fn dbg_tim12_stop(&self) -> DBG_TIM12_STOP_R`[src]

Bit 6 - DBG_TIM12_STOP

`pub fn dbg_tim13_stop(&self) -> DBG_TIM13_STOP_R`[src]

Bit 7 - DBG_TIM13_STOP

`pub fn dbg_tim14_stop(&self) -> DBG_TIM14_STOP_R`[src]

Bit 8 - DBG_TIM14_STOP

`pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R`[src]

Bit 9 - DBG_LPTIM1_STOP

`pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R`[src]

Bit 10 - DBG_RTC_STOP

`pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R`[src]

Bit 11 - DBG_WWDG_STOP

`pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R`[src]

Bit 12 - DBG_IWDG_STOP

`pub fn dbg_can3_stop(&self) -> DBG_CAN3_STOP_R`[src]

Bit 13 - DBG_CAN3_STOP

`pub fn dbg_i2c1_smbus_timeout(&self) -> DBG_I2C1_SMBUS_TIMEOUT_R`[src]

Bit 21 - DBG_I2C1_SMBUS_TIMEOUT

`pub fn dbg_i2c2_smbus_timeout(&self) -> DBG_I2C2_SMBUS_TIMEOUT_R`[src]

Bit 22 - DBG_I2C2_SMBUS_TIMEOUT

`pub fn dbg_i2c3_smbus_timeout(&self) -> DBG_I2C3_SMBUS_TIMEOUT_R`[src]

Bit 23 - DBG_I2C3_SMBUS_TIMEOUT

`pub fn dbg_i2c4_smbus_timeout(&self) -> DBG_I2C4_SMBUS_TIMEOUT_R`[src]

Bit 24 - DBG_I2C4SMBUS_TIMEOUT

`pub fn dbg_can1_stop(&self) -> DBG_CAN1_STOP_R`[src]

Bit 25 - DBG_CAN1_STOP

`pub fn dbg_can2_stop(&self) -> DBG_CAN2_STOP_R`[src]

Bit 26 - DBG_CAN2_STOP

`impl R<u32, Reg<u32, _APB2_FZ>>`[src]

`pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R`[src]

Bit 0 - TIM1 counter stopped when core is halted

`pub fn dbg_tim8_stop(&self) -> DBG_TIM8_STOP_R`[src]

Bit 1 - TIM8 counter stopped when core is halted

`pub fn dbg_tim9_stop(&self) -> DBG_TIM9_STOP_R`[src]

Bit 16 - TIM9 counter stopped when core is halted

`pub fn dbg_tim10_stop(&self) -> DBG_TIM10_STOP_R`[src]

Bit 17 - TIM10 counter stopped when core is halted

`pub fn dbg_tim11_stop(&self) -> DBG_TIM11_STOP_R`[src]

Bit 18 - TIM11 counter stopped when core is halted

Trait Implementations

`impl<U, T, FI> PartialEq<FI> for R<U, T> where U: PartialEq, FI: Copy + Into,` [src]

`fn eq(&self, other: &FI) -> bool`[src]

`#[must_use]fn ne(&self, other: &Rhs) -> bool`1.0.0[src]

Auto Trait Implementations

`impl<U, T> Send for R<U, T> where T: Send, U: Send,`

`impl<U, T> Sync for R<U, T> where T: Sync, U: Sync,`

`impl<U, T> Unpin for R<U, T> where T: Unpin, U: Unpin,`

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T> Same<T> for T`

`type Output = T`

Should always be Self

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Struct stm32f7::R

Methods

impl<U, T> R<U, T> where U: Copy, [src]

pub fn bits(&self) -> U[src]

impl<FI> R<bool, FI>[src]

pub fn bit(&self) -> bool[src]

pub fn bit_is_clear(&self) -> bool[src]

pub fn bit_is_set(&self) -> bool[src]

impl R<u8, CKD_A>[src]

pub fn variant(&self) -> Variant<u8, CKD_A>[src]

pub fn is_div1(&self) -> bool[src]

pub fn is_div2(&self) -> bool[src]

pub fn is_div4(&self) -> bool[src]

impl R<bool, ARPE_A>[src]

pub fn variant(&self) -> ARPE_A[src]

pub fn is_disabled(&self) -> bool[src]

pub fn is_enabled(&self) -> bool[src]

impl R<u8, CMS_A>[src]

pub fn variant(&self) -> CMS_A[src]

pub fn is_edge_aligned(&self) -> bool[src]

pub fn is_center_aligned1(&self) -> bool[src]

pub fn is_center_aligned2(&self) -> bool[src]

pub fn is_center_aligned3(&self) -> bool[src]

impl R<bool, DIR_A>[src]

pub fn variant(&self) -> DIR_A[src]

pub fn is_up(&self) -> bool[src]

pub fn is_down(&self) -> bool[src]

impl R<bool, OPM_A>[src]

pub fn variant(&self) -> OPM_A[src]

pub fn is_disabled(&self) -> bool[src]

pub fn is_enabled(&self) -> bool[src]

impl R<bool, URS_A>[src]

pub fn variant(&self) -> URS_A[src]

pub fn is_any_event(&self) -> bool[src]

pub fn is_counter_only(&self) -> bool[src]

impl R<bool, UDIS_A>[src]

pub fn variant(&self) -> UDIS_A[src]

pub fn is_enabled(&self) -> bool[src]

pub fn is_disabled(&self) -> bool[src]

impl R<bool, CEN_A>[src]

pub fn variant(&self) -> CEN_A[src]

pub fn is_disabled(&self) -> bool[src]

pub fn is_enabled(&self) -> bool[src]

impl R<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&self) -> CKD_R[src]

pub fn arpe(&self) -> ARPE_R[src]

pub fn cms(&self) -> CMS_R[src]

pub fn dir(&self) -> DIR_R[src]

pub fn opm(&self) -> OPM_R[src]

pub fn urs(&self) -> URS_R[src]

pub fn udis(&self) -> UDIS_R[src]

pub fn cen(&self) -> CEN_R[src]

pub fn uifremap(&self) -> UIFREMAP_R[src]

impl R<bool, TI1S_A>[src]

pub fn variant(&self) -> TI1S_A[src]

pub fn is_normal(&self) -> bool[src]

pub fn is_xor(&self) -> bool[src]

impl R<u8, MMS_A>[src]

pub fn variant(&self) -> MMS_A[src]

pub fn is_reset(&self) -> bool[src]

pub fn is_enable(&self) -> bool[src]

pub fn is_update(&self) -> bool[src]

pub fn is_compare_pulse(&self) -> bool[src]

pub fn is_compare_oc1(&self) -> bool[src]

pub fn is_compare_oc2(&self) -> bool[src]

pub fn is_compare_oc3(&self) -> bool[src]

pub fn is_compare_oc4(&self) -> bool[src]

impl R<bool, CCDS_A>[src]

pub fn variant(&self) -> CCDS_A[src]

pub fn is_on_compare(&self) -> bool[src]

pub fn is_on_update(&self) -> bool[src]

impl R<u32, Reg<u32, _CR2>>[src]

pub fn ois4(&self) -> OIS4_R[src]

pub fn ois3n(&self) -> OIS3N_R[src]

pub fn ois3(&self) -> OIS3_R[src]

pub fn ois2n(&self) -> OIS2N_R[src]

pub fn ois2(&self) -> OIS2_R[src]

pub fn ois1n(&self) -> OIS1N_R[src]

pub fn ois1(&self) -> OIS1_R[src]

pub fn ti1s(&self) -> TI1S_R[src]

`impl<U, T> R<U, T> where U: Copy,` [src]

`pub fn bits(&self) -> U`[src]

`impl<FI> R<bool, FI>`[src]

`pub fn bit(&self) -> bool`[src]

`pub fn bit_is_clear(&self) -> bool`[src]

`pub fn bit_is_set(&self) -> bool`[src]

`impl R<u8, CKD_A>`[src]

`pub fn variant(&self) -> Variant<u8, CKD_A>`[src]

`pub fn is_div1(&self) -> bool`[src]

`pub fn is_div2(&self) -> bool`[src]

`pub fn is_div4(&self) -> bool`[src]

`impl R<bool, ARPE_A>`[src]

`pub fn variant(&self) -> ARPE_A`[src]

`pub fn is_disabled(&self) -> bool`[src]

`pub fn is_enabled(&self) -> bool`[src]

`impl R<u8, CMS_A>`[src]

`pub fn variant(&self) -> CMS_A`[src]

`pub fn is_edge_aligned(&self) -> bool`[src]

`pub fn is_center_aligned1(&self) -> bool`[src]

`pub fn is_center_aligned2(&self) -> bool`[src]

`pub fn is_center_aligned3(&self) -> bool`[src]

`impl R<bool, DIR_A>`[src]

`pub fn variant(&self) -> DIR_A`[src]

`pub fn is_up(&self) -> bool`[src]

`pub fn is_down(&self) -> bool`[src]

`impl R<bool, OPM_A>`[src]

`pub fn variant(&self) -> OPM_A`[src]

`pub fn is_disabled(&self) -> bool`[src]

`pub fn is_enabled(&self) -> bool`[src]

`impl R<bool, URS_A>`[src]

`pub fn variant(&self) -> URS_A`[src]

`pub fn is_any_event(&self) -> bool`[src]

`pub fn is_counter_only(&self) -> bool`[src]

`impl R<bool, UDIS_A>`[src]

`pub fn variant(&self) -> UDIS_A`[src]

`pub fn is_enabled(&self) -> bool`[src]

`pub fn is_disabled(&self) -> bool`[src]

`impl R<bool, CEN_A>`[src]

`pub fn variant(&self) -> CEN_A`[src]

`pub fn is_disabled(&self) -> bool`[src]

`pub fn is_enabled(&self) -> bool`[src]

`impl R<u32, Reg<u32, _CR1>>`[src]

`pub fn ckd(&self) -> CKD_R`[src]

`pub fn arpe(&self) -> ARPE_R`[src]

`pub fn cms(&self) -> CMS_R`[src]

`pub fn dir(&self) -> DIR_R`[src]

`pub fn opm(&self) -> OPM_R`[src]

`pub fn urs(&self) -> URS_R`[src]

`pub fn udis(&self) -> UDIS_R`[src]

`pub fn cen(&self) -> CEN_R`[src]

`pub fn uifremap(&self) -> UIFREMAP_R`[src]

`impl R<bool, TI1S_A>`[src]

`pub fn variant(&self) -> TI1S_A`[src]

`pub fn is_normal(&self) -> bool`[src]

`pub fn is_xor(&self) -> bool`[src]

`impl R<u8, MMS_A>`[src]

`pub fn variant(&self) -> MMS_A`[src]

`pub fn is_reset(&self) -> bool`[src]

`pub fn is_enable(&self) -> bool`[src]

`pub fn is_update(&self) -> bool`[src]

`pub fn is_compare_pulse(&self) -> bool`[src]

`pub fn is_compare_oc1(&self) -> bool`[src]

`pub fn is_compare_oc2(&self) -> bool`[src]

`pub fn is_compare_oc3(&self) -> bool`[src]

`pub fn is_compare_oc4(&self) -> bool`[src]

`impl R<bool, CCDS_A>`[src]

`pub fn variant(&self) -> CCDS_A`[src]

`pub fn is_on_compare(&self) -> bool`[src]

`pub fn is_on_update(&self) -> bool`[src]

`impl R<u32, Reg<u32, _CR2>>`[src]

`pub fn ois4(&self) -> OIS4_R`[src]

`pub fn ois3n(&self) -> OIS3N_R`[src]

`pub fn ois3(&self) -> OIS3_R`[src]

`pub fn ois2n(&self) -> OIS2N_R`[src]

`pub fn ois2(&self) -> OIS2_R`[src]

`pub fn ois1n(&self) -> OIS1N_R`[src]

`pub fn ois1(&self) -> OIS1_R`[src]

`pub fn ti1s(&self) -> TI1S_R`[src]

`pub fn mms(&self) -> MMS_R`[src]

`pub fn ccds(&self) -> CCDS_R`[src]