stm32f7_staging/stm32f779/jpeg/
huffenc_ac1.rs

1///Register `HUFFENC_AC1%s` reader
2pub type R = crate::R<HUFFENC_AC1rs>;
3///Register `HUFFENC_AC1%s` writer
4pub type W = crate::W<HUFFENC_AC1rs>;
5///Field `DHTMem_RAM` reader - DHTMem RAM
6pub type DHTMEM_RAM_R = crate::FieldReader<u32>;
7///Field `DHTMem_RAM` writer - DHTMem RAM
8pub type DHTMEM_RAM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    ///Bits 0:31 - DHTMem RAM
11    #[inline(always)]
12    pub fn dhtmem_ram(&self) -> DHTMEM_RAM_R {
13        DHTMEM_RAM_R::new(self.bits)
14    }
15}
16impl core::fmt::Debug for R {
17    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18        f.debug_struct("HUFFENC_AC1")
19            .field("dhtmem_ram", &self.dhtmem_ram())
20            .finish()
21    }
22}
23impl W {
24    ///Bits 0:31 - DHTMem RAM
25    #[inline(always)]
26    pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<HUFFENC_AC1rs> {
27        DHTMEM_RAM_W::new(self, 0)
28    }
29}
30/**JPEG encoder, AC Huffman table 1
31
32You can [`read`](crate::Reg::read) this register and get [`huffenc_ac1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`huffenc_ac1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
33
34See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#JPEG:HUFFENC_AC1[0])*/
35pub struct HUFFENC_AC1rs;
36impl crate::RegisterSpec for HUFFENC_AC1rs {
37    type Ux = u32;
38}
39///`read()` method returns [`huffenc_ac1::R`](R) reader structure
40impl crate::Readable for HUFFENC_AC1rs {}
41///`write(|w| ..)` method takes [`huffenc_ac1::W`](W) writer structure
42impl crate::Writable for HUFFENC_AC1rs {
43    type Safety = crate::Unsafe;
44}
45///`reset()` method sets HUFFENC_AC1%s to value 0
46impl crate::Resettable for HUFFENC_AC1rs {}
stm32f7_staging/stm32f779/jpeg/huffenc_ac1.rs

stm32f7_staging/stm32f779/jpeg/
huffenc_ac1.rs
