stm32f7-staging 0.18.1

///Register `PLLSAICFGR` reader
pub type R = crate::R<PLLSAICFGRrs>;
///Register `PLLSAICFGR` writer
pub type W = crate::W<PLLSAICFGRrs>;
///Field `PLLSAIN` reader - PLLSAI division factor for VCO
pub type PLLSAIN_R = crate::FieldReader<u16>;
///Field `PLLSAIN` writer - PLLSAI division factor for VCO
pub type PLLSAIN_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
/**PLLSAI division factor for 48MHz clock

Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PLLSAIP {
    ///0: PLL*P=2
    Div2 = 0,
    ///1: PLL*P=4
    Div4 = 1,
    ///2: PLL*P=6
    Div6 = 2,
    ///3: PLL*P=8
    Div8 = 3,
}
impl From<PLLSAIP> for u8 {
    #[inline(always)]
    fn from(variant: PLLSAIP) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for PLLSAIP {
    type Ux = u8;
}
impl crate::IsEnum for PLLSAIP {}
///Field `PLLSAIP` reader - PLLSAI division factor for 48MHz clock
pub type PLLSAIP_R = crate::FieldReader<PLLSAIP>;
impl PLLSAIP_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub const fn variant(&self) -> PLLSAIP {
        match self.bits {
            0 => PLLSAIP::Div2,
            1 => PLLSAIP::Div4,
            2 => PLLSAIP::Div6,
            3 => PLLSAIP::Div8,
            _ => unreachable!(),
        }
    }
    ///PLL*P=2
    #[inline(always)]
    pub fn is_div2(&self) -> bool {
        *self == PLLSAIP::Div2
    }
    ///PLL*P=4
    #[inline(always)]
    pub fn is_div4(&self) -> bool {
        *self == PLLSAIP::Div4
    }
    ///PLL*P=6
    #[inline(always)]
    pub fn is_div6(&self) -> bool {
        *self == PLLSAIP::Div6
    }
    ///PLL*P=8
    #[inline(always)]
    pub fn is_div8(&self) -> bool {
        *self == PLLSAIP::Div8
    }
}
///Field `PLLSAIP` writer - PLLSAI division factor for 48MHz clock
pub type PLLSAIP_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PLLSAIP, crate::Safe>;
impl<'a, REG> PLLSAIP_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    ///PLL*P=2
    #[inline(always)]
    pub fn div2(self) -> &'a mut crate::W<REG> {
        self.variant(PLLSAIP::Div2)
    }
    ///PLL*P=4
    #[inline(always)]
    pub fn div4(self) -> &'a mut crate::W<REG> {
        self.variant(PLLSAIP::Div4)
    }
    ///PLL*P=6
    #[inline(always)]
    pub fn div6(self) -> &'a mut crate::W<REG> {
        self.variant(PLLSAIP::Div6)
    }
    ///PLL*P=8
    #[inline(always)]
    pub fn div8(self) -> &'a mut crate::W<REG> {
        self.variant(PLLSAIP::Div8)
    }
}
///Field `PLLSAIQ` reader - PLLSAI division factor for SAI clock
pub type PLLSAIQ_R = crate::FieldReader;
///Field `PLLSAIQ` writer - PLLSAI division factor for SAI clock
pub type PLLSAIQ_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
///Field `PLLSAIR` reader - PLLSAI division factor for LCD clock
pub type PLLSAIR_R = crate::FieldReader;
///Field `PLLSAIR` writer - PLLSAI division factor for LCD clock
pub type PLLSAIR_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
    ///Bits 6:14 - PLLSAI division factor for VCO
    #[inline(always)]
    pub fn pllsain(&self) -> PLLSAIN_R {
        PLLSAIN_R::new(((self.bits >> 6) & 0x01ff) as u16)
    }
    ///Bits 16:17 - PLLSAI division factor for 48MHz clock
    #[inline(always)]
    pub fn pllsaip(&self) -> PLLSAIP_R {
        PLLSAIP_R::new(((self.bits >> 16) & 3) as u8)
    }
    ///Bits 24:27 - PLLSAI division factor for SAI clock
    #[inline(always)]
    pub fn pllsaiq(&self) -> PLLSAIQ_R {
        PLLSAIQ_R::new(((self.bits >> 24) & 0x0f) as u8)
    }
    ///Bits 28:30 - PLLSAI division factor for LCD clock
    #[inline(always)]
    pub fn pllsair(&self) -> PLLSAIR_R {
        PLLSAIR_R::new(((self.bits >> 28) & 7) as u8)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PLLSAICFGR")
            .field("pllsain", &self.pllsain())
            .field("pllsaip", &self.pllsaip())
            .field("pllsaiq", &self.pllsaiq())
            .field("pllsair", &self.pllsair())
            .finish()
    }
}
impl W {
    ///Bits 6:14 - PLLSAI division factor for VCO
    #[inline(always)]
    pub fn pllsain(&mut self) -> PLLSAIN_W<PLLSAICFGRrs> {
        PLLSAIN_W::new(self, 6)
    }
    ///Bits 16:17 - PLLSAI division factor for 48MHz clock
    #[inline(always)]
    pub fn pllsaip(&mut self) -> PLLSAIP_W<PLLSAICFGRrs> {
        PLLSAIP_W::new(self, 16)
    }
    ///Bits 24:27 - PLLSAI division factor for SAI clock
    #[inline(always)]
    pub fn pllsaiq(&mut self) -> PLLSAIQ_W<PLLSAICFGRrs> {
        PLLSAIQ_W::new(self, 24)
    }
    ///Bits 28:30 - PLLSAI division factor for LCD clock
    #[inline(always)]
    pub fn pllsair(&mut self) -> PLLSAIR_W<PLLSAICFGRrs> {
        PLLSAIR_W::new(self, 28)
    }
}
/**PLL configuration register

You can [`read`](crate::Reg::read) this register and get [`pllsaicfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllsaicfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F777.html#RCC:PLLSAICFGR)*/
pub struct PLLSAICFGRrs;
impl crate::RegisterSpec for PLLSAICFGRrs {
    type Ux = u32;
}
///`read()` method returns [`pllsaicfgr::R`](R) reader structure
impl crate::Readable for PLLSAICFGRrs {}
///`write(|w| ..)` method takes [`pllsaicfgr::W`](W) writer structure
impl crate::Writable for PLLSAICFGRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets PLLSAICFGR to value 0x2000_3000
impl crate::Resettable for PLLSAICFGRrs {
    const RESET_VALUE: u32 = 0x2000_3000;
}