stm32f7_staging/stm32f779/tim2/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5/**Capture/compare DMA selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CCDS {
11    ///0: CCx DMA request sent when CCx event occurs
12    OnCompare = 0,
13    ///1: CCx DMA request sent when update event occurs
14    OnUpdate = 1,
15}
16impl From<CCDS> for bool {
17    #[inline(always)]
18    fn from(variant: CCDS) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCDS` reader - Capture/compare DMA selection
23pub type CCDS_R = crate::BitReader<CCDS>;
24impl CCDS_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CCDS {
28        match self.bits {
29            false => CCDS::OnCompare,
30            true => CCDS::OnUpdate,
31        }
32    }
33    ///CCx DMA request sent when CCx event occurs
34    #[inline(always)]
35    pub fn is_on_compare(&self) -> bool {
36        *self == CCDS::OnCompare
37    }
38    ///CCx DMA request sent when update event occurs
39    #[inline(always)]
40    pub fn is_on_update(&self) -> bool {
41        *self == CCDS::OnUpdate
42    }
43}
44///Field `CCDS` writer - Capture/compare DMA selection
45pub type CCDS_W<'a, REG> = crate::BitWriter<'a, REG, CCDS>;
46impl<'a, REG> CCDS_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///CCx DMA request sent when CCx event occurs
51    #[inline(always)]
52    pub fn on_compare(self) -> &'a mut crate::W<REG> {
53        self.variant(CCDS::OnCompare)
54    }
55    ///CCx DMA request sent when update event occurs
56    #[inline(always)]
57    pub fn on_update(self) -> &'a mut crate::W<REG> {
58        self.variant(CCDS::OnUpdate)
59    }
60}
61/**Master mode selection
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum MMS {
68    ///0: The UG bit from the TIMx_EGR register is used as trigger output
69    Reset = 0,
70    ///1: The counter enable signal, CNT_EN, is used as trigger output
71    Enable = 1,
72    ///2: The update event is selected as trigger output
73    Update = 2,
74    ///3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
75    ComparePulse = 3,
76    ///4: OC1REF signal is used as trigger output
77    CompareOc1 = 4,
78    ///5: OC2REF signal is used as trigger output
79    CompareOc2 = 5,
80    ///6: OC3REF signal is used as trigger output
81    CompareOc3 = 6,
82    ///7: OC4REF signal is used as trigger output
83    CompareOc4 = 7,
84}
85impl From<MMS> for u8 {
86    #[inline(always)]
87    fn from(variant: MMS) -> Self {
88        variant as _
89    }
90}
91impl crate::FieldSpec for MMS {
92    type Ux = u8;
93}
94impl crate::IsEnum for MMS {}
95///Field `MMS` reader - Master mode selection
96pub type MMS_R = crate::FieldReader<MMS>;
97impl MMS_R {
98    ///Get enumerated values variant
99    #[inline(always)]
100    pub const fn variant(&self) -> MMS {
101        match self.bits {
102            0 => MMS::Reset,
103            1 => MMS::Enable,
104            2 => MMS::Update,
105            3 => MMS::ComparePulse,
106            4 => MMS::CompareOc1,
107            5 => MMS::CompareOc2,
108            6 => MMS::CompareOc3,
109            7 => MMS::CompareOc4,
110            _ => unreachable!(),
111        }
112    }
113    ///The UG bit from the TIMx_EGR register is used as trigger output
114    #[inline(always)]
115    pub fn is_reset(&self) -> bool {
116        *self == MMS::Reset
117    }
118    ///The counter enable signal, CNT_EN, is used as trigger output
119    #[inline(always)]
120    pub fn is_enable(&self) -> bool {
121        *self == MMS::Enable
122    }
123    ///The update event is selected as trigger output
124    #[inline(always)]
125    pub fn is_update(&self) -> bool {
126        *self == MMS::Update
127    }
128    ///The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
129    #[inline(always)]
130    pub fn is_compare_pulse(&self) -> bool {
131        *self == MMS::ComparePulse
132    }
133    ///OC1REF signal is used as trigger output
134    #[inline(always)]
135    pub fn is_compare_oc1(&self) -> bool {
136        *self == MMS::CompareOc1
137    }
138    ///OC2REF signal is used as trigger output
139    #[inline(always)]
140    pub fn is_compare_oc2(&self) -> bool {
141        *self == MMS::CompareOc2
142    }
143    ///OC3REF signal is used as trigger output
144    #[inline(always)]
145    pub fn is_compare_oc3(&self) -> bool {
146        *self == MMS::CompareOc3
147    }
148    ///OC4REF signal is used as trigger output
149    #[inline(always)]
150    pub fn is_compare_oc4(&self) -> bool {
151        *self == MMS::CompareOc4
152    }
153}
154///Field `MMS` writer - Master mode selection
155pub type MMS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, MMS, crate::Safe>;
156impl<'a, REG> MMS_W<'a, REG>
157where
158    REG: crate::Writable + crate::RegisterSpec,
159    REG::Ux: From<u8>,
160{
161    ///The UG bit from the TIMx_EGR register is used as trigger output
162    #[inline(always)]
163    pub fn reset(self) -> &'a mut crate::W<REG> {
164        self.variant(MMS::Reset)
165    }
166    ///The counter enable signal, CNT_EN, is used as trigger output
167    #[inline(always)]
168    pub fn enable(self) -> &'a mut crate::W<REG> {
169        self.variant(MMS::Enable)
170    }
171    ///The update event is selected as trigger output
172    #[inline(always)]
173    pub fn update(self) -> &'a mut crate::W<REG> {
174        self.variant(MMS::Update)
175    }
176    ///The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
177    #[inline(always)]
178    pub fn compare_pulse(self) -> &'a mut crate::W<REG> {
179        self.variant(MMS::ComparePulse)
180    }
181    ///OC1REF signal is used as trigger output
182    #[inline(always)]
183    pub fn compare_oc1(self) -> &'a mut crate::W<REG> {
184        self.variant(MMS::CompareOc1)
185    }
186    ///OC2REF signal is used as trigger output
187    #[inline(always)]
188    pub fn compare_oc2(self) -> &'a mut crate::W<REG> {
189        self.variant(MMS::CompareOc2)
190    }
191    ///OC3REF signal is used as trigger output
192    #[inline(always)]
193    pub fn compare_oc3(self) -> &'a mut crate::W<REG> {
194        self.variant(MMS::CompareOc3)
195    }
196    ///OC4REF signal is used as trigger output
197    #[inline(always)]
198    pub fn compare_oc4(self) -> &'a mut crate::W<REG> {
199        self.variant(MMS::CompareOc4)
200    }
201}
202/**TI1 selection
203
204Value on reset: 0*/
205#[cfg_attr(feature = "defmt", derive(defmt::Format))]
206#[derive(Clone, Copy, Debug, PartialEq, Eq)]
207pub enum TI1S {
208    ///0: The TIMx_CH1 pin is connected to TI1 input
209    Normal = 0,
210    ///1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
211    Xor = 1,
212}
213impl From<TI1S> for bool {
214    #[inline(always)]
215    fn from(variant: TI1S) -> Self {
216        variant as u8 != 0
217    }
218}
219///Field `TI1S` reader - TI1 selection
220pub type TI1S_R = crate::BitReader<TI1S>;
221impl TI1S_R {
222    ///Get enumerated values variant
223    #[inline(always)]
224    pub const fn variant(&self) -> TI1S {
225        match self.bits {
226            false => TI1S::Normal,
227            true => TI1S::Xor,
228        }
229    }
230    ///The TIMx_CH1 pin is connected to TI1 input
231    #[inline(always)]
232    pub fn is_normal(&self) -> bool {
233        *self == TI1S::Normal
234    }
235    ///The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
236    #[inline(always)]
237    pub fn is_xor(&self) -> bool {
238        *self == TI1S::Xor
239    }
240}
241///Field `TI1S` writer - TI1 selection
242pub type TI1S_W<'a, REG> = crate::BitWriter<'a, REG, TI1S>;
243impl<'a, REG> TI1S_W<'a, REG>
244where
245    REG: crate::Writable + crate::RegisterSpec,
246{
247    ///The TIMx_CH1 pin is connected to TI1 input
248    #[inline(always)]
249    pub fn normal(self) -> &'a mut crate::W<REG> {
250        self.variant(TI1S::Normal)
251    }
252    ///The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
253    #[inline(always)]
254    pub fn xor(self) -> &'a mut crate::W<REG> {
255        self.variant(TI1S::Xor)
256    }
257}
258impl R {
259    ///Bit 3 - Capture/compare DMA selection
260    #[inline(always)]
261    pub fn ccds(&self) -> CCDS_R {
262        CCDS_R::new(((self.bits >> 3) & 1) != 0)
263    }
264    ///Bits 4:6 - Master mode selection
265    #[inline(always)]
266    pub fn mms(&self) -> MMS_R {
267        MMS_R::new(((self.bits >> 4) & 7) as u8)
268    }
269    ///Bit 7 - TI1 selection
270    #[inline(always)]
271    pub fn ti1s(&self) -> TI1S_R {
272        TI1S_R::new(((self.bits >> 7) & 1) != 0)
273    }
274}
275impl core::fmt::Debug for R {
276    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
277        f.debug_struct("CR2")
278            .field("ti1s", &self.ti1s())
279            .field("mms", &self.mms())
280            .field("ccds", &self.ccds())
281            .finish()
282    }
283}
284impl W {
285    ///Bit 3 - Capture/compare DMA selection
286    #[inline(always)]
287    pub fn ccds(&mut self) -> CCDS_W<CR2rs> {
288        CCDS_W::new(self, 3)
289    }
290    ///Bits 4:6 - Master mode selection
291    #[inline(always)]
292    pub fn mms(&mut self) -> MMS_W<CR2rs> {
293        MMS_W::new(self, 4)
294    }
295    ///Bit 7 - TI1 selection
296    #[inline(always)]
297    pub fn ti1s(&mut self) -> TI1S_W<CR2rs> {
298        TI1S_W::new(self, 7)
299    }
300}
301/**control register 2
302
303You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
304
305See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM2:CR2)*/
306pub struct CR2rs;
307impl crate::RegisterSpec for CR2rs {
308    type Ux = u32;
309}
310///`read()` method returns [`cr2::R`](R) reader structure
311impl crate::Readable for CR2rs {}
312///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
313impl crate::Writable for CR2rs {
314    type Safety = crate::Unsafe;
315}
316///`reset()` method sets CR2 to value 0
317impl crate::Resettable for CR2rs {}
stm32f7_staging/stm32f779/tim2/cr2.rs

stm32f7_staging/stm32f779/tim2/
cr2.rs
