stm32f429/syscfg/
memrm.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::MEMRM {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = r" Value of the field"]
46pub struct MEM_MODER {
47    bits: u8,
48}
49impl MEM_MODER {
50    #[doc = r" Value of the field as raw bits"]
51    #[inline]
52    pub fn bits(&self) -> u8 {
53        self.bits
54    }
55}
56#[doc = r" Value of the field"]
57pub struct FB_MODER {
58    bits: bool,
59}
60impl FB_MODER {
61    #[doc = r" Value of the field as raw bits"]
62    #[inline]
63    pub fn bit(&self) -> bool {
64        self.bits
65    }
66    #[doc = r" Returns `true` if the bit is clear (0)"]
67    #[inline]
68    pub fn bit_is_clear(&self) -> bool {
69        !self.bit()
70    }
71    #[doc = r" Returns `true` if the bit is set (1)"]
72    #[inline]
73    pub fn bit_is_set(&self) -> bool {
74        self.bit()
75    }
76}
77#[doc = r" Value of the field"]
78pub struct SWP_FMCR {
79    bits: u8,
80}
81impl SWP_FMCR {
82    #[doc = r" Value of the field as raw bits"]
83    #[inline]
84    pub fn bits(&self) -> u8 {
85        self.bits
86    }
87}
88#[doc = r" Proxy"]
89pub struct _MEM_MODEW<'a> {
90    w: &'a mut W,
91}
92impl<'a> _MEM_MODEW<'a> {
93    #[doc = r" Writes raw bits to the field"]
94    #[inline]
95    pub unsafe fn bits(self, value: u8) -> &'a mut W {
96        const MASK: u8 = 7;
97        const OFFSET: u8 = 0;
98        self.w.bits &= !((MASK as u32) << OFFSET);
99        self.w.bits |= ((value & MASK) as u32) << OFFSET;
100        self.w
101    }
102}
103#[doc = r" Proxy"]
104pub struct _FB_MODEW<'a> {
105    w: &'a mut W,
106}
107impl<'a> _FB_MODEW<'a> {
108    #[doc = r" Sets the field bit"]
109    pub fn set_bit(self) -> &'a mut W {
110        self.bit(true)
111    }
112    #[doc = r" Clears the field bit"]
113    pub fn clear_bit(self) -> &'a mut W {
114        self.bit(false)
115    }
116    #[doc = r" Writes raw bits to the field"]
117    #[inline]
118    pub fn bit(self, value: bool) -> &'a mut W {
119        const MASK: bool = true;
120        const OFFSET: u8 = 8;
121        self.w.bits &= !((MASK as u32) << OFFSET);
122        self.w.bits |= ((value & MASK) as u32) << OFFSET;
123        self.w
124    }
125}
126#[doc = r" Proxy"]
127pub struct _SWP_FMCW<'a> {
128    w: &'a mut W,
129}
130impl<'a> _SWP_FMCW<'a> {
131    #[doc = r" Writes raw bits to the field"]
132    #[inline]
133    pub unsafe fn bits(self, value: u8) -> &'a mut W {
134        const MASK: u8 = 3;
135        const OFFSET: u8 = 10;
136        self.w.bits &= !((MASK as u32) << OFFSET);
137        self.w.bits |= ((value & MASK) as u32) << OFFSET;
138        self.w
139    }
140}
141impl R {
142    #[doc = r" Value of the register as raw bits"]
143    #[inline]
144    pub fn bits(&self) -> u32 {
145        self.bits
146    }
147    #[doc = "Bits 0:2 - Memory mapping selection"]
148    #[inline]
149    pub fn mem_mode(&self) -> MEM_MODER {
150        let bits = {
151            const MASK: u8 = 7;
152            const OFFSET: u8 = 0;
153            ((self.bits >> OFFSET) & MASK as u32) as u8
154        };
155        MEM_MODER { bits }
156    }
157    #[doc = "Bit 8 - Flash bank mode selection"]
158    #[inline]
159    pub fn fb_mode(&self) -> FB_MODER {
160        let bits = {
161            const MASK: bool = true;
162            const OFFSET: u8 = 8;
163            ((self.bits >> OFFSET) & MASK as u32) != 0
164        };
165        FB_MODER { bits }
166    }
167    #[doc = "Bits 10:11 - FMC memory mapping swap"]
168    #[inline]
169    pub fn swp_fmc(&self) -> SWP_FMCR {
170        let bits = {
171            const MASK: u8 = 3;
172            const OFFSET: u8 = 10;
173            ((self.bits >> OFFSET) & MASK as u32) as u8
174        };
175        SWP_FMCR { bits }
176    }
177}
178impl W {
179    #[doc = r" Reset value of the register"]
180    #[inline]
181    pub fn reset_value() -> W {
182        W { bits: 0 }
183    }
184    #[doc = r" Writes raw bits to the register"]
185    #[inline]
186    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
187        self.bits = bits;
188        self
189    }
190    #[doc = "Bits 0:2 - Memory mapping selection"]
191    #[inline]
192    pub fn mem_mode(&mut self) -> _MEM_MODEW {
193        _MEM_MODEW { w: self }
194    }
195    #[doc = "Bit 8 - Flash bank mode selection"]
196    #[inline]
197    pub fn fb_mode(&mut self) -> _FB_MODEW {
198        _FB_MODEW { w: self }
199    }
200    #[doc = "Bits 10:11 - FMC memory mapping swap"]
201    #[inline]
202    pub fn swp_fmc(&mut self) -> _SWP_FMCW {
203        _SWP_FMCW { w: self }
204    }
205}
stm32f429/syscfg/memrm.rs

stm32f429/syscfg/
memrm.rs
