pub unsafe trait DMASet<STREAM, CHANNEL, DIRECTION> { }Trait to mark a set of Stream, Channel and Direction for a Peripheral as correct together.
Memory corruption might occur if this trait is implemented for an invalid combination.
impl DMASet<Stream0<DMA1>, Channel0, PeripheralToMemory> for SPI3[src]impl DMASet<Stream0<DMA1>, Channel1, PeripheralToMemory> for I2C1[src]impl DMASet<Stream0<DMA1>, Channel2, MemoryToPeripheral> for CCR1<TIM4>[src]impl DMASet<Stream0<DMA1>, Channel2, PeripheralToMemory> for CCR1<TIM4>[src]impl DMASet<Stream0<DMA1>, Channel4, PeripheralToMemory> for UART5[src]impl DMASet<Stream0<DMA1>, Channel6, MemoryToPeripheral> for CCR3<TIM5>[src]impl DMASet<Stream0<DMA1>, Channel6, MemoryToPeripheral> for DMAR<TIM5>[src]impl DMASet<Stream0<DMA1>, Channel6, PeripheralToMemory> for CCR3<TIM5>[src]impl DMASet<Stream0<DMA1>, Channel6, PeripheralToMemory> for DMAR<TIM5>[src]impl DMASet<Stream0<DMA2>, Channel0, MemoryToMemory<u8>> for MemoryToMemory<u8>[src]impl DMASet<Stream0<DMA2>, Channel0, MemoryToMemory<u16>> for MemoryToMemory<u16>[src]impl DMASet<Stream0<DMA2>, Channel0, MemoryToMemory<u32>> for MemoryToMemory<u32>[src]impl DMASet<Stream0<DMA2>, Channel0, PeripheralToMemory> for ADC1[src]impl DMASet<Stream0<DMA2>, Channel2, PeripheralToMemory> for ADC3[src]impl DMASet<Stream0<DMA2>, Channel3, PeripheralToMemory> for SPI1[src]impl DMASet<Stream0<DMA2>, Channel6, MemoryToPeripheral> for DMAR<TIM1>[src]impl DMASet<Stream0<DMA2>, Channel6, PeripheralToMemory> for DMAR<TIM1>[src]impl DMASet<Stream1<DMA1>, Channel3, MemoryToPeripheral> for CCR3<TIM2>[src]impl DMASet<Stream1<DMA1>, Channel3, MemoryToPeripheral> for DMAR<TIM2>[src]impl DMASet<Stream1<DMA1>, Channel3, PeripheralToMemory> for CCR3<TIM2>[src]impl DMASet<Stream1<DMA1>, Channel3, PeripheralToMemory> for DMAR<TIM2>[src]impl DMASet<Stream1<DMA1>, Channel4, PeripheralToMemory> for USART3[src]impl DMASet<Stream1<DMA1>, Channel6, MemoryToPeripheral> for CCR4<TIM5>[src]impl DMASet<Stream1<DMA1>, Channel6, MemoryToPeripheral> for DMAR<TIM5>[src]impl DMASet<Stream1<DMA1>, Channel6, PeripheralToMemory> for CCR4<TIM5>[src]impl DMASet<Stream1<DMA1>, Channel6, PeripheralToMemory> for DMAR<TIM5>[src]impl DMASet<Stream1<DMA2>, Channel0, MemoryToMemory<u8>> for MemoryToMemory<u8>[src]impl DMASet<Stream1<DMA2>, Channel0, MemoryToMemory<u16>> for MemoryToMemory<u16>[src]impl DMASet<Stream1<DMA2>, Channel0, MemoryToMemory<u32>> for MemoryToMemory<u32>[src]impl DMASet<Stream1<DMA2>, Channel1, PeripheralToMemory> for DCMI[src]impl DMASet<Stream1<DMA2>, Channel2, PeripheralToMemory> for ADC3[src]impl DMASet<Stream1<DMA2>, Channel5, PeripheralToMemory> for Rx<USART6>[src]impl DMASet<Stream1<DMA2>, Channel5, PeripheralToMemory> for USART6[src]impl DMASet<Stream1<DMA2>, Channel6, MemoryToPeripheral> for CCR1<TIM1>[src]impl DMASet<Stream1<DMA2>, Channel6, PeripheralToMemory> for CCR1<TIM1>[src]impl DMASet<Stream1<DMA2>, Channel7, MemoryToPeripheral> for DMAR<TIM8>[src]impl DMASet<Stream1<DMA2>, Channel7, PeripheralToMemory> for DMAR<TIM8>[src]impl DMASet<Stream2<DMA1>, Channel0, PeripheralToMemory> for SPI3[src]impl DMASet<Stream2<DMA1>, Channel3, PeripheralToMemory> for I2C3[src]impl DMASet<Stream2<DMA1>, Channel4, PeripheralToMemory> for UART4[src]impl DMASet<Stream2<DMA1>, Channel5, MemoryToPeripheral> for CCR4<TIM3>[src]impl DMASet<Stream2<DMA1>, Channel5, MemoryToPeripheral> for DMAR<TIM3>[src]impl DMASet<Stream2<DMA1>, Channel5, PeripheralToMemory> for CCR4<TIM3>[src]impl DMASet<Stream2<DMA1>, Channel5, PeripheralToMemory> for DMAR<TIM3>[src]impl DMASet<Stream2<DMA1>, Channel6, MemoryToPeripheral> for CCR1<TIM5>[src]impl DMASet<Stream2<DMA1>, Channel6, PeripheralToMemory> for CCR1<TIM5>[src]impl DMASet<Stream2<DMA1>, Channel7, PeripheralToMemory> for I2C2[src]impl DMASet<Stream2<DMA2>, Channel0, MemoryToMemory<u8>> for MemoryToMemory<u8>[src]impl DMASet<Stream2<DMA2>, Channel0, MemoryToMemory<u16>> for MemoryToMemory<u16>[src]impl DMASet<Stream2<DMA2>, Channel0, MemoryToMemory<u32>> for MemoryToMemory<u32>[src]impl DMASet<Stream2<DMA2>, Channel0, MemoryToPeripheral> for CCR1<TIM8>[src]impl DMASet<Stream2<DMA2>, Channel0, MemoryToPeripheral> for CCR2<TIM8>[src]impl DMASet<Stream2<DMA2>, Channel0, MemoryToPeripheral> for CCR3<TIM8>[src]impl DMASet<Stream2<DMA2>, Channel0, PeripheralToMemory> for CCR1<TIM8>[src]impl DMASet<Stream2<DMA2>, Channel0, PeripheralToMemory> for CCR2<TIM8>[src]impl DMASet<Stream2<DMA2>, Channel0, PeripheralToMemory> for CCR3<TIM8>[src]impl DMASet<Stream2<DMA2>, Channel1, PeripheralToMemory> for ADC2[src]impl DMASet<Stream2<DMA2>, Channel3, PeripheralToMemory> for SPI1[src]impl DMASet<Stream2<DMA2>, Channel4, PeripheralToMemory> for Rx<USART1>[src]impl DMASet<Stream2<DMA2>, Channel4, PeripheralToMemory> for USART1[src]impl DMASet<Stream2<DMA2>, Channel5, PeripheralToMemory> for Rx<USART6>[src]impl DMASet<Stream2<DMA2>, Channel5, PeripheralToMemory> for USART6[src]impl DMASet<Stream2<DMA2>, Channel6, MemoryToPeripheral> for CCR2<TIM1>[src]impl DMASet<Stream2<DMA2>, Channel6, PeripheralToMemory> for CCR2<TIM1>[src]impl DMASet<Stream2<DMA2>, Channel7, MemoryToPeripheral> for CCR1<TIM8>[src]impl DMASet<Stream2<DMA2>, Channel7, PeripheralToMemory> for CCR1<TIM8>[src]impl DMASet<Stream3<DMA1>, Channel0, PeripheralToMemory> for SPI2[src]impl DMASet<Stream3<DMA1>, Channel2, MemoryToPeripheral> for CCR2<TIM4>[src]impl DMASet<Stream3<DMA1>, Channel2, PeripheralToMemory> for CCR2<TIM4>[src]impl DMASet<Stream3<DMA1>, Channel4, MemoryToPeripheral> for USART3[src]impl DMASet<Stream3<DMA1>, Channel6, MemoryToPeripheral> for CCR4<TIM5>[src]impl DMASet<Stream3<DMA1>, Channel6, MemoryToPeripheral> for DMAR<TIM5>[src]impl DMASet<Stream3<DMA1>, Channel6, PeripheralToMemory> for CCR4<TIM5>[src]impl DMASet<Stream3<DMA1>, Channel6, PeripheralToMemory> for DMAR<TIM5>[src]impl DMASet<Stream3<DMA1>, Channel7, PeripheralToMemory> for I2C2[src]impl DMASet<Stream3<DMA2>, Channel0, MemoryToMemory<u8>> for MemoryToMemory<u8>[src]impl DMASet<Stream3<DMA2>, Channel0, MemoryToMemory<u16>> for MemoryToMemory<u16>[src]impl DMASet<Stream3<DMA2>, Channel0, MemoryToMemory<u32>> for MemoryToMemory<u32>[src]impl DMASet<Stream3<DMA2>, Channel1, PeripheralToMemory> for ADC2[src]impl DMASet<Stream3<DMA2>, Channel3, MemoryToPeripheral> for SPI1[src]impl DMASet<Stream3<DMA2>, Channel4, MemoryToPeripheral> for SDIO[src]impl DMASet<Stream3<DMA2>, Channel4, PeripheralToMemory> for SDIO[src]impl DMASet<Stream3<DMA2>, Channel6, MemoryToPeripheral> for CCR1<TIM1>[src]impl DMASet<Stream3<DMA2>, Channel6, PeripheralToMemory> for CCR1<TIM1>[src]impl DMASet<Stream3<DMA2>, Channel7, MemoryToPeripheral> for CCR2<TIM8>[src]impl DMASet<Stream3<DMA2>, Channel7, PeripheralToMemory> for CCR2<TIM8>[src]impl DMASet<Stream4<DMA1>, Channel0, MemoryToPeripheral> for SPI2[src]impl DMASet<Stream4<DMA1>, Channel3, MemoryToPeripheral> for I2C3[src]impl DMASet<Stream4<DMA1>, Channel4, MemoryToPeripheral> for UART4[src]impl DMASet<Stream4<DMA1>, Channel5, MemoryToPeripheral> for CCR1<TIM3>[src]impl DMASet<Stream4<DMA1>, Channel5, MemoryToPeripheral> for DMAR<TIM3>[src]impl DMASet<Stream4<DMA1>, Channel5, PeripheralToMemory> for CCR1<TIM3>[src]impl DMASet<Stream4<DMA1>, Channel5, PeripheralToMemory> for DMAR<TIM3>[src]impl DMASet<Stream4<DMA1>, Channel6, MemoryToPeripheral> for CCR2<TIM5>[src]impl DMASet<Stream4<DMA1>, Channel6, PeripheralToMemory> for CCR2<TIM5>[src]impl DMASet<Stream4<DMA1>, Channel7, MemoryToPeripheral> for USART3[src]impl DMASet<Stream4<DMA2>, Channel0, MemoryToMemory<u8>> for MemoryToMemory<u8>[src]impl DMASet<Stream4<DMA2>, Channel0, MemoryToMemory<u16>> for MemoryToMemory<u16>[src]impl DMASet<Stream4<DMA2>, Channel0, MemoryToMemory<u32>> for MemoryToMemory<u32>[src]impl DMASet<Stream4<DMA2>, Channel0, PeripheralToMemory> for ADC1[src]impl DMASet<Stream4<DMA2>, Channel6, MemoryToPeripheral> for CCR4<TIM1>[src]impl DMASet<Stream4<DMA2>, Channel6, MemoryToPeripheral> for DMAR<TIM1>[src]impl DMASet<Stream4<DMA2>, Channel6, PeripheralToMemory> for CCR4<TIM1>[src]impl DMASet<Stream4<DMA2>, Channel6, PeripheralToMemory> for DMAR<TIM1>[src]impl DMASet<Stream4<DMA2>, Channel7, MemoryToPeripheral> for CCR3<TIM8>[src]impl DMASet<Stream4<DMA2>, Channel7, PeripheralToMemory> for CCR3<TIM8>[src]impl DMASet<Stream5<DMA1>, Channel0, MemoryToPeripheral> for SPI3[src]impl DMASet<Stream5<DMA1>, Channel1, PeripheralToMemory> for I2C1[src]impl DMASet<Stream5<DMA1>, Channel3, MemoryToPeripheral> for CCR1<TIM2>[src]impl DMASet<Stream5<DMA1>, Channel3, PeripheralToMemory> for CCR1<TIM2>[src]impl DMASet<Stream5<DMA1>, Channel4, PeripheralToMemory> for Rx<USART2>[src]impl DMASet<Stream5<DMA1>, Channel4, PeripheralToMemory> for USART2[src]impl DMASet<Stream5<DMA1>, Channel5, MemoryToPeripheral> for CCR2<TIM3>[src]impl DMASet<Stream5<DMA1>, Channel5, PeripheralToMemory> for CCR2<TIM3>[src]impl DMASet<Stream5<DMA2>, Channel0, MemoryToMemory<u8>> for MemoryToMemory<u8>[src]impl DMASet<Stream5<DMA2>, Channel0, MemoryToMemory<u16>> for MemoryToMemory<u16>[src]impl DMASet<Stream5<DMA2>, Channel0, MemoryToMemory<u32>> for MemoryToMemory<u32>[src]impl DMASet<Stream5<DMA2>, Channel2, PeripheralToMemory> for CRYP[src]impl DMASet<Stream5<DMA2>, Channel3, MemoryToPeripheral> for SPI1[src]impl DMASet<Stream5<DMA2>, Channel4, PeripheralToMemory> for Rx<USART1>[src]impl DMASet<Stream5<DMA2>, Channel4, PeripheralToMemory> for USART1[src]impl DMASet<Stream5<DMA2>, Channel6, MemoryToPeripheral> for DMAR<TIM1>[src]impl DMASet<Stream5<DMA2>, Channel6, PeripheralToMemory> for DMAR<TIM1>[src]impl DMASet<Stream6<DMA1>, Channel1, MemoryToPeripheral> for I2C1[src]impl DMASet<Stream6<DMA1>, Channel2, MemoryToPeripheral> for DMAR<TIM4>[src]impl DMASet<Stream6<DMA1>, Channel2, PeripheralToMemory> for DMAR<TIM4>[src]impl DMASet<Stream6<DMA1>, Channel3, MemoryToPeripheral> for CCR2<TIM2>[src]impl DMASet<Stream6<DMA1>, Channel3, MemoryToPeripheral> for CCR4<TIM2>[src]impl DMASet<Stream6<DMA1>, Channel3, PeripheralToMemory> for CCR2<TIM2>[src]impl DMASet<Stream6<DMA1>, Channel3, PeripheralToMemory> for CCR4<TIM2>[src]impl DMASet<Stream6<DMA1>, Channel4, MemoryToPeripheral> for Tx<USART2>[src]impl DMASet<Stream6<DMA1>, Channel4, MemoryToPeripheral> for USART2[src]impl DMASet<Stream6<DMA1>, Channel6, MemoryToPeripheral> for DMAR<TIM5>[src]impl DMASet<Stream6<DMA1>, Channel6, PeripheralToMemory> for DMAR<TIM5>[src]impl DMASet<Stream6<DMA2>, Channel0, MemoryToMemory<u8>> for MemoryToMemory<u8>[src]impl DMASet<Stream6<DMA2>, Channel0, MemoryToMemory<u16>> for MemoryToMemory<u16>[src]impl DMASet<Stream6<DMA2>, Channel0, MemoryToMemory<u32>> for MemoryToMemory<u32>[src]impl DMASet<Stream6<DMA2>, Channel0, MemoryToPeripheral> for CCR1<TIM1>[src]impl DMASet<Stream6<DMA2>, Channel0, MemoryToPeripheral> for CCR2<TIM1>[src]impl DMASet<Stream6<DMA2>, Channel0, MemoryToPeripheral> for CCR3<TIM1>[src]impl DMASet<Stream6<DMA2>, Channel0, PeripheralToMemory> for CCR1<TIM1>[src]impl DMASet<Stream6<DMA2>, Channel0, PeripheralToMemory> for CCR2<TIM1>[src]impl DMASet<Stream6<DMA2>, Channel0, PeripheralToMemory> for CCR3<TIM1>[src]impl DMASet<Stream6<DMA2>, Channel2, MemoryToPeripheral> for CRYP[src]impl DMASet<Stream6<DMA2>, Channel4, MemoryToPeripheral> for SDIO[src]impl DMASet<Stream6<DMA2>, Channel4, PeripheralToMemory> for SDIO[src]impl DMASet<Stream6<DMA2>, Channel5, MemoryToPeripheral> for Tx<USART6>[src]impl DMASet<Stream6<DMA2>, Channel5, MemoryToPeripheral> for USART6[src]impl DMASet<Stream6<DMA2>, Channel6, MemoryToPeripheral> for CCR3<TIM1>[src]impl DMASet<Stream6<DMA2>, Channel6, PeripheralToMemory> for CCR3<TIM1>[src]impl DMASet<Stream7<DMA1>, Channel0, MemoryToPeripheral> for SPI3[src]impl DMASet<Stream7<DMA1>, Channel1, MemoryToPeripheral> for I2C1[src]impl DMASet<Stream7<DMA1>, Channel2, MemoryToPeripheral> for CCR3<TIM4>[src]impl DMASet<Stream7<DMA1>, Channel2, PeripheralToMemory> for CCR3<TIM4>[src]impl DMASet<Stream7<DMA1>, Channel3, MemoryToPeripheral> for CCR4<TIM2>[src]impl DMASet<Stream7<DMA1>, Channel3, MemoryToPeripheral> for DMAR<TIM2>[src]impl DMASet<Stream7<DMA1>, Channel3, PeripheralToMemory> for CCR4<TIM2>[src]impl DMASet<Stream7<DMA1>, Channel3, PeripheralToMemory> for DMAR<TIM2>[src]impl DMASet<Stream7<DMA1>, Channel4, MemoryToPeripheral> for UART5[src]impl DMASet<Stream7<DMA1>, Channel5, MemoryToPeripheral> for CCR3<TIM3>[src]impl DMASet<Stream7<DMA1>, Channel5, PeripheralToMemory> for CCR3<TIM3>[src]impl DMASet<Stream7<DMA1>, Channel7, MemoryToPeripheral> for I2C2[src]impl DMASet<Stream7<DMA2>, Channel0, MemoryToMemory<u8>> for MemoryToMemory<u8>[src]impl DMASet<Stream7<DMA2>, Channel0, MemoryToMemory<u16>> for MemoryToMemory<u16>[src]impl DMASet<Stream7<DMA2>, Channel0, MemoryToMemory<u32>> for MemoryToMemory<u32>[src]impl DMASet<Stream7<DMA2>, Channel1, PeripheralToMemory> for DCMI[src]impl DMASet<Stream7<DMA2>, Channel2, MemoryToPeripheral> for HASH[src]impl DMASet<Stream7<DMA2>, Channel4, MemoryToPeripheral> for Tx<USART1>[src]impl DMASet<Stream7<DMA2>, Channel4, MemoryToPeripheral> for USART1[src]impl DMASet<Stream7<DMA2>, Channel5, MemoryToPeripheral> for Tx<USART6>[src]impl DMASet<Stream7<DMA2>, Channel5, MemoryToPeripheral> for USART6[src]impl DMASet<Stream7<DMA2>, Channel7, MemoryToPeripheral> for CCR4<TIM8>[src]impl DMASet<Stream7<DMA2>, Channel7, MemoryToPeripheral> for DMAR<TIM8>[src]impl DMASet<Stream7<DMA2>, Channel7, PeripheralToMemory> for CCR4<TIM8>[src]impl DMASet<Stream7<DMA2>, Channel7, PeripheralToMemory> for DMAR<TIM8>[src]