use super::*;
use crate::{
bb,
pac::{self, DMA1, DMA2, RCC},
serial::{Rx, Tx},
};
use core::ops::Deref;
pub(crate) mod sealed {
pub trait Bits<T> {
fn bits(self) -> T;
}
pub trait Sealed {}
}
use sealed::{Bits, Sealed};
pub trait Stream: Sealed {
const NUMBER: usize;
fn clear_interrupts(&mut self);
fn clear_transfer_complete_interrupt(&mut self);
fn clear_half_transfer_interrupt(&mut self);
fn clear_transfer_error_interrupt(&mut self);
fn clear_direct_mode_error_interrupt(&mut self);
fn clear_fifo_error_interrupt(&mut self);
fn get_transfer_complete_flag() -> bool;
fn get_half_transfer_flag() -> bool;
fn set_peripheral_address(&mut self, value: u32);
fn set_memory_address(&mut self, value: u32);
fn get_memory_address(&self) -> u32;
fn set_memory_double_buffer_address(&mut self, value: u32);
fn get_memory_double_buffer_address(&self) -> u32;
fn set_number_of_transfers(&mut self, value: u16);
fn get_number_of_transfers() -> u16;
unsafe fn enable(&mut self);
fn is_enabled() -> bool;
fn disable(&mut self);
fn set_channel<C: Channel>(&mut self, channel: C);
fn set_priority(&mut self, priority: config::Priority);
unsafe fn set_memory_size(&mut self, size: u8);
unsafe fn set_peripheral_size(&mut self, size: u8);
fn set_memory_increment(&mut self, increment: bool);
fn set_peripheral_increment(&mut self, increment: bool);
fn set_direction<D: Direction>(&mut self, direction: D);
fn set_interrupts_enable(
&mut self,
transfer_complete: bool,
half_transfer: bool,
transfer_error: bool,
direct_mode_error: bool,
);
fn get_interrupts_enable() -> (bool, bool, bool, bool);
fn set_transfer_complete_interrupt_enable(&mut self, transfer_complete_interrupt: bool);
fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool);
fn set_transfer_error_interrupt_enable(&mut self, transfer_error_interrupt: bool);
fn set_direct_mode_error_interrupt_enable(&mut self, direct_mode_error_interrupt: bool);
fn set_fifo_error_interrupt_enable(&mut self, fifo_error_interrupt: bool);
fn set_double_buffer(&mut self, double_buffer: bool);
fn set_fifo_threshold(&mut self, fifo_threshold: config::FifoThreshold);
fn set_fifo_enable(&mut self, fifo_enable: bool);
fn set_memory_burst(&mut self, memory_burst: config::BurstMode);
fn set_peripheral_burst(&mut self, peripheral_burst: config::BurstMode);
fn fifo_level() -> FifoLevel;
fn current_buffer() -> CurrentBuffer;
}
pub trait Direction: Bits<u8> {
fn new() -> Self;
fn direction() -> DmaDirection;
}
pub unsafe trait PeriAddress {
type MemSize;
fn address(&self) -> u32;
}
macro_rules! address {
($(($peripheral:ty, $register:ident, $size: ty)),+ $(,)*) => {
$(
unsafe impl PeriAddress for $peripheral {
#[inline(always)]
fn address(&self) -> u32 {
&self.$register as *const _ as u32
}
type MemSize = $size;
}
)+
};
}
impl Sealed for DMA1 {}
impl Sealed for DMA2 {}
#[cfg(not(any(
feature = "stm32f411",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f410"
)))]
pub type DMARegisterBlock = pac::dma2::RegisterBlock;
#[cfg(any(
feature = "stm32f411",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f410"
))]
pub type DMARegisterBlock = pac::dma1::RegisterBlock;
pub trait Instance: Deref<Target = DMARegisterBlock> + Sealed {
fn ptr() -> *const DMARegisterBlock;
}
impl Instance for DMA1 {
#[inline(always)]
fn ptr() -> *const DMARegisterBlock {
DMA1::ptr()
}
}
impl Instance for DMA2 {
#[inline(always)]
fn ptr() -> *const DMARegisterBlock {
DMA2::ptr()
}
}
pub trait RccEnable: Sealed {
fn rcc_enable(&self);
}
impl RccEnable for pac::DMA1 {
fn rcc_enable(&self) {
unsafe {
let rcc = &(*RCC::ptr());
bb::set(&rcc.ahb1enr, 21);
cortex_m::asm::dsb();
bb::set(&rcc.ahb1rstr, 21);
bb::clear(&rcc.ahb1rstr, 21);
}
}
}
impl RccEnable for pac::DMA2 {
fn rcc_enable(&self) {
unsafe {
let rcc = &(*RCC::ptr());
bb::set(&rcc.ahb1enr, 22);
cortex_m::asm::dsb();
bb::set(&rcc.ahb1rstr, 22);
bb::clear(&rcc.ahb1rstr, 22);
}
}
}
macro_rules! tim_channels {
($($name:ident),+ $(,)*) => {
$(
pub struct $name<T> (pub T);
impl<T> Deref for $name<T> {
type Target = T;
#[inline(always)]
fn deref(&self) -> &T {
&self.0
}
}
)+
};
}
pub trait Channel: Bits<u8> {
fn new() -> Self;
}
pub unsafe trait DMASet<STREAM, CHANNEL, DIRECTION> {}
tim_channels!(CCR1, CCR2, CCR3, CCR4, DMAR, ARR);
macro_rules! dma_map {
($(($Stream:ty, $Channel:ty, $Peripheral:ty, $Dir:ty)),+ $(,)*) => {
$(
unsafe impl DMASet<$Stream, $Channel, $Dir> for $Peripheral {}
)+
};
}
#[cfg(any(
feature = "stm32f401",
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream0<DMA1>, Channel2, CCR1<pac::TIM4>, MemoryToPeripheral),
(Stream0<DMA1>, Channel2, CCR1<pac::TIM4>, PeripheralToMemory),
(Stream2<DMA1>, Channel5, CCR4<pac::TIM3>, MemoryToPeripheral),
(Stream2<DMA1>, Channel5, CCR4<pac::TIM3>, PeripheralToMemory),
(Stream2<DMA1>, Channel5, DMAR<pac::TIM3>, MemoryToPeripheral),
(Stream2<DMA1>, Channel5, DMAR<pac::TIM3>, PeripheralToMemory),
(Stream3<DMA1>, Channel2, CCR2<pac::TIM4>, MemoryToPeripheral),
(Stream3<DMA1>, Channel2, CCR2<pac::TIM4>, PeripheralToMemory),
(Stream4<DMA1>, Channel5, CCR1<pac::TIM3>, MemoryToPeripheral),
(Stream4<DMA1>, Channel5, CCR1<pac::TIM3>, PeripheralToMemory),
(Stream4<DMA1>, Channel5, DMAR<pac::TIM3>, MemoryToPeripheral),
(Stream4<DMA1>, Channel5, DMAR<pac::TIM3>, PeripheralToMemory),
(Stream5<DMA1>, Channel3, CCR1<pac::TIM2>, MemoryToPeripheral),
(Stream5<DMA1>, Channel3, CCR1<pac::TIM2>, PeripheralToMemory),
(Stream5<DMA1>, Channel5, CCR2<pac::TIM3>, MemoryToPeripheral),
(Stream5<DMA1>, Channel5, CCR2<pac::TIM3>, PeripheralToMemory),
(Stream6<DMA1>, Channel2, DMAR<pac::TIM4>, MemoryToPeripheral),
(Stream6<DMA1>, Channel2, DMAR<pac::TIM4>, PeripheralToMemory),
(Stream6<DMA1>, Channel3, CCR2<pac::TIM2>, MemoryToPeripheral),
(Stream6<DMA1>, Channel3, CCR2<pac::TIM2>, PeripheralToMemory),
(Stream6<DMA1>, Channel3, CCR4<pac::TIM2>, MemoryToPeripheral),
(Stream6<DMA1>, Channel3, CCR4<pac::TIM2>, PeripheralToMemory),
(Stream7<DMA1>, Channel2, CCR3<pac::TIM4>, MemoryToPeripheral),
(Stream7<DMA1>, Channel2, CCR3<pac::TIM4>, PeripheralToMemory),
(Stream7<DMA1>, Channel5, CCR3<pac::TIM3>, MemoryToPeripheral),
(Stream7<DMA1>, Channel5, CCR3<pac::TIM3>, PeripheralToMemory),
(Stream0<DMA1>, Channel0, pac::SPI3, PeripheralToMemory),
(Stream2<DMA1>, Channel0, pac::SPI3, PeripheralToMemory),
(Stream4<DMA1>, Channel3, pac::I2C3, MemoryToPeripheral),
(Stream5<DMA1>, Channel0, pac::SPI3, MemoryToPeripheral),
(Stream7<DMA1>, Channel0, pac::SPI3, MemoryToPeripheral),
);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
address!(
(CCR1<pac::TIM4>, ccr1, u16),
(CCR4<pac::TIM3>, ccr4, u16),
(CCR1<pac::TIM2>, ccr1, u16),
(CCR1<pac::TIM3>, ccr1, u16),
(CCR2<pac::TIM2>, ccr2, u16),
(CCR2<pac::TIM3>, ccr2, u16),
(CCR2<pac::TIM4>, ccr2, u16),
(CCR3<pac::TIM3>, ccr3, u16),
(CCR3<pac::TIM4>, ccr3, u16),
(CCR4<pac::TIM2>, ccr4, u16),
(DMAR<pac::TIM3>, dmar, u16),
(DMAR<pac::TIM4>, dmar, u16),
(pac::SPI3, dr, u8),
(pac::I2C3, dr, u8),
);
#[cfg(not(any(feature = "stm32f410")))]
dma_map!(
(Stream3<DMA2>, Channel4, pac::SDIO, MemoryToPeripheral),
(Stream3<DMA2>, Channel4, pac::SDIO, PeripheralToMemory),
(Stream6<DMA2>, Channel4, pac::SDIO, MemoryToPeripheral),
(Stream6<DMA2>, Channel4, pac::SDIO, PeripheralToMemory),
);
#[cfg(not(any(feature = "stm32f410")))]
address!((pac::SDIO, fifo, u32),);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f410",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream0<DMA1>, Channel6, CCR3<pac::TIM5>, MemoryToPeripheral),
(Stream0<DMA1>, Channel6, CCR3<pac::TIM5>, PeripheralToMemory),
(Stream0<DMA1>, Channel6, DMAR<pac::TIM5>, MemoryToPeripheral),
(Stream0<DMA1>, Channel6, DMAR<pac::TIM5>, PeripheralToMemory),
(Stream1<DMA1>, Channel6, CCR4<pac::TIM5>, MemoryToPeripheral),
(Stream1<DMA1>, Channel6, CCR4<pac::TIM5>, PeripheralToMemory),
(Stream1<DMA1>, Channel6, DMAR<pac::TIM5>, MemoryToPeripheral),
(Stream1<DMA1>, Channel6, DMAR<pac::TIM5>, PeripheralToMemory),
(Stream2<DMA1>, Channel6, CCR1<pac::TIM5>, MemoryToPeripheral),
(Stream2<DMA1>, Channel6, CCR1<pac::TIM5>, PeripheralToMemory),
(Stream3<DMA1>, Channel6, CCR4<pac::TIM5>, MemoryToPeripheral),
(Stream3<DMA1>, Channel6, CCR4<pac::TIM5>, PeripheralToMemory),
(Stream3<DMA1>, Channel6, DMAR<pac::TIM5>, MemoryToPeripheral),
(Stream3<DMA1>, Channel6, DMAR<pac::TIM5>, PeripheralToMemory),
(Stream4<DMA1>, Channel6, CCR2<pac::TIM5>, MemoryToPeripheral),
(Stream4<DMA1>, Channel6, CCR2<pac::TIM5>, PeripheralToMemory),
(Stream6<DMA1>, Channel6, DMAR<pac::TIM5>, MemoryToPeripheral),
(Stream6<DMA1>, Channel6, DMAR<pac::TIM5>, PeripheralToMemory),
(Stream0<DMA2>, Channel6, DMAR<pac::TIM1>, MemoryToPeripheral),
(Stream0<DMA2>, Channel6, DMAR<pac::TIM1>, PeripheralToMemory),
(Stream1<DMA2>, Channel6, CCR1<pac::TIM1>, MemoryToPeripheral),
(Stream1<DMA2>, Channel6, CCR1<pac::TIM1>, PeripheralToMemory),
(Stream2<DMA2>, Channel6, CCR2<pac::TIM1>, MemoryToPeripheral),
(Stream2<DMA2>, Channel6, CCR2<pac::TIM1>, PeripheralToMemory),
(Stream3<DMA2>, Channel6, CCR1<pac::TIM1>, MemoryToPeripheral),
(Stream3<DMA2>, Channel6, CCR1<pac::TIM1>, PeripheralToMemory),
(Stream4<DMA2>, Channel6, CCR4<pac::TIM1>, MemoryToPeripheral),
(Stream4<DMA2>, Channel6, CCR4<pac::TIM1>, PeripheralToMemory),
(Stream4<DMA2>, Channel6, DMAR<pac::TIM1>, MemoryToPeripheral),
(Stream4<DMA2>, Channel6, DMAR<pac::TIM1>, PeripheralToMemory),
(Stream5<DMA2>, Channel6, DMAR<pac::TIM1>, MemoryToPeripheral),
(Stream5<DMA2>, Channel6, DMAR<pac::TIM1>, PeripheralToMemory),
(Stream6<DMA2>, Channel0, CCR1<pac::TIM1>, MemoryToPeripheral),
(Stream6<DMA2>, Channel0, CCR1<pac::TIM1>, PeripheralToMemory),
(Stream6<DMA2>, Channel0, CCR2<pac::TIM1>, MemoryToPeripheral),
(Stream6<DMA2>, Channel0, CCR2<pac::TIM1>, PeripheralToMemory),
(Stream6<DMA2>, Channel0, CCR3<pac::TIM1>, MemoryToPeripheral),
(Stream6<DMA2>, Channel0, CCR3<pac::TIM1>, PeripheralToMemory),
(Stream6<DMA2>, Channel6, CCR3<pac::TIM1>, MemoryToPeripheral),
(Stream6<DMA2>, Channel6, CCR3<pac::TIM1>, PeripheralToMemory),
(Stream0<DMA1>, Channel1, pac::I2C1, PeripheralToMemory),
(Stream2<DMA1>, Channel7, pac::I2C2, PeripheralToMemory),
(Stream3<DMA1>, Channel0, pac::SPI2, PeripheralToMemory),
(Stream3<DMA1>, Channel7, pac::I2C2, PeripheralToMemory),
(Stream4<DMA1>, Channel0, pac::SPI2, MemoryToPeripheral),
(Stream5<DMA1>, Channel1, pac::I2C1, PeripheralToMemory),
(Stream5<DMA1>, Channel4, pac::USART2, PeripheralToMemory),
(Stream5<DMA1>, Channel4, Rx<pac::USART2>, PeripheralToMemory),
(Stream6<DMA1>, Channel4, pac::USART2, MemoryToPeripheral),
(Stream6<DMA1>, Channel4, Tx<pac::USART2>, MemoryToPeripheral),
(Stream7<DMA1>, Channel7, pac::I2C2, MemoryToPeripheral),
(Stream0<DMA2>, Channel0, pac::ADC1, PeripheralToMemory),
(Stream0<DMA2>, Channel3, pac::SPI1, PeripheralToMemory),
(Stream1<DMA2>, Channel5, pac::USART6, PeripheralToMemory),
(Stream1<DMA2>, Channel5, Rx<pac::USART6>, PeripheralToMemory),
(Stream2<DMA2>, Channel3, pac::SPI1, PeripheralToMemory),
(Stream2<DMA2>, Channel4, pac::USART1, PeripheralToMemory),
(Stream2<DMA2>, Channel4, Rx<pac::USART1>, PeripheralToMemory),
(Stream2<DMA2>, Channel5, pac::USART6, PeripheralToMemory),
(Stream2<DMA2>, Channel5, Rx<pac::USART6>, PeripheralToMemory),
(Stream4<DMA2>, Channel0, pac::ADC1, PeripheralToMemory),
(Stream5<DMA2>, Channel4, pac::USART1, PeripheralToMemory),
(Stream5<DMA2>, Channel4, Rx<pac::USART1>, PeripheralToMemory),
(Stream6<DMA2>, Channel5, pac::USART6, MemoryToPeripheral),
(Stream6<DMA2>, Channel5, Tx<pac::USART6>, MemoryToPeripheral),
(Stream7<DMA2>, Channel4, pac::USART1, MemoryToPeripheral),
(Stream7<DMA2>, Channel4, Tx<pac::USART1>, MemoryToPeripheral),
(Stream7<DMA2>, Channel5, pac::USART6, MemoryToPeripheral),
(Stream7<DMA2>, Channel5, Tx<pac::USART6>, MemoryToPeripheral),
(
Stream0<DMA2>,
Channel0,
MemoryToMemory<u8>,
MemoryToMemory<u8>
),
(
Stream1<DMA2>,
Channel0,
MemoryToMemory<u8>,
MemoryToMemory<u8>
),
(
Stream2<DMA2>,
Channel0,
MemoryToMemory<u8>,
MemoryToMemory<u8>
),
(
Stream3<DMA2>,
Channel0,
MemoryToMemory<u8>,
MemoryToMemory<u8>
),
(
Stream4<DMA2>,
Channel0,
MemoryToMemory<u8>,
MemoryToMemory<u8>
),
(
Stream5<DMA2>,
Channel0,
MemoryToMemory<u8>,
MemoryToMemory<u8>
),
(
Stream6<DMA2>,
Channel0,
MemoryToMemory<u8>,
MemoryToMemory<u8>
),
(
Stream7<DMA2>,
Channel0,
MemoryToMemory<u8>,
MemoryToMemory<u8>
),
(
Stream0<DMA2>,
Channel0,
MemoryToMemory<u16>,
MemoryToMemory<u16>
),
(
Stream1<DMA2>,
Channel0,
MemoryToMemory<u16>,
MemoryToMemory<u16>
),
(
Stream2<DMA2>,
Channel0,
MemoryToMemory<u16>,
MemoryToMemory<u16>
),
(
Stream3<DMA2>,
Channel0,
MemoryToMemory<u16>,
MemoryToMemory<u16>
),
(
Stream4<DMA2>,
Channel0,
MemoryToMemory<u16>,
MemoryToMemory<u16>
),
(
Stream5<DMA2>,
Channel0,
MemoryToMemory<u16>,
MemoryToMemory<u16>
),
(
Stream6<DMA2>,
Channel0,
MemoryToMemory<u16>,
MemoryToMemory<u16>
),
(
Stream7<DMA2>,
Channel0,
MemoryToMemory<u16>,
MemoryToMemory<u16>
),
(
Stream0<DMA2>,
Channel0,
MemoryToMemory<u32>,
MemoryToMemory<u32>
),
(
Stream1<DMA2>,
Channel0,
MemoryToMemory<u32>,
MemoryToMemory<u32>
),
(
Stream2<DMA2>,
Channel0,
MemoryToMemory<u32>,
MemoryToMemory<u32>
),
(
Stream3<DMA2>,
Channel0,
MemoryToMemory<u32>,
MemoryToMemory<u32>
),
(
Stream4<DMA2>,
Channel0,
MemoryToMemory<u32>,
MemoryToMemory<u32>
),
(
Stream5<DMA2>,
Channel0,
MemoryToMemory<u32>,
MemoryToMemory<u32>
),
(
Stream6<DMA2>,
Channel0,
MemoryToMemory<u32>,
MemoryToMemory<u32>
),
(
Stream7<DMA2>,
Channel0,
MemoryToMemory<u32>,
MemoryToMemory<u32>
),
);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f410",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
address!(
(CCR1<pac::TIM1>, ccr1, u16),
(CCR2<pac::TIM1>, ccr2, u16),
(CCR3<pac::TIM1>, ccr3, u16),
(CCR4<pac::TIM1>, ccr4, u16),
(DMAR<pac::TIM1>, dmar, u16),
(CCR1<pac::TIM5>, ccr1, u16),
(CCR2<pac::TIM5>, ccr2, u16),
(CCR3<pac::TIM5>, ccr3, u16),
(CCR4<pac::TIM5>, ccr4, u16),
(DMAR<pac::TIM5>, dmar, u16),
(pac::ADC1, dr, u16),
(pac::I2C1, dr, u8),
(pac::I2C2, dr, u8),
(pac::SPI1, dr, u8),
(pac::SPI2, dr, u8),
(pac::USART1, dr, u8),
(pac::USART2, dr, u8),
(pac::USART6, dr, u8),
);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f446",
))]
dma_map!(
(Stream1<DMA1>, Channel1, pac::I2C3, PeripheralToMemory),
(Stream2<DMA1>, Channel3, pac::I2C3, PeripheralToMemory),
);
#[cfg(any(feature = "stm32f401", feature = "stm32f411",))]
dma_map!(
(Stream1<DMA1>, Channel3, CCR3<pac::TIM2>, MemoryToPeripheral),
(Stream1<DMA1>, Channel3, CCR3<pac::TIM2>, PeripheralToMemory),
(Stream1<DMA1>, Channel3, DMAR<pac::TIM2>, MemoryToPeripheral),
(Stream1<DMA1>, Channel3, DMAR<pac::TIM2>, PeripheralToMemory),
(Stream7<DMA1>, Channel3, CCR4<pac::TIM2>, MemoryToPeripheral),
(Stream7<DMA1>, Channel3, CCR4<pac::TIM2>, PeripheralToMemory),
(Stream7<DMA1>, Channel3, DMAR<pac::TIM2>, MemoryToPeripheral),
(Stream7<DMA1>, Channel3, DMAR<pac::TIM2>, PeripheralToMemory),
);
#[cfg(any(feature = "stm32f401", feature = "stm32f411",))]
address!((CCR3<pac::TIM2>, ccr3, u16), (DMAR<pac::TIM2>, dmar, u16),);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
))]
dma_map!((Stream5<DMA1>, Channel6, pac::I2C3, MemoryToPeripheral),);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream6<DMA1>, Channel1, pac::I2C1, MemoryToPeripheral),
(Stream7<DMA1>, Channel1, pac::I2C1, MemoryToPeripheral),
(Stream3<DMA2>, Channel3, pac::SPI1, MemoryToPeripheral),
(Stream5<DMA2>, Channel3, pac::SPI1, MemoryToPeripheral),
);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream0<DMA2>, Channel4, pac::SPI4, PeripheralToMemory),
(Stream1<DMA2>, Channel4, pac::SPI4, MemoryToPeripheral),
(Stream3<DMA2>, Channel5, pac::SPI4, PeripheralToMemory),
(Stream4<DMA2>, Channel5, pac::SPI4, MemoryToPeripheral),
);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
address!((pac::SPI4, dr, u8),);
#[cfg(any(
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream0<DMA1>, Channel4, pac::UART5, PeripheralToMemory),
(Stream2<DMA1>, Channel4, pac::UART4, PeripheralToMemory),
(Stream4<DMA1>, Channel4, pac::UART4, MemoryToPeripheral),
);
#[cfg(any(
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
address!(
(pac::UART4, dr, u8),
(pac::UART5, dr, u8),
);
#[cfg(any(
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream1<DMA1>, Channel3, DMAR<pac::TIM2>, MemoryToPeripheral),
(Stream1<DMA1>, Channel3, DMAR<pac::TIM2>, PeripheralToMemory),
(Stream1<DMA1>, Channel3, CCR3<pac::TIM2>, MemoryToPeripheral),
(Stream1<DMA1>, Channel3, CCR3<pac::TIM2>, PeripheralToMemory),
(Stream7<DMA1>, Channel3, DMAR<pac::TIM2>, MemoryToPeripheral),
(Stream7<DMA1>, Channel3, DMAR<pac::TIM2>, PeripheralToMemory),
(Stream7<DMA1>, Channel3, CCR4<pac::TIM2>, MemoryToPeripheral),
(Stream7<DMA1>, Channel3, CCR4<pac::TIM2>, PeripheralToMemory),
(Stream1<DMA2>, Channel7, DMAR<pac::TIM8>, MemoryToPeripheral),
(Stream1<DMA2>, Channel7, DMAR<pac::TIM8>, PeripheralToMemory),
(Stream2<DMA2>, Channel0, CCR1<pac::TIM8>, MemoryToPeripheral),
(Stream2<DMA2>, Channel0, CCR1<pac::TIM8>, PeripheralToMemory),
(Stream2<DMA2>, Channel0, CCR2<pac::TIM8>, MemoryToPeripheral),
(Stream2<DMA2>, Channel0, CCR2<pac::TIM8>, PeripheralToMemory),
(Stream2<DMA2>, Channel0, CCR3<pac::TIM8>, MemoryToPeripheral),
(Stream2<DMA2>, Channel0, CCR3<pac::TIM8>, PeripheralToMemory),
(Stream2<DMA2>, Channel7, CCR1<pac::TIM8>, MemoryToPeripheral),
(Stream2<DMA2>, Channel7, CCR1<pac::TIM8>, PeripheralToMemory),
(Stream3<DMA2>, Channel7, CCR2<pac::TIM8>, MemoryToPeripheral),
(Stream3<DMA2>, Channel7, CCR2<pac::TIM8>, PeripheralToMemory),
(Stream4<DMA2>, Channel7, CCR3<pac::TIM8>, MemoryToPeripheral),
(Stream4<DMA2>, Channel7, CCR3<pac::TIM8>, PeripheralToMemory),
(Stream7<DMA2>, Channel7, CCR4<pac::TIM8>, MemoryToPeripheral),
(Stream7<DMA2>, Channel7, CCR4<pac::TIM8>, PeripheralToMemory),
(Stream7<DMA2>, Channel7, DMAR<pac::TIM8>, MemoryToPeripheral),
(Stream7<DMA2>, Channel7, DMAR<pac::TIM8>, PeripheralToMemory),
(Stream1<DMA1>, Channel4, pac::USART3, PeripheralToMemory),
(Stream3<DMA1>, Channel4, pac::USART3, MemoryToPeripheral),
(Stream4<DMA1>, Channel7, pac::USART3, MemoryToPeripheral),
);
#[cfg(any(
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
address!(
(CCR1<pac::TIM8>, ccr1, u16),
(CCR2<pac::TIM8>, ccr2, u16),
(CCR3<pac::TIM8>, ccr3, u16),
(CCR4<pac::TIM8>, ccr4, u16),
(DMAR<pac::TIM8>, dmar, u16),
(CCR3<pac::TIM2>, ccr3, u16),
(DMAR<pac::TIM2>, dmar, u16),
(pac::USART3, dr, u8),
);
#[cfg(any(
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream2<DMA1>, Channel3, pac::I2C3, PeripheralToMemory),
(Stream5<DMA2>, Channel2, pac::CRYP, PeripheralToMemory),
(Stream6<DMA2>, Channel2, pac::CRYP, MemoryToPeripheral),
(Stream7<DMA2>, Channel2, pac::HASH, MemoryToPeripheral),
);
#[cfg(any(
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f469",
feature = "stm32f479",
))]
address!((pac::HASH, din, u32), (pac::CRYP, din, u32),);
#[cfg(any(
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream7<DMA1>, Channel4, pac::UART5, MemoryToPeripheral),
(Stream0<DMA2>, Channel2, pac::ADC3, PeripheralToMemory),
(Stream1<DMA2>, Channel1, pac::DCMI, PeripheralToMemory),
(Stream1<DMA2>, Channel2, pac::ADC3, PeripheralToMemory),
(Stream2<DMA2>, Channel1, pac::ADC2, PeripheralToMemory),
(Stream3<DMA2>, Channel1, pac::ADC2, PeripheralToMemory),
(Stream7<DMA2>, Channel1, pac::DCMI, PeripheralToMemory),
);
#[cfg(any(
feature = "stm32f417",
feature = "stm32f415",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
address!(
(pac::ADC2, dr, u16),
(pac::ADC3, dr, u16),
(pac::DCMI, dr, u32),
);
#[cfg(any(
feature = "stm32f410",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
))]
dma_map!(
(Stream1<DMA1>, Channel0, pac::I2C1, MemoryToPeripheral),
(Stream6<DMA1>, Channel1, pac::I2C1, MemoryToPeripheral),
(Stream7<DMA1>, Channel1, pac::I2C1, MemoryToPeripheral),
(Stream7<DMA1>, Channel6, pac::USART2, PeripheralToMemory),
(Stream2<DMA2>, Channel2, pac::SPI1, MemoryToPeripheral),
(Stream3<DMA2>, Channel3, pac::SPI1, MemoryToPeripheral),
(Stream5<DMA2>, Channel3, pac::SPI1, MemoryToPeripheral),
(Stream5<DMA2>, Channel5, pac::SPI5, MemoryToPeripheral),
);
#[cfg(any(
feature = "stm32f410",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream3<DMA2>, Channel2, pac::SPI5, PeripheralToMemory),
(Stream4<DMA2>, Channel2, pac::SPI5, MemoryToPeripheral),
(Stream5<DMA2>, Channel7, pac::SPI5, PeripheralToMemory),
(Stream6<DMA2>, Channel7, pac::SPI5, MemoryToPeripheral),
);
#[cfg(any(
feature = "stm32f410",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f469",
feature = "stm32f479",
))]
address!((pac::SPI5, dr, u8),);
#[cfg(any(
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
))]
dma_map!((Stream4<DMA2>, Channel4, pac::SPI4, PeripheralToMemory),);
#[cfg(any(
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream7<DMA2>, Channel3, pac::QUADSPI, MemoryToPeripheral),
(Stream7<DMA2>, Channel3, pac::QUADSPI, PeripheralToMemory),
);
#[cfg(any(
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479",
))]
address!((pac::QUADSPI, dr, u32),);
#[cfg(any(
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream0<DMA1>, Channel5, pac::UART8, MemoryToPeripheral),
(Stream1<DMA1>, Channel5, pac::UART7, MemoryToPeripheral),
(Stream3<DMA1>, Channel5, pac::UART7, PeripheralToMemory),
(Stream6<DMA1>, Channel5, pac::UART8, PeripheralToMemory),
);
#[cfg(any(
feature = "stm32f413",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f469",
feature = "stm32f479",
))]
address!((pac::UART7, dr, u8), (pac::UART8, dr, u8),);
#[cfg(any(feature = "stm32f413", feature = "stm32f423",))]
dma_map!(
(Stream7<DMA1>, Channel8, pac::UART5, MemoryToPeripheral),
(Stream0<DMA2>, Channel1, pac::UART9, MemoryToPeripheral),
(Stream0<DMA2>, Channel5, pac::UART10, PeripheralToMemory),
(Stream3<DMA2>, Channel9, pac::UART10, PeripheralToMemory),
(Stream5<DMA2>, Channel9, pac::UART10, MemoryToPeripheral),
(Stream7<DMA2>, Channel0, pac::UART9, PeripheralToMemory),
(Stream7<DMA2>, Channel6, pac::UART10, MemoryToPeripheral),
);
#[cfg(any(feature = "stm32f413", feature = "stm32f423",))]
address!(
(pac::UART9, dr, u8),
(pac::UART10, dr, u8),
);
#[cfg(any(
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f469",
feature = "stm32f479",
))]
dma_map!(
(Stream5<DMA2>, Channel1, pac::SPI6, MemoryToPeripheral),
(Stream6<DMA2>, Channel1, pac::SPI6, PeripheralToMemory),
);
#[cfg(any(
feature = "stm32f427",
feature = "stm32f439",
feature = "stm32f437",
feature = "stm32f429",
feature = "stm32f469",
feature = "stm32f479",
))]
address!((pac::SPI6, dr, u8),);