stm32f4/stm32f407/
otg_hs_global.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    gotgctl: GOTGCTL,
6    gotgint: GOTGINT,
7    gahbcfg: GAHBCFG,
8    gusbcfg: GUSBCFG,
9    grstctl: GRSTCTL,
10    gintsts: GINTSTS,
11    gintmsk: GINTMSK,
12    _reserved_7_grxstsr: [u8; 0x04],
13    _reserved_8_grxstsp: [u8; 0x04],
14    grxfsiz: GRXFSIZ,
15    _reserved_10_dieptxf0: [u8; 0x04],
16    hnptxsts: HNPTXSTS,
17    _reserved12: [u8; 0x08],
18    gccfg: GCCFG,
19    cid: CID,
20    _reserved14: [u8; 0xc0],
21    hptxfsiz: HPTXFSIZ,
22    dieptxf: [DIEPTXF; 5],
23}
24impl RegisterBlock {
25    ///0x00 - OTG_HS control and status register
26    #[inline(always)]
27    pub const fn gotgctl(&self) -> &GOTGCTL {
28        &self.gotgctl
29    }
30    ///0x04 - OTG_HS interrupt register
31    #[inline(always)]
32    pub const fn gotgint(&self) -> &GOTGINT {
33        &self.gotgint
34    }
35    ///0x08 - OTG_HS AHB configuration register
36    #[inline(always)]
37    pub const fn gahbcfg(&self) -> &GAHBCFG {
38        &self.gahbcfg
39    }
40    ///0x0c - OTG_HS USB configuration register
41    #[inline(always)]
42    pub const fn gusbcfg(&self) -> &GUSBCFG {
43        &self.gusbcfg
44    }
45    ///0x10 - OTG_HS reset register
46    #[inline(always)]
47    pub const fn grstctl(&self) -> &GRSTCTL {
48        &self.grstctl
49    }
50    ///0x14 - OTG_HS core interrupt register
51    #[inline(always)]
52    pub const fn gintsts(&self) -> &GINTSTS {
53        &self.gintsts
54    }
55    ///0x18 - OTG_HS interrupt mask register
56    #[inline(always)]
57    pub const fn gintmsk(&self) -> &GINTMSK {
58        &self.gintmsk
59    }
60    ///0x1c - OTG_HS Receive status debug read register (peripheral mode mode)
61    #[inline(always)]
62    pub const fn grxstsr_device(&self) -> &GRXSTSR_DEVICE {
63        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
64    }
65    ///0x1c - OTG_HS Receive status debug read register (host mode)
66    #[inline(always)]
67    pub const fn grxstsr_host(&self) -> &GRXSTSR_HOST {
68        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
69    }
70    ///0x20 - OTG_HS status read and pop register (peripheral mode)
71    #[inline(always)]
72    pub const fn grxstsp_device(&self) -> &GRXSTSP_DEVICE {
73        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
74    }
75    ///0x20 - OTG_HS status read and pop register (host mode)
76    #[inline(always)]
77    pub const fn grxstsp_host(&self) -> &GRXSTSP_HOST {
78        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
79    }
80    ///0x24 - OTG_HS Receive FIFO size register
81    #[inline(always)]
82    pub const fn grxfsiz(&self) -> &GRXFSIZ {
83        &self.grxfsiz
84    }
85    ///0x28 - Endpoint 0 transmit FIFO size (peripheral mode)
86    #[inline(always)]
87    pub const fn dieptxf0(&self) -> &DIEPTXF0 {
88        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
89    }
90    ///0x28 - OTG_HS nonperiodic transmit FIFO size register (host mode)
91    #[inline(always)]
92    pub const fn hnptxfsiz(&self) -> &HNPTXFSIZ {
93        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
94    }
95    ///0x2c - OTG_HS nonperiodic transmit FIFO/queue status register
96    #[inline(always)]
97    pub const fn hnptxsts(&self) -> &HNPTXSTS {
98        &self.hnptxsts
99    }
100    ///0x38 - OTG_HS general core configuration register
101    #[inline(always)]
102    pub const fn gccfg(&self) -> &GCCFG {
103        &self.gccfg
104    }
105    ///0x3c - OTG_HS core ID register
106    #[inline(always)]
107    pub const fn cid(&self) -> &CID {
108        &self.cid
109    }
110    ///0x100 - OTG_HS Host periodic transmit FIFO size register
111    #[inline(always)]
112    pub const fn hptxfsiz(&self) -> &HPTXFSIZ {
113        &self.hptxfsiz
114    }
115    ///0x104..0x118 - OTG_HS device IN endpoint transmit FIFO size register
116    ///
117    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `DIEPTXF1` register.</div>
118    #[inline(always)]
119    pub const fn dieptxf(&self, n: usize) -> &DIEPTXF {
120        &self.dieptxf[n]
121    }
122    ///Iterator for array of:
123    ///0x104..0x118 - OTG_HS device IN endpoint transmit FIFO size register
124    #[inline(always)]
125    pub fn dieptxf_iter(&self) -> impl Iterator<Item = &DIEPTXF> {
126        self.dieptxf.iter()
127    }
128    ///0x104 - OTG_HS device IN endpoint transmit FIFO size register
129    #[inline(always)]
130    pub const fn dieptxf1(&self) -> &DIEPTXF {
131        self.dieptxf(0)
132    }
133    ///0x108 - OTG_HS device IN endpoint transmit FIFO size register
134    #[inline(always)]
135    pub const fn dieptxf2(&self) -> &DIEPTXF {
136        self.dieptxf(1)
137    }
138    ///0x10c - OTG_HS device IN endpoint transmit FIFO size register
139    #[inline(always)]
140    pub const fn dieptxf3(&self) -> &DIEPTXF {
141        self.dieptxf(2)
142    }
143    ///0x110 - OTG_HS device IN endpoint transmit FIFO size register
144    #[inline(always)]
145    pub const fn dieptxf4(&self) -> &DIEPTXF {
146        self.dieptxf(3)
147    }
148    ///0x114 - OTG_HS device IN endpoint transmit FIFO size register
149    #[inline(always)]
150    pub const fn dieptxf5(&self) -> &DIEPTXF {
151        self.dieptxf(4)
152    }
153}
154/**GOTGCTL (rw) register accessor: OTG_HS control and status register
155
156You can [`read`](crate::Reg::read) this register and get [`gotgctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gotgctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
157
158See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GOTGCTL)
159
160For information about available fields see [`mod@gotgctl`] module*/
161pub type GOTGCTL = crate::Reg<gotgctl::GOTGCTLrs>;
162///OTG_HS control and status register
163pub mod gotgctl;
164/**GOTGINT (rw) register accessor: OTG_HS interrupt register
165
166You can [`read`](crate::Reg::read) this register and get [`gotgint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gotgint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GOTGINT)
169
170For information about available fields see [`mod@gotgint`] module*/
171pub type GOTGINT = crate::Reg<gotgint::GOTGINTrs>;
172///OTG_HS interrupt register
173pub mod gotgint;
174/**GAHBCFG (rw) register accessor: OTG_HS AHB configuration register
175
176You can [`read`](crate::Reg::read) this register and get [`gahbcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gahbcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
177
178See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GAHBCFG)
179
180For information about available fields see [`mod@gahbcfg`] module*/
181pub type GAHBCFG = crate::Reg<gahbcfg::GAHBCFGrs>;
182///OTG_HS AHB configuration register
183pub mod gahbcfg;
184/**GUSBCFG (rw) register accessor: OTG_HS USB configuration register
185
186You can [`read`](crate::Reg::read) this register and get [`gusbcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gusbcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
187
188See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GUSBCFG)
189
190For information about available fields see [`mod@gusbcfg`] module*/
191pub type GUSBCFG = crate::Reg<gusbcfg::GUSBCFGrs>;
192///OTG_HS USB configuration register
193pub mod gusbcfg;
194/**GRSTCTL (rw) register accessor: OTG_HS reset register
195
196You can [`read`](crate::Reg::read) this register and get [`grstctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grstctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
197
198See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GRSTCTL)
199
200For information about available fields see [`mod@grstctl`] module*/
201pub type GRSTCTL = crate::Reg<grstctl::GRSTCTLrs>;
202///OTG_HS reset register
203pub mod grstctl;
204/**GINTSTS (rw) register accessor: OTG_HS core interrupt register
205
206You can [`read`](crate::Reg::read) this register and get [`gintsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gintsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
207
208See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GINTSTS)
209
210For information about available fields see [`mod@gintsts`] module*/
211pub type GINTSTS = crate::Reg<gintsts::GINTSTSrs>;
212///OTG_HS core interrupt register
213pub mod gintsts;
214/**GINTMSK (rw) register accessor: OTG_HS interrupt mask register
215
216You can [`read`](crate::Reg::read) this register and get [`gintmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gintmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
217
218See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GINTMSK)
219
220For information about available fields see [`mod@gintmsk`] module*/
221pub type GINTMSK = crate::Reg<gintmsk::GINTMSKrs>;
222///OTG_HS interrupt mask register
223pub mod gintmsk;
224/**GRXSTSR_Host (r) register accessor: OTG_HS Receive status debug read register (host mode)
225
226You can [`read`](crate::Reg::read) this register and get [`grxstsr_host::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
227
228See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GRXSTSR_Host)
229
230For information about available fields see [`mod@grxstsr_host`] module*/
231#[doc(alias = "GRXSTSR_Host")]
232pub type GRXSTSR_HOST = crate::Reg<grxstsr_host::GRXSTSR_HOSTrs>;
233///OTG_HS Receive status debug read register (host mode)
234pub mod grxstsr_host;
235/**GRXSTSP_Host (r) register accessor: OTG_HS status read and pop register (host mode)
236
237You can [`read`](crate::Reg::read) this register and get [`grxstsp_host::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
238
239See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GRXSTSP_Host)
240
241For information about available fields see [`mod@grxstsp_host`] module*/
242#[doc(alias = "GRXSTSP_Host")]
243pub type GRXSTSP_HOST = crate::Reg<grxstsp_host::GRXSTSP_HOSTrs>;
244///OTG_HS status read and pop register (host mode)
245pub mod grxstsp_host;
246/**GRXFSIZ (rw) register accessor: OTG_HS Receive FIFO size register
247
248You can [`read`](crate::Reg::read) this register and get [`grxfsiz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxfsiz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
249
250See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GRXFSIZ)
251
252For information about available fields see [`mod@grxfsiz`] module*/
253pub type GRXFSIZ = crate::Reg<grxfsiz::GRXFSIZrs>;
254///OTG_HS Receive FIFO size register
255pub mod grxfsiz;
256/**HNPTXFSIZ (rw) register accessor: OTG_HS nonperiodic transmit FIFO size register (host mode)
257
258You can [`read`](crate::Reg::read) this register and get [`hnptxfsiz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hnptxfsiz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
259
260See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:HNPTXFSIZ)
261
262For information about available fields see [`mod@hnptxfsiz`] module*/
263pub type HNPTXFSIZ = crate::Reg<hnptxfsiz::HNPTXFSIZrs>;
264///OTG_HS nonperiodic transmit FIFO size register (host mode)
265pub mod hnptxfsiz;
266/**DIEPTXF0 (rw) register accessor: Endpoint 0 transmit FIFO size (peripheral mode)
267
268You can [`read`](crate::Reg::read) this register and get [`dieptxf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dieptxf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
269
270See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:DIEPTXF0)
271
272For information about available fields see [`mod@dieptxf0`] module*/
273pub type DIEPTXF0 = crate::Reg<dieptxf0::DIEPTXF0rs>;
274///Endpoint 0 transmit FIFO size (peripheral mode)
275pub mod dieptxf0;
276/**HNPTXSTS (r) register accessor: OTG_HS nonperiodic transmit FIFO/queue status register
277
278You can [`read`](crate::Reg::read) this register and get [`hnptxsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
279
280See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:HNPTXSTS)
281
282For information about available fields see [`mod@hnptxsts`] module*/
283pub type HNPTXSTS = crate::Reg<hnptxsts::HNPTXSTSrs>;
284///OTG_HS nonperiodic transmit FIFO/queue status register
285pub mod hnptxsts;
286/**GCCFG (rw) register accessor: OTG_HS general core configuration register
287
288You can [`read`](crate::Reg::read) this register and get [`gccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
289
290See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GCCFG)
291
292For information about available fields see [`mod@gccfg`] module*/
293pub type GCCFG = crate::Reg<gccfg::GCCFGrs>;
294///OTG_HS general core configuration register
295pub mod gccfg;
296/**CID (rw) register accessor: OTG_HS core ID register
297
298You can [`read`](crate::Reg::read) this register and get [`cid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
299
300See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:CID)
301
302For information about available fields see [`mod@cid`] module*/
303pub type CID = crate::Reg<cid::CIDrs>;
304///OTG_HS core ID register
305pub mod cid;
306/**HPTXFSIZ (rw) register accessor: OTG_HS Host periodic transmit FIFO size register
307
308You can [`read`](crate::Reg::read) this register and get [`hptxfsiz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hptxfsiz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
309
310See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:HPTXFSIZ)
311
312For information about available fields see [`mod@hptxfsiz`] module*/
313pub type HPTXFSIZ = crate::Reg<hptxfsiz::HPTXFSIZrs>;
314///OTG_HS Host periodic transmit FIFO size register
315pub mod hptxfsiz;
316/**DIEPTXF (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register
317
318You can [`read`](crate::Reg::read) this register and get [`dieptxf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dieptxf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
319
320See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:DIEPTXF[1])
321
322For information about available fields see [`mod@dieptxf`] module*/
323pub type DIEPTXF = crate::Reg<dieptxf::DIEPTXFrs>;
324///OTG_HS device IN endpoint transmit FIFO size register
325pub mod dieptxf;
326/**GRXSTSR_Device (r) register accessor: OTG_HS Receive status debug read register (peripheral mode mode)
327
328You can [`read`](crate::Reg::read) this register and get [`grxstsr_device::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
329
330See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GRXSTSR_Device)
331
332For information about available fields see [`mod@grxstsr_device`] module*/
333#[doc(alias = "GRXSTSR_Device")]
334pub type GRXSTSR_DEVICE = crate::Reg<grxstsr_device::GRXSTSR_DEVICErs>;
335///OTG_HS Receive status debug read register (peripheral mode mode)
336pub mod grxstsr_device;
337/**GRXSTSP_Device (r) register accessor: OTG_HS status read and pop register (peripheral mode)
338
339You can [`read`](crate::Reg::read) this register and get [`grxstsp_device::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
340
341See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL:GRXSTSP_Device)
342
343For information about available fields see [`mod@grxstsp_device`] module*/
344#[doc(alias = "GRXSTSP_Device")]
345pub type GRXSTSP_DEVICE = crate::Reg<grxstsp_device::GRXSTSP_DEVICErs>;
346///OTG_HS status read and pop register (peripheral mode)
347pub mod grxstsp_device;
stm32f4/stm32f407/otg_hs_global.rs

stm32f4/stm32f407/
otg_hs_global.rs
