pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
fn WWDG();
fn PVD();
fn TAMP_STAMP();
fn RTC_WKUP();
fn FLASH();
fn RCC();
fn EXTI0();
fn EXTI1();
fn EXTI2();
fn EXTI3();
fn EXTI4();
fn DMA1_STREAM0();
fn DMA1_STREAM1();
fn DMA1_STREAM2();
fn DMA1_STREAM3();
fn DMA1_STREAM4();
fn DMA1_STREAM5();
fn DMA1_STREAM6();
fn ADC();
fn CAN1_TX();
fn CAN1_RX0();
fn CAN1_RX1();
fn CAN1_SCE();
fn EXTI9_5();
fn TIM1_BRK_TIM9();
fn TIM1_UP_TIM10();
fn TIM1_TRG_COM_TIM11();
fn TIM1_CC();
fn TIM2();
fn TIM3();
fn TIM4();
fn I2C1_EV();
fn I2C1_ER();
fn I2C2_EV();
fn I2C2_ER();
fn SPI1();
fn SPI2();
fn USART1();
fn USART2();
fn USART3();
fn EXTI15_10();
fn RTC_ALARM();
fn OTG_FS_WKUP();
fn TIM8_BRK_TIM12();
fn TIM8_UP_TIM13();
fn TIM8_TRG_COM_TIM14();
fn TIM8_CC();
fn DMA1_STREAM7();
fn FMC();
fn SDIO();
fn TIM5();
fn SPI3();
fn UART4();
fn UART5();
fn TIM6_DAC();
fn TIM7();
fn DMA2_STREAM0();
fn DMA2_STREAM1();
fn DMA2_STREAM2();
fn DMA2_STREAM3();
fn DMA2_STREAM4();
fn ETH();
fn ETH_WKUP();
fn CAN2_TX();
fn CAN2_RX0();
fn CAN2_RX1();
fn CAN2_SCE();
fn OTG_FS();
fn DMA2_STREAM5();
fn DMA2_STREAM6();
fn DMA2_STREAM7();
fn USART6();
fn I2C3_EV();
fn I2C3_ER();
fn OTG_HS_EP1_OUT();
fn OTG_HS_EP1_IN();
fn OTG_HS_WKUP();
fn OTG_HS();
fn DCMI();
fn CRYP();
fn HASH_RNG();
fn FPU();
fn UART7();
fn UART8();
fn SPI4();
fn SPI5();
fn SPI6();
fn SAI1();
fn LCD_TFT();
fn LCD_TFT_1();
fn DMA2D();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 91] = [
Vector { _handler: WWDG },
Vector { _handler: PVD },
Vector {
_handler: TAMP_STAMP,
},
Vector { _handler: RTC_WKUP },
Vector { _handler: FLASH },
Vector { _handler: RCC },
Vector { _handler: EXTI0 },
Vector { _handler: EXTI1 },
Vector { _handler: EXTI2 },
Vector { _handler: EXTI3 },
Vector { _handler: EXTI4 },
Vector {
_handler: DMA1_STREAM0,
},
Vector {
_handler: DMA1_STREAM1,
},
Vector {
_handler: DMA1_STREAM2,
},
Vector {
_handler: DMA1_STREAM3,
},
Vector {
_handler: DMA1_STREAM4,
},
Vector {
_handler: DMA1_STREAM5,
},
Vector {
_handler: DMA1_STREAM6,
},
Vector { _handler: ADC },
Vector { _handler: CAN1_TX },
Vector { _handler: CAN1_RX0 },
Vector { _handler: CAN1_RX1 },
Vector { _handler: CAN1_SCE },
Vector { _handler: EXTI9_5 },
Vector {
_handler: TIM1_BRK_TIM9,
},
Vector {
_handler: TIM1_UP_TIM10,
},
Vector {
_handler: TIM1_TRG_COM_TIM11,
},
Vector { _handler: TIM1_CC },
Vector { _handler: TIM2 },
Vector { _handler: TIM3 },
Vector { _handler: TIM4 },
Vector { _handler: I2C1_EV },
Vector { _handler: I2C1_ER },
Vector { _handler: I2C2_EV },
Vector { _handler: I2C2_ER },
Vector { _handler: SPI1 },
Vector { _handler: SPI2 },
Vector { _handler: USART1 },
Vector { _handler: USART2 },
Vector { _handler: USART3 },
Vector {
_handler: EXTI15_10,
},
Vector {
_handler: RTC_ALARM,
},
Vector {
_handler: OTG_FS_WKUP,
},
Vector {
_handler: TIM8_BRK_TIM12,
},
Vector {
_handler: TIM8_UP_TIM13,
},
Vector {
_handler: TIM8_TRG_COM_TIM14,
},
Vector { _handler: TIM8_CC },
Vector {
_handler: DMA1_STREAM7,
},
Vector { _handler: FMC },
Vector { _handler: SDIO },
Vector { _handler: TIM5 },
Vector { _handler: SPI3 },
Vector { _handler: UART4 },
Vector { _handler: UART5 },
Vector { _handler: TIM6_DAC },
Vector { _handler: TIM7 },
Vector {
_handler: DMA2_STREAM0,
},
Vector {
_handler: DMA2_STREAM1,
},
Vector {
_handler: DMA2_STREAM2,
},
Vector {
_handler: DMA2_STREAM3,
},
Vector {
_handler: DMA2_STREAM4,
},
Vector { _handler: ETH },
Vector { _handler: ETH_WKUP },
Vector { _handler: CAN2_TX },
Vector { _handler: CAN2_RX0 },
Vector { _handler: CAN2_RX1 },
Vector { _handler: CAN2_SCE },
Vector { _handler: OTG_FS },
Vector {
_handler: DMA2_STREAM5,
},
Vector {
_handler: DMA2_STREAM6,
},
Vector {
_handler: DMA2_STREAM7,
},
Vector { _handler: USART6 },
Vector { _handler: I2C3_EV },
Vector { _handler: I2C3_ER },
Vector {
_handler: OTG_HS_EP1_OUT,
},
Vector {
_handler: OTG_HS_EP1_IN,
},
Vector {
_handler: OTG_HS_WKUP,
},
Vector { _handler: OTG_HS },
Vector { _handler: DCMI },
Vector { _handler: CRYP },
Vector { _handler: HASH_RNG },
Vector { _handler: FPU },
Vector { _handler: UART7 },
Vector { _handler: UART8 },
Vector { _handler: SPI4 },
Vector { _handler: SPI5 },
Vector { _handler: SPI6 },
Vector { _handler: SAI1 },
Vector { _handler: LCD_TFT },
Vector {
_handler: LCD_TFT_1,
},
Vector { _handler: DMA2D },
];
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
WWDG = 0,
PVD = 1,
TAMP_STAMP = 2,
RTC_WKUP = 3,
FLASH = 4,
RCC = 5,
EXTI0 = 6,
EXTI1 = 7,
EXTI2 = 8,
EXTI3 = 9,
EXTI4 = 10,
DMA1_STREAM0 = 11,
DMA1_STREAM1 = 12,
DMA1_STREAM2 = 13,
DMA1_STREAM3 = 14,
DMA1_STREAM4 = 15,
DMA1_STREAM5 = 16,
DMA1_STREAM6 = 17,
ADC = 18,
CAN1_TX = 19,
CAN1_RX0 = 20,
CAN1_RX1 = 21,
CAN1_SCE = 22,
EXTI9_5 = 23,
TIM1_BRK_TIM9 = 24,
TIM1_UP_TIM10 = 25,
TIM1_TRG_COM_TIM11 = 26,
TIM1_CC = 27,
TIM2 = 28,
TIM3 = 29,
TIM4 = 30,
I2C1_EV = 31,
I2C1_ER = 32,
I2C2_EV = 33,
I2C2_ER = 34,
SPI1 = 35,
SPI2 = 36,
USART1 = 37,
USART2 = 38,
USART3 = 39,
EXTI15_10 = 40,
RTC_ALARM = 41,
OTG_FS_WKUP = 42,
TIM8_BRK_TIM12 = 43,
TIM8_UP_TIM13 = 44,
TIM8_TRG_COM_TIM14 = 45,
TIM8_CC = 46,
DMA1_STREAM7 = 47,
FMC = 48,
SDIO = 49,
TIM5 = 50,
SPI3 = 51,
UART4 = 52,
UART5 = 53,
TIM6_DAC = 54,
TIM7 = 55,
DMA2_STREAM0 = 56,
DMA2_STREAM1 = 57,
DMA2_STREAM2 = 58,
DMA2_STREAM3 = 59,
DMA2_STREAM4 = 60,
ETH = 61,
ETH_WKUP = 62,
CAN2_TX = 63,
CAN2_RX0 = 64,
CAN2_RX1 = 65,
CAN2_SCE = 66,
OTG_FS = 67,
DMA2_STREAM5 = 68,
DMA2_STREAM6 = 69,
DMA2_STREAM7 = 70,
USART6 = 71,
I2C3_EV = 72,
I2C3_ER = 73,
OTG_HS_EP1_OUT = 74,
OTG_HS_EP1_IN = 75,
OTG_HS_WKUP = 76,
OTG_HS = 77,
DCMI = 78,
CRYP = 79,
HASH_RNG = 80,
FPU = 81,
UART7 = 82,
UART8 = 83,
SPI4 = 84,
SPI5 = 85,
SPI6 = 86,
SAI1 = 87,
LCD_TFT = 88,
LCD_TFT_1 = 89,
DMA2D = 90,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
#[inline(always)]
fn number(self) -> u16 {
self as u16
}
}
pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
impl core::fmt::Debug for RNG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RNG").finish()
}
}
pub mod rng;
pub type HASH = crate::Periph<hash::RegisterBlock, 0x5006_0400>;
impl core::fmt::Debug for HASH {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HASH").finish()
}
}
pub mod hash;
pub type CRYP = crate::Periph<cryp::RegisterBlock, 0x5006_0000>;
impl core::fmt::Debug for CRYP {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRYP").finish()
}
}
pub mod cryp;
pub type DCMI = crate::Periph<dcmi::RegisterBlock, 0x5005_0000>;
impl core::fmt::Debug for DCMI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DCMI").finish()
}
}
pub mod dcmi;
pub type FMC = crate::Periph<fmc::RegisterBlock, 0xa000_0000>;
impl core::fmt::Debug for FMC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FMC").finish()
}
}
pub mod fmc;
pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
impl core::fmt::Debug for DBGMCU {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DBGMCU").finish()
}
}
pub mod dbgmcu;
pub type DMA2 = crate::Periph<dma2::RegisterBlock, 0x4002_6400>;
impl core::fmt::Debug for DMA2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA2").finish()
}
}
pub mod dma2;
pub type DMA1 = crate::Periph<dma2::RegisterBlock, 0x4002_6000>;
impl core::fmt::Debug for DMA1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA1").finish()
}
}
pub use self::dma2 as dma1;
pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_3800>;
impl core::fmt::Debug for RCC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RCC").finish()
}
}
pub mod rcc;
pub type GPIOK = crate::Periph<gpiok::RegisterBlock, 0x4002_2800>;
impl core::fmt::Debug for GPIOK {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOK").finish()
}
}
pub mod gpiok;
pub type GPIOJ = crate::Periph<gpiok::RegisterBlock, 0x4002_2400>;
impl core::fmt::Debug for GPIOJ {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOJ").finish()
}
}
pub use self::gpiok as gpioj;
pub type GPIOI = crate::Periph<gpiok::RegisterBlock, 0x4002_2000>;
impl core::fmt::Debug for GPIOI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOI").finish()
}
}
pub use self::gpiok as gpioi;
pub type GPIOH = crate::Periph<gpiok::RegisterBlock, 0x4002_1c00>;
impl core::fmt::Debug for GPIOH {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOH").finish()
}
}
pub use self::gpiok as gpioh;
pub type GPIOG = crate::Periph<gpiok::RegisterBlock, 0x4002_1800>;
impl core::fmt::Debug for GPIOG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOG").finish()
}
}
pub use self::gpiok as gpiog;
pub type GPIOF = crate::Periph<gpiok::RegisterBlock, 0x4002_1400>;
impl core::fmt::Debug for GPIOF {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOF").finish()
}
}
pub use self::gpiok as gpiof;
pub type GPIOE = crate::Periph<gpiok::RegisterBlock, 0x4002_1000>;
impl core::fmt::Debug for GPIOE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOE").finish()
}
}
pub use self::gpiok as gpioe;
pub type GPIOD = crate::Periph<gpiok::RegisterBlock, 0x4002_0c00>;
impl core::fmt::Debug for GPIOD {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOD").finish()
}
}
pub use self::gpiok as gpiod;
pub type GPIOC = crate::Periph<gpiok::RegisterBlock, 0x4002_0800>;
impl core::fmt::Debug for GPIOC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOC").finish()
}
}
pub use self::gpiok as gpioc;
pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4002_0400>;
impl core::fmt::Debug for GPIOB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOB").finish()
}
}
pub mod gpiob;
pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for GPIOA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOA").finish()
}
}
pub mod gpioa;
pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_3800>;
impl core::fmt::Debug for SYSCFG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SYSCFG").finish()
}
}
pub mod syscfg;
pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for SPI1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI1").finish()
}
}
pub mod spi1;
pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
impl core::fmt::Debug for SPI2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI2").finish()
}
}
pub use self::spi1 as spi2;
pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
impl core::fmt::Debug for SPI3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI3").finish()
}
}
pub use self::spi1 as spi3;
pub type I2S2EXT = crate::Periph<spi1::RegisterBlock, 0x4000_3400>;
impl core::fmt::Debug for I2S2EXT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2S2EXT").finish()
}
}
pub use self::spi1 as i2s2ext;
pub type I2S3EXT = crate::Periph<spi1::RegisterBlock, 0x4000_4000>;
impl core::fmt::Debug for I2S3EXT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2S3EXT").finish()
}
}
pub use self::spi1 as i2s3ext;
pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4001_3400>;
impl core::fmt::Debug for SPI4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI4").finish()
}
}
pub use self::spi1 as spi4;
pub type SPI5 = crate::Periph<spi1::RegisterBlock, 0x4001_5000>;
impl core::fmt::Debug for SPI5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI5").finish()
}
}
pub use self::spi1 as spi5;
pub type SPI6 = crate::Periph<spi1::RegisterBlock, 0x4001_5400>;
impl core::fmt::Debug for SPI6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI6").finish()
}
}
pub use self::spi1 as spi6;
pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_2c00>;
impl core::fmt::Debug for SDIO {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SDIO").finish()
}
}
pub mod sdio;
pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2000>;
impl core::fmt::Debug for ADC1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC1").finish()
}
}
pub mod adc1;
pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x4001_2100>;
impl core::fmt::Debug for ADC2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC2").finish()
}
}
pub use self::adc1 as adc2;
pub type ADC3 = crate::Periph<adc1::RegisterBlock, 0x4001_2200>;
impl core::fmt::Debug for ADC3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC3").finish()
}
}
pub use self::adc1 as adc3;
pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_1000>;
impl core::fmt::Debug for USART1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART1").finish()
}
}
pub mod usart1;
pub type USART6 = crate::Periph<usart1::RegisterBlock, 0x4001_1400>;
impl core::fmt::Debug for USART6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART6").finish()
}
}
pub use self::usart1 as usart6;
pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
impl core::fmt::Debug for USART2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART2").finish()
}
}
pub use self::usart1 as usart2;
pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
impl core::fmt::Debug for USART3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART3").finish()
}
}
pub use self::usart1 as usart3;
pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
impl core::fmt::Debug for UART4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART4").finish()
}
}
pub mod uart4;
pub type UART7 = crate::Periph<uart4::RegisterBlock, 0x4000_7800>;
impl core::fmt::Debug for UART7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART7").finish()
}
}
pub use self::uart4 as uart7;
pub type UART8 = crate::Periph<uart4::RegisterBlock, 0x4000_7c00>;
impl core::fmt::Debug for UART8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART8").finish()
}
}
pub use self::uart4 as uart8;
pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
impl core::fmt::Debug for DAC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DAC").finish()
}
}
pub mod dac;
pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
impl core::fmt::Debug for PWR {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PWR").finish()
}
}
pub mod pwr;
pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for IWDG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IWDG").finish()
}
}
pub mod iwdg;
pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
impl core::fmt::Debug for WWDG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WWDG").finish()
}
}
pub mod wwdg;
pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
impl core::fmt::Debug for RTC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTC").finish()
}
}
pub mod rtc;
pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for UART5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART5").finish()
}
}
pub use self::uart4 as uart5;
pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4001_2300>;
impl core::fmt::Debug for ADC_COMMON {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC_COMMON").finish()
}
}
pub mod adc_common;
pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for TIM1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM1").finish()
}
}
pub mod tim1;
pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_0400>;
impl core::fmt::Debug for TIM8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM8").finish()
}
}
pub use self::tim1 as tim8;
pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for TIM2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM2").finish()
}
}
pub mod tim2;
pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
impl core::fmt::Debug for TIM3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM3").finish()
}
}
pub mod tim3;
pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
impl core::fmt::Debug for TIM4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM4").finish()
}
}
pub use self::tim3 as tim4;
pub type TIM5 = crate::Periph<tim5::RegisterBlock, 0x4000_0c00>;
impl core::fmt::Debug for TIM5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM5").finish()
}
}
pub mod tim5;
pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for TIM9 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM9").finish()
}
}
pub mod tim9;
pub type TIM12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
impl core::fmt::Debug for TIM12 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM12").finish()
}
}
pub use self::tim9 as tim12;
pub type TIM10 = crate::Periph<tim10::RegisterBlock, 0x4001_4400>;
impl core::fmt::Debug for TIM10 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM10").finish()
}
}
pub mod tim10;
pub type TIM13 = crate::Periph<tim10::RegisterBlock, 0x4000_1c00>;
impl core::fmt::Debug for TIM13 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM13").finish()
}
}
pub use self::tim10 as tim13;
pub type TIM14 = crate::Periph<tim10::RegisterBlock, 0x4000_2000>;
impl core::fmt::Debug for TIM14 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM14").finish()
}
}
pub use self::tim10 as tim14;
pub type TIM11 = crate::Periph<tim11::RegisterBlock, 0x4001_4800>;
impl core::fmt::Debug for TIM11 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM11").finish()
}
}
pub mod tim11;
pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for TIM6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM6").finish()
}
}
pub mod tim6;
pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
impl core::fmt::Debug for TIM7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM7").finish()
}
}
pub use self::tim6 as tim7;
pub type ETHERNET_MAC = crate::Periph<ethernet_mac::RegisterBlock, 0x4002_8000>;
impl core::fmt::Debug for ETHERNET_MAC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ETHERNET_MAC").finish()
}
}
pub mod ethernet_mac;
pub type ETHERNET_MMC = crate::Periph<ethernet_mmc::RegisterBlock, 0x4002_8100>;
impl core::fmt::Debug for ETHERNET_MMC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ETHERNET_MMC").finish()
}
}
pub mod ethernet_mmc;
pub type ETHERNET_PTP = crate::Periph<ethernet_ptp::RegisterBlock, 0x4002_8700>;
impl core::fmt::Debug for ETHERNET_PTP {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ETHERNET_PTP").finish()
}
}
pub mod ethernet_ptp;
pub type ETHERNET_DMA = crate::Periph<ethernet_dma::RegisterBlock, 0x4002_9000>;
impl core::fmt::Debug for ETHERNET_DMA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ETHERNET_DMA").finish()
}
}
pub mod ethernet_dma;
pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
impl core::fmt::Debug for CRC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRC").finish()
}
}
pub mod crc;
pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
impl core::fmt::Debug for OTG_FS_GLOBAL {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OTG_FS_GLOBAL").finish()
}
}
pub mod otg_fs_global;
pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
impl core::fmt::Debug for OTG_FS_HOST {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OTG_FS_HOST").finish()
}
}
pub mod otg_fs_host;
pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
impl core::fmt::Debug for OTG_FS_DEVICE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OTG_FS_DEVICE").finish()
}
}
pub mod otg_fs_device;
pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
impl core::fmt::Debug for OTG_FS_PWRCLK {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OTG_FS_PWRCLK").finish()
}
}
pub mod otg_fs_pwrclk;
pub type CAN1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
impl core::fmt::Debug for CAN1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN1").finish()
}
}
pub mod can1;
pub type CAN2 = crate::Periph<can1::RegisterBlock, 0x4000_6800>;
impl core::fmt::Debug for CAN2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN2").finish()
}
}
pub use self::can1 as can2;
pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_3c00>;
impl core::fmt::Debug for FLASH {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH").finish()
}
}
pub mod flash;
pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_3c00>;
impl core::fmt::Debug for EXTI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EXTI").finish()
}
}
pub mod exti;
pub type OTG_HS_GLOBAL = crate::Periph<otg_hs_global::RegisterBlock, 0x4004_0000>;
impl core::fmt::Debug for OTG_HS_GLOBAL {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OTG_HS_GLOBAL").finish()
}
}
pub mod otg_hs_global;
pub type OTG_HS_HOST = crate::Periph<otg_hs_host::RegisterBlock, 0x4004_0400>;
impl core::fmt::Debug for OTG_HS_HOST {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OTG_HS_HOST").finish()
}
}
pub mod otg_hs_host;
pub type OTG_HS_DEVICE = crate::Periph<otg_hs_device::RegisterBlock, 0x4004_0800>;
impl core::fmt::Debug for OTG_HS_DEVICE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OTG_HS_DEVICE").finish()
}
}
pub mod otg_hs_device;
pub type OTG_HS_PWRCLK = crate::Periph<otg_hs_pwrclk::RegisterBlock, 0x4004_0e00>;
impl core::fmt::Debug for OTG_HS_PWRCLK {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OTG_HS_PWRCLK").finish()
}
}
pub mod otg_hs_pwrclk;
pub type LTDC = crate::Periph<ltdc::RegisterBlock, 0x4001_6800>;
impl core::fmt::Debug for LTDC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LTDC").finish()
}
}
pub mod ltdc;
pub type SAI = crate::Periph<sai::RegisterBlock, 0x4001_5800>;
impl core::fmt::Debug for SAI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SAI").finish()
}
}
pub mod sai;
pub type DMA2D = crate::Periph<dma2d::RegisterBlock, 0x4002_b000>;
impl core::fmt::Debug for DMA2D {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA2D").finish()
}
}
pub mod dma2d;
pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
impl core::fmt::Debug for I2C1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C1").finish()
}
}
pub mod i2c1;
pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
impl core::fmt::Debug for I2C3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C3").finish()
}
}
pub use self::i2c1 as i2c3;
pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
impl core::fmt::Debug for I2C2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C2").finish()
}
}
pub use self::i2c1 as i2c2;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[allow(non_snake_case)]
pub struct Peripherals {
pub RNG: RNG,
pub HASH: HASH,
pub CRYP: CRYP,
pub DCMI: DCMI,
pub FMC: FMC,
pub DBGMCU: DBGMCU,
pub DMA2: DMA2,
pub DMA1: DMA1,
pub RCC: RCC,
pub GPIOK: GPIOK,
pub GPIOJ: GPIOJ,
pub GPIOI: GPIOI,
pub GPIOH: GPIOH,
pub GPIOG: GPIOG,
pub GPIOF: GPIOF,
pub GPIOE: GPIOE,
pub GPIOD: GPIOD,
pub GPIOC: GPIOC,
pub GPIOB: GPIOB,
pub GPIOA: GPIOA,
pub SYSCFG: SYSCFG,
pub SPI1: SPI1,
pub SPI2: SPI2,
pub SPI3: SPI3,
pub I2S2EXT: I2S2EXT,
pub I2S3EXT: I2S3EXT,
pub SPI4: SPI4,
pub SPI5: SPI5,
pub SPI6: SPI6,
pub SDIO: SDIO,
pub ADC1: ADC1,
pub ADC2: ADC2,
pub ADC3: ADC3,
pub USART1: USART1,
pub USART6: USART6,
pub USART2: USART2,
pub USART3: USART3,
pub UART4: UART4,
pub UART7: UART7,
pub UART8: UART8,
pub DAC: DAC,
pub PWR: PWR,
pub IWDG: IWDG,
pub WWDG: WWDG,
pub RTC: RTC,
pub UART5: UART5,
pub ADC_COMMON: ADC_COMMON,
pub TIM1: TIM1,
pub TIM8: TIM8,
pub TIM2: TIM2,
pub TIM3: TIM3,
pub TIM4: TIM4,
pub TIM5: TIM5,
pub TIM9: TIM9,
pub TIM12: TIM12,
pub TIM10: TIM10,
pub TIM13: TIM13,
pub TIM14: TIM14,
pub TIM11: TIM11,
pub TIM6: TIM6,
pub TIM7: TIM7,
pub ETHERNET_MAC: ETHERNET_MAC,
pub ETHERNET_MMC: ETHERNET_MMC,
pub ETHERNET_PTP: ETHERNET_PTP,
pub ETHERNET_DMA: ETHERNET_DMA,
pub CRC: CRC,
pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
pub OTG_FS_HOST: OTG_FS_HOST,
pub OTG_FS_DEVICE: OTG_FS_DEVICE,
pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
pub CAN1: CAN1,
pub CAN2: CAN2,
pub FLASH: FLASH,
pub EXTI: EXTI,
pub OTG_HS_GLOBAL: OTG_HS_GLOBAL,
pub OTG_HS_HOST: OTG_HS_HOST,
pub OTG_HS_DEVICE: OTG_HS_DEVICE,
pub OTG_HS_PWRCLK: OTG_HS_PWRCLK,
pub LTDC: LTDC,
pub SAI: SAI,
pub DMA2D: DMA2D,
pub I2C1: I2C1,
pub I2C3: I2C3,
pub I2C2: I2C2,
}
impl Peripherals {
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
RNG: RNG::steal(),
HASH: HASH::steal(),
CRYP: CRYP::steal(),
DCMI: DCMI::steal(),
FMC: FMC::steal(),
DBGMCU: DBGMCU::steal(),
DMA2: DMA2::steal(),
DMA1: DMA1::steal(),
RCC: RCC::steal(),
GPIOK: GPIOK::steal(),
GPIOJ: GPIOJ::steal(),
GPIOI: GPIOI::steal(),
GPIOH: GPIOH::steal(),
GPIOG: GPIOG::steal(),
GPIOF: GPIOF::steal(),
GPIOE: GPIOE::steal(),
GPIOD: GPIOD::steal(),
GPIOC: GPIOC::steal(),
GPIOB: GPIOB::steal(),
GPIOA: GPIOA::steal(),
SYSCFG: SYSCFG::steal(),
SPI1: SPI1::steal(),
SPI2: SPI2::steal(),
SPI3: SPI3::steal(),
I2S2EXT: I2S2EXT::steal(),
I2S3EXT: I2S3EXT::steal(),
SPI4: SPI4::steal(),
SPI5: SPI5::steal(),
SPI6: SPI6::steal(),
SDIO: SDIO::steal(),
ADC1: ADC1::steal(),
ADC2: ADC2::steal(),
ADC3: ADC3::steal(),
USART1: USART1::steal(),
USART6: USART6::steal(),
USART2: USART2::steal(),
USART3: USART3::steal(),
UART4: UART4::steal(),
UART7: UART7::steal(),
UART8: UART8::steal(),
DAC: DAC::steal(),
PWR: PWR::steal(),
IWDG: IWDG::steal(),
WWDG: WWDG::steal(),
RTC: RTC::steal(),
UART5: UART5::steal(),
ADC_COMMON: ADC_COMMON::steal(),
TIM1: TIM1::steal(),
TIM8: TIM8::steal(),
TIM2: TIM2::steal(),
TIM3: TIM3::steal(),
TIM4: TIM4::steal(),
TIM5: TIM5::steal(),
TIM9: TIM9::steal(),
TIM12: TIM12::steal(),
TIM10: TIM10::steal(),
TIM13: TIM13::steal(),
TIM14: TIM14::steal(),
TIM11: TIM11::steal(),
TIM6: TIM6::steal(),
TIM7: TIM7::steal(),
ETHERNET_MAC: ETHERNET_MAC::steal(),
ETHERNET_MMC: ETHERNET_MMC::steal(),
ETHERNET_PTP: ETHERNET_PTP::steal(),
ETHERNET_DMA: ETHERNET_DMA::steal(),
CRC: CRC::steal(),
OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
OTG_FS_HOST: OTG_FS_HOST::steal(),
OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
CAN1: CAN1::steal(),
CAN2: CAN2::steal(),
FLASH: FLASH::steal(),
EXTI: EXTI::steal(),
OTG_HS_GLOBAL: OTG_HS_GLOBAL::steal(),
OTG_HS_HOST: OTG_HS_HOST::steal(),
OTG_HS_DEVICE: OTG_HS_DEVICE::steal(),
OTG_HS_PWRCLK: OTG_HS_PWRCLK::steal(),
LTDC: LTDC::steal(),
SAI: SAI::steal(),
DMA2D: DMA2D::steal(),
I2C1: I2C1::steal(),
I2C3: I2C3::steal(),
I2C2: I2C2::steal(),
}
}
}