stm32f4 0.16.0

/*!Peripheral access API for STM32F413 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))

You can find an overview of the generated API [here].

API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.

[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
[repository]: https://github.com/rust-embedded/svd2rust*/
///Number available in the NVIC for configuring priority
pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
    fn PVD();
    fn TAMP_STAMP();
    fn RTC_WKUP();
    fn FLASH();
    fn RCC();
    fn EXTI0();
    fn EXTI1();
    fn EXTI2();
    fn EXTI3();
    fn EXTI4();
    fn DMA1_STREAM0();
    fn DMA1_STREAM1();
    fn DMA1_STREAM2();
    fn DMA1_STREAM3();
    fn DMA1_STREAM4();
    fn DMA1_STREAM5();
    fn DMA1_STREAM6();
    fn ADC();
    fn CAN1_TX();
    fn CAN1_RX0();
    fn CAN1_RX1();
    fn CAN1_SCE();
    fn EXTI9_5();
    fn TIM1_BRK_TIM9();
    fn TIM1_UP_TIM10();
    fn TIM1_TRG_COM_TIM11();
    fn TIM1_CC();
    fn TIM2();
    fn TIM3();
    fn TIM4();
    fn I2C1_EVT();
    fn I2C1_ERR();
    fn I2C2_EVT();
    fn I2C2_ERR();
    fn SPI1();
    fn SPI2();
    fn USART1();
    fn USART2();
    fn USART3();
    fn EXTI15_10();
    fn EXTI17_RTC_ALARM();
    fn TIM8_BRK_TIM12();
    fn TIM8_UP_TIM13();
    fn TIM8_TRG_COM_TIM14();
    fn TIM8_CC();
    fn DMA1_STREAM7();
    fn FSMC();
    fn SDIO();
    fn TIM5();
    fn UART4();
    fn UART5();
    fn TIM6_GLB_IT_DAC1_DAC2();
    fn TIM7();
    fn DMA2_STREAM0();
    fn DMA2_STREAM1();
    fn DMA2_STREAM2();
    fn DMA2_STREAM3();
    fn DMA2_STREAM4();
    fn DFSDM1_FLT0();
    fn DFSDM1_FLT1();
    fn CAN2_TX();
    fn CAN2_RX0();
    fn CAN2_RX1();
    fn CAN2_SCE();
    fn OTG_FS();
    fn DMA2_STREAM5();
    fn DMA2_STREAM6();
    fn DMA2_STREAM7();
    fn USART6();
    fn I2C3_EV();
    fn I2C3_ER();
    fn CAN3_TX();
    fn CAN3_RX0();
    fn CAN3_RX1();
    fn CAN3_SCE();
    fn CRYPTO();
    fn RNG();
    fn FPU();
    fn UART7();
    fn UART8();
    fn SPI4();
    fn SPI5();
    fn SAI1();
    fn UART9();
    fn UART10();
    fn QUAD_SPI();
    fn I2CFMP1EVENT();
    fn I2CFMP1ERROR();
    fn LPTIM1_OR_IT_EIT_23();
    fn DFSDM2_FILTER1();
    fn DFSDM2_FILTER2();
    fn DFSDM2_FILTER3();
    fn DFSDM2_FILTER4();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
    _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 102] = [
    Vector { _reserved: 0 },
    Vector { _handler: PVD },
    Vector {
        _handler: TAMP_STAMP,
    },
    Vector { _handler: RTC_WKUP },
    Vector { _handler: FLASH },
    Vector { _handler: RCC },
    Vector { _handler: EXTI0 },
    Vector { _handler: EXTI1 },
    Vector { _handler: EXTI2 },
    Vector { _handler: EXTI3 },
    Vector { _handler: EXTI4 },
    Vector {
        _handler: DMA1_STREAM0,
    },
    Vector {
        _handler: DMA1_STREAM1,
    },
    Vector {
        _handler: DMA1_STREAM2,
    },
    Vector {
        _handler: DMA1_STREAM3,
    },
    Vector {
        _handler: DMA1_STREAM4,
    },
    Vector {
        _handler: DMA1_STREAM5,
    },
    Vector {
        _handler: DMA1_STREAM6,
    },
    Vector { _handler: ADC },
    Vector { _handler: CAN1_TX },
    Vector { _handler: CAN1_RX0 },
    Vector { _handler: CAN1_RX1 },
    Vector { _handler: CAN1_SCE },
    Vector { _handler: EXTI9_5 },
    Vector {
        _handler: TIM1_BRK_TIM9,
    },
    Vector {
        _handler: TIM1_UP_TIM10,
    },
    Vector {
        _handler: TIM1_TRG_COM_TIM11,
    },
    Vector { _handler: TIM1_CC },
    Vector { _handler: TIM2 },
    Vector { _handler: TIM3 },
    Vector { _handler: TIM4 },
    Vector { _handler: I2C1_EVT },
    Vector { _handler: I2C1_ERR },
    Vector { _handler: I2C2_EVT },
    Vector { _handler: I2C2_ERR },
    Vector { _handler: SPI1 },
    Vector { _handler: SPI2 },
    Vector { _handler: USART1 },
    Vector { _handler: USART2 },
    Vector { _handler: USART3 },
    Vector {
        _handler: EXTI15_10,
    },
    Vector {
        _handler: EXTI17_RTC_ALARM,
    },
    Vector { _reserved: 0 },
    Vector {
        _handler: TIM8_BRK_TIM12,
    },
    Vector {
        _handler: TIM8_UP_TIM13,
    },
    Vector {
        _handler: TIM8_TRG_COM_TIM14,
    },
    Vector { _handler: TIM8_CC },
    Vector {
        _handler: DMA1_STREAM7,
    },
    Vector { _handler: FSMC },
    Vector { _handler: SDIO },
    Vector { _handler: TIM5 },
    Vector { _reserved: 0 },
    Vector { _handler: UART4 },
    Vector { _handler: UART5 },
    Vector {
        _handler: TIM6_GLB_IT_DAC1_DAC2,
    },
    Vector { _handler: TIM7 },
    Vector {
        _handler: DMA2_STREAM0,
    },
    Vector {
        _handler: DMA2_STREAM1,
    },
    Vector {
        _handler: DMA2_STREAM2,
    },
    Vector {
        _handler: DMA2_STREAM3,
    },
    Vector {
        _handler: DMA2_STREAM4,
    },
    Vector {
        _handler: DFSDM1_FLT0,
    },
    Vector {
        _handler: DFSDM1_FLT1,
    },
    Vector { _handler: CAN2_TX },
    Vector { _handler: CAN2_RX0 },
    Vector { _handler: CAN2_RX1 },
    Vector { _handler: CAN2_SCE },
    Vector { _handler: OTG_FS },
    Vector {
        _handler: DMA2_STREAM5,
    },
    Vector {
        _handler: DMA2_STREAM6,
    },
    Vector {
        _handler: DMA2_STREAM7,
    },
    Vector { _handler: USART6 },
    Vector { _handler: I2C3_EV },
    Vector { _handler: I2C3_ER },
    Vector { _handler: CAN3_TX },
    Vector { _handler: CAN3_RX0 },
    Vector { _handler: CAN3_RX1 },
    Vector { _handler: CAN3_SCE },
    Vector { _reserved: 0 },
    Vector { _handler: CRYPTO },
    Vector { _handler: RNG },
    Vector { _handler: FPU },
    Vector { _handler: UART7 },
    Vector { _handler: UART8 },
    Vector { _handler: SPI4 },
    Vector { _handler: SPI5 },
    Vector { _reserved: 0 },
    Vector { _handler: SAI1 },
    Vector { _handler: UART9 },
    Vector { _handler: UART10 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: QUAD_SPI },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector {
        _handler: I2CFMP1EVENT,
    },
    Vector {
        _handler: I2CFMP1ERROR,
    },
    Vector {
        _handler: LPTIM1_OR_IT_EIT_23,
    },
    Vector {
        _handler: DFSDM2_FILTER1,
    },
    Vector {
        _handler: DFSDM2_FILTER2,
    },
    Vector {
        _handler: DFSDM2_FILTER3,
    },
    Vector {
        _handler: DFSDM2_FILTER4,
    },
];
///Enumeration of all the interrupts.
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
    ///1 - PVD through EXTI line detection interrupt
    PVD = 1,
    ///2 - Tamper and TimeStamp interrupts through the EXTI line
    TAMP_STAMP = 2,
    ///3 - RTC Wakeup interrupt through the EXTI line
    RTC_WKUP = 3,
    ///4 - FLASH global interrupt
    FLASH = 4,
    ///5 - RCC global interrupt
    RCC = 5,
    ///6 - EXTI Line0 interrupt
    EXTI0 = 6,
    ///7 - EXTI Line1 interrupt
    EXTI1 = 7,
    ///8 - EXTI Line2 interrupt
    EXTI2 = 8,
    ///9 - EXTI Line3 interrupt
    EXTI3 = 9,
    ///10 - EXTI Line4 interrupt
    EXTI4 = 10,
    ///11 - DMA1 Stream0 global interrupt
    DMA1_STREAM0 = 11,
    ///12 - DMA1 Stream1 global interrupt
    DMA1_STREAM1 = 12,
    ///13 - DMA1 Stream2 global interrupt
    DMA1_STREAM2 = 13,
    ///14 - DMA1 Stream3 global interrupt
    DMA1_STREAM3 = 14,
    ///15 - DMA1 Stream4 global interrupt
    DMA1_STREAM4 = 15,
    ///16 - DMA1 Stream5 global interrupt
    DMA1_STREAM5 = 16,
    ///17 - DMA1 Stream6 global interrupt
    DMA1_STREAM6 = 17,
    ///18 - ADC1 global interrupt
    ADC = 18,
    ///19 - CAN1 TX interrupts
    CAN1_TX = 19,
    ///20 - CAN1 RX0 interrupts
    CAN1_RX0 = 20,
    ///21 - CAN1 RX1 interrupts
    CAN1_RX1 = 21,
    ///22 - CAN1 SCE interrupt
    CAN1_SCE = 22,
    ///23 - EXTI Line\[9:5\] interrupts
    EXTI9_5 = 23,
    ///24 - TIM1 Break interrupt and TIM9 global interrupt
    TIM1_BRK_TIM9 = 24,
    ///25 - TIM1 Update interrupt and TIM10 global interrupt
    TIM1_UP_TIM10 = 25,
    ///26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
    TIM1_TRG_COM_TIM11 = 26,
    ///27 - TIM1 Capture Compare interrupt
    TIM1_CC = 27,
    ///28 - TIM2 global interrupt
    TIM2 = 28,
    ///29 - TIM3 global interrupt
    TIM3 = 29,
    ///30 - TIM4 global interrupt
    TIM4 = 30,
    ///31 - I2C1 event interrupt
    I2C1_EVT = 31,
    ///32 - I2C1 error interrupt
    I2C1_ERR = 32,
    ///33 - I2C2 event interrupt
    I2C2_EVT = 33,
    ///34 - I2C2 error interrupt
    I2C2_ERR = 34,
    ///35 - SPI1 global interrupt
    SPI1 = 35,
    ///36 - SPI2 global interrupt
    SPI2 = 36,
    ///37 - USART1 global interrupt
    USART1 = 37,
    ///38 - USART 2 global interrupt
    USART2 = 38,
    ///39 - USART 3 global interrupt
    USART3 = 39,
    ///40 - EXTI Line\[15:10\] interrupts
    EXTI15_10 = 40,
    ///41 - RTC Alarms (A and B) through EXTI line interrupt
    EXTI17_RTC_ALARM = 41,
    ///43 - Timer 12 global interrupt
    TIM8_BRK_TIM12 = 43,
    ///44 - Timer 13 global interrupt
    TIM8_UP_TIM13 = 44,
    ///45 - Timer 14 global interrupt
    TIM8_TRG_COM_TIM14 = 45,
    ///46 - TIM8 Cap/Com interrupt
    TIM8_CC = 46,
    ///47 - DMA1 global interrupt Channel 7
    DMA1_STREAM7 = 47,
    ///48 - FSMC global interrupt
    FSMC = 48,
    ///49 - SDIO global interrupt
    SDIO = 49,
    ///50 - TIM5 global interrupt
    TIM5 = 50,
    ///52 - UART4 global interrupt
    UART4 = 52,
    ///53 - UART5 global interrupt
    UART5 = 53,
    ///54 - TIM6 global and DAC12 underrun interrupts
    TIM6_GLB_IT_DAC1_DAC2 = 54,
    ///55 - TIM7 global interrupt
    TIM7 = 55,
    ///56 - DMA2 Stream0 global interrupt
    DMA2_STREAM0 = 56,
    ///57 - DMA2 Stream1 global interrupt
    DMA2_STREAM1 = 57,
    ///58 - DMA2 Stream2 global interrupt
    DMA2_STREAM2 = 58,
    ///59 - DMA2 Stream3 global interrupt
    DMA2_STREAM3 = 59,
    ///60 - DMA2 Stream4 global interrupt
    DMA2_STREAM4 = 60,
    ///61 - SD filter0 global interrupt
    DFSDM1_FLT0 = 61,
    ///62 - SD filter1 global interrupt
    DFSDM1_FLT1 = 62,
    ///63 - CAN2 TX interrupt
    CAN2_TX = 63,
    ///64 - BXCAN2 RX0 interrupt
    CAN2_RX0 = 64,
    ///65 - BXCAN2 RX1 interrupt
    CAN2_RX1 = 65,
    ///66 - CAN2 SCE interrupt
    CAN2_SCE = 66,
    ///67 - USB OTG FS Interrupt
    OTG_FS = 67,
    ///68 - DMA2 Stream5 global interrupt
    DMA2_STREAM5 = 68,
    ///69 - DMA2 Stream6 global interrupt
    DMA2_STREAM6 = 69,
    ///70 - DMA2 Stream7 global interrupt
    DMA2_STREAM7 = 70,
    ///71 - USART 6 global interrupt
    USART6 = 71,
    ///72 - I2C3 event interrupt
    I2C3_EV = 72,
    ///73 - I2C3 error interrupt
    I2C3_ER = 73,
    ///74 - CAN 3 TX interrupt
    CAN3_TX = 74,
    ///75 - BxCAN 3 RX0 interrupt
    CAN3_RX0 = 75,
    ///76 - BxCAN 3 RX1 interrupt
    CAN3_RX1 = 76,
    ///77 - CAN 3 SCE interrupt
    CAN3_SCE = 77,
    ///79 - AES global interrupt
    CRYPTO = 79,
    ///80 - Rng global interrupt
    RNG = 80,
    ///81 - FPU interrupt
    FPU = 81,
    ///82 - UART 7 global interrupt
    UART7 = 82,
    ///83 - UART 8 global interrupt
    UART8 = 83,
    ///84 - SPI4 global interrupt
    SPI4 = 84,
    ///85 - SPI5 global interrupt
    SPI5 = 85,
    ///87 - SAI1 global interrupt
    SAI1 = 87,
    ///88 - UART9 global interrupt
    UART9 = 88,
    ///89 - UART10 global interrupt
    UART10 = 89,
    ///92 - Quad-SPI global interrupt
    QUAD_SPI = 92,
    ///95 - I2CFMP1 event interrupt
    I2CFMP1EVENT = 95,
    ///96 - I2CFMP1 error interrupt
    I2CFMP1ERROR = 96,
    ///97 - LP Timer global interrupt or EXT1 interrupt line 23
    LPTIM1_OR_IT_EIT_23 = 97,
    ///98 - DFSDM2 SD filter 1 global interrupt
    DFSDM2_FILTER1 = 98,
    ///99 - DFSDM2 SD filter 2 global interrupt
    DFSDM2_FILTER2 = 99,
    ///100 - DFSDM2 SD filter 3 global interrupt
    DFSDM2_FILTER3 = 100,
    ///101 - DFSDM2 SD filter 4 global interrupt
    DFSDM2_FILTER4 = 101,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}
///Advanced encryption standard hardware accelerator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#AES)
pub type AES = crate::Periph<aes::RegisterBlock, 0x5006_0000>;
impl core::fmt::Debug for AES {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("AES").finish()
    }
}
///Advanced encryption standard hardware accelerator
pub mod aes;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM1)
pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for TIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM1").finish()
    }
}
///Advanced-timers
pub mod tim1;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM1)
pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_0400>;
impl core::fmt::Debug for TIM8 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM8").finish()
    }
}
///Advanced-timers
pub use self::tim1 as tim8;
///Analog-to-digital converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#ADC1)
pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2000>;
impl core::fmt::Debug for ADC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC1").finish()
    }
}
///Analog-to-digital converter
pub mod adc1;
///Basic timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM7)
pub type TIM7 = crate::Periph<tim7::RegisterBlock, 0x4000_1400>;
impl core::fmt::Debug for TIM7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM7").finish()
    }
}
///Basic timers
pub mod tim7;
///Basic timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM7)
pub type TIM6 = crate::Periph<tim7::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for TIM6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM6").finish()
    }
}
///Basic timers
pub use self::tim7 as tim6;
///Controller area network
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#CAN1)
pub type CAN1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
impl core::fmt::Debug for CAN1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CAN1").finish()
    }
}
///Controller area network
pub mod can1;
///Controller area network
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#CAN1)
pub type CAN2 = crate::Periph<can1::RegisterBlock, 0x4000_6800>;
impl core::fmt::Debug for CAN2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CAN2").finish()
    }
}
///Controller area network
pub use self::can1 as can2;
///Controller area network
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#CAN1)
pub type CAN3 = crate::Periph<can1::RegisterBlock, 0x4000_6c00>;
impl core::fmt::Debug for CAN3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CAN3").finish()
    }
}
///Controller area network
pub use self::can1 as can3;
///Cryptographic processor
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#CRC)
pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
impl core::fmt::Debug for CRC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRC").finish()
    }
}
///Cryptographic processor
pub mod crc;
///Debug support
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DBGMCU)
pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
impl core::fmt::Debug for DBGMCU {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DBGMCU").finish()
    }
}
///Debug support
pub mod dbgmcu;
///Digital filter for sigma delta modulators
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DFSDM2)
pub type DFSDM2 = crate::Periph<dfsdm2::RegisterBlock, 0x4001_6400>;
impl core::fmt::Debug for DFSDM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DFSDM2").finish()
    }
}
///Digital filter for sigma delta modulators
pub mod dfsdm2;
///Digital filter for sigma delta modulators
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DFSDM2)
pub type DFSDM1 = crate::Periph<dfsdm2::RegisterBlock, 0x4001_6000>;
impl core::fmt::Debug for DFSDM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DFSDM1").finish()
    }
}
///Digital filter for sigma delta modulators
pub use self::dfsdm2 as dfsdm1;
///Digital-to-analog converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DAC)
pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
impl core::fmt::Debug for DAC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC").finish()
    }
}
///Digital-to-analog converter
pub mod dac;
///DMA controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DMA1)
pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_6000>;
impl core::fmt::Debug for DMA1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA1").finish()
    }
}
///DMA controller
pub mod dma1;
///DMA controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DMA1)
pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_6400>;
impl core::fmt::Debug for DMA2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA2").finish()
    }
}
///DMA controller
pub use self::dma1 as dma2;
///External interrupt/event controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#EXTI)
pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_3c00>;
impl core::fmt::Debug for EXTI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EXTI").finish()
    }
}
///External interrupt/event controller
pub mod exti;
///fast-mode Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#FMPI2C1)
pub type FMPI2C1 = crate::Periph<fmpi2c1::RegisterBlock, 0x4000_6000>;
impl core::fmt::Debug for FMPI2C1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FMPI2C1").finish()
    }
}
///fast-mode Inter-integrated circuit
pub mod fmpi2c1;
///FLASH
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#FLASH)
pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_3c00>;
impl core::fmt::Debug for FLASH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FLASH").finish()
    }
}
///FLASH
pub mod flash;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM12)
pub type TIM12 = crate::Periph<tim12::RegisterBlock, 0x4000_1800>;
impl core::fmt::Debug for TIM12 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM12").finish()
    }
}
///General purpose timers
pub mod tim12;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM10)
pub type TIM10 = crate::Periph<tim10::RegisterBlock, 0x4001_4400>;
impl core::fmt::Debug for TIM10 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM10").finish()
    }
}
///General-purpose-timers
pub mod tim10;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM10)
pub type TIM13 = crate::Periph<tim10::RegisterBlock, 0x4000_1c00>;
impl core::fmt::Debug for TIM13 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM13").finish()
    }
}
///General purpose timers
pub use self::tim10 as tim13;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM10)
pub type TIM14 = crate::Periph<tim10::RegisterBlock, 0x4000_2000>;
impl core::fmt::Debug for TIM14 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM14").finish()
    }
}
///General-purpose-timers
pub use self::tim10 as tim14;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM12)
pub type TIM9 = crate::Periph<tim12::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for TIM9 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM9").finish()
    }
}
///General purpose timers
pub use self::tim12 as tim9;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM3)
pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
impl core::fmt::Debug for TIM3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM3").finish()
    }
}
///General purpose timers
pub mod tim3;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM3)
pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
impl core::fmt::Debug for TIM4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM4").finish()
    }
}
///General purpose timers
pub use self::tim3 as tim4;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM2)
pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for TIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM2").finish()
    }
}
///General purpose timers
pub mod tim2;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
pub type GPIOF = crate::Periph<gpiof::RegisterBlock, 0x4002_1400>;
impl core::fmt::Debug for GPIOF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOF").finish()
    }
}
///General-purpose I/Os
pub mod gpiof;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
pub type GPIOH = crate::Periph<gpiof::RegisterBlock, 0x4002_1c00>;
impl core::fmt::Debug for GPIOH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOH").finish()
    }
}
///General-purpose I/Os
pub use self::gpiof as gpioh;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
pub type GPIOE = crate::Periph<gpiof::RegisterBlock, 0x4002_1000>;
impl core::fmt::Debug for GPIOE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOE").finish()
    }
}
///General-purpose I/Os
pub use self::gpiof as gpioe;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
pub type GPIOC = crate::Periph<gpiof::RegisterBlock, 0x4002_0800>;
impl core::fmt::Debug for GPIOC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOC").finish()
    }
}
///General-purpose I/Os
pub use self::gpiof as gpioc;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
pub type GPIOG = crate::Periph<gpiof::RegisterBlock, 0x4002_1800>;
impl core::fmt::Debug for GPIOG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOG").finish()
    }
}
///General-purpose I/Os
pub use self::gpiof as gpiog;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
pub type GPIOD = crate::Periph<gpiof::RegisterBlock, 0x4002_0c00>;
impl core::fmt::Debug for GPIOD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOD").finish()
    }
}
///General-purpose I/Os
pub use self::gpiof as gpiod;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOB)
pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4002_0400>;
impl core::fmt::Debug for GPIOB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOB").finish()
    }
}
///General-purpose I/Os
pub mod gpiob;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOA)
pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for GPIOA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOA").finish()
    }
}
///General-purpose I/Os
pub mod gpioa;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM11)
pub type TIM11 = crate::Periph<tim11::RegisterBlock, 0x4001_4800>;
impl core::fmt::Debug for TIM11 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM11").finish()
    }
}
///General-purpose-timers
pub mod tim11;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM5)
pub type TIM5 = crate::Periph<tim5::RegisterBlock, 0x4000_0c00>;
impl core::fmt::Debug for TIM5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM5").finish()
    }
}
///General-purpose-timers
pub mod tim5;
///Independent watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#IWDG)
pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for IWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IWDG").finish()
    }
}
///Independent watchdog
pub mod iwdg;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
pub type I2S2EXT = crate::Periph<spi1::RegisterBlock, 0x4000_3400>;
impl core::fmt::Debug for I2S2EXT {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2S2EXT").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as i2s2ext;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#I2C1)
pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
impl core::fmt::Debug for I2C1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C1").finish()
    }
}
///Inter-integrated circuit
pub mod i2c1;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#I2C1)
pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
impl core::fmt::Debug for I2C2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C2").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c2;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#I2C1)
pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
impl core::fmt::Debug for I2C3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C3").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c3;
///Low power timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#LPTIM)
pub type LPTIM = crate::Periph<lptim::RegisterBlock, 0x4000_2400>;
impl core::fmt::Debug for LPTIM {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LPTIM").finish()
    }
}
///Low power timer
pub mod lptim;
///Power control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#PWR)
pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
impl core::fmt::Debug for PWR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PWR").finish()
    }
}
///Power control
pub mod pwr;
///QuadSPI interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#QUADSPI)
pub type QUADSPI = crate::Periph<quadspi::RegisterBlock, 0xa000_1000>;
impl core::fmt::Debug for QUADSPI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("QUADSPI").finish()
    }
}
///QuadSPI interface
pub mod quadspi;
///Random number generator
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#RNG)
pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
impl core::fmt::Debug for RNG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RNG").finish()
    }
}
///Random number generator
pub mod rng;
///Real-time clock
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#RTC)
pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
impl core::fmt::Debug for RTC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RTC").finish()
    }
}
///Real-time clock
pub mod rtc;
///Reset and clock control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#RCC)
pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_3800>;
impl core::fmt::Debug for RCC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RCC").finish()
    }
}
///Reset and clock control
pub mod rcc;
///Secure digital input/output interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SDIO)
pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_2c00>;
impl core::fmt::Debug for SDIO {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SDIO").finish()
    }
}
///Secure digital input/output interface
pub mod sdio;
///Serial audio interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SAI)
pub type SAI = crate::Periph<sai::RegisterBlock, 0x4001_5800>;
impl core::fmt::Debug for SAI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SAI").finish()
    }
}
///Serial audio interface
pub mod sai;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for SPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI1").finish()
    }
}
///Serial peripheral interface
pub mod spi1;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
pub type SPI5 = crate::Periph<spi1::RegisterBlock, 0x4001_5000>;
impl core::fmt::Debug for SPI5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI5").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as spi5;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4001_3400>;
impl core::fmt::Debug for SPI4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI4").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as spi4;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
impl core::fmt::Debug for SPI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI2").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as spi2;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
pub type SPI6 = crate::Periph<spi1::RegisterBlock, 0x4001_5400>;
impl core::fmt::Debug for SPI6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI6").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as spi6;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
impl core::fmt::Debug for SPI3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI3").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as spi3;
///Serial peripheral interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
pub type I2S3EXT = crate::Periph<spi1::RegisterBlock, 0x4000_4000>;
impl core::fmt::Debug for I2S3EXT {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2S3EXT").finish()
    }
}
///Serial peripheral interface
pub use self::spi1 as i2s3ext;
///System configuration controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SYSCFG)
pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_3800>;
impl core::fmt::Debug for SYSCFG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYSCFG").finish()
    }
}
///System configuration controller
pub mod syscfg;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#USART1)
pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_1000>;
impl core::fmt::Debug for USART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod usart1;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#USART1)
pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
impl core::fmt::Debug for USART3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART3").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart3;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#USART1)
pub type USART6 = crate::Periph<usart1::RegisterBlock, 0x4001_1400>;
impl core::fmt::Debug for USART6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART6").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart6;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#USART1)
pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
impl core::fmt::Debug for USART2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART2").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart2;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
impl core::fmt::Debug for UART4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART4").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod uart4;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
pub type UART10 = crate::Periph<uart4::RegisterBlock, 0x4001_1c00>;
impl core::fmt::Debug for UART10 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART10").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::uart4 as uart10;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
pub type UART9 = crate::Periph<uart4::RegisterBlock, 0x4001_1800>;
impl core::fmt::Debug for UART9 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART9").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::uart4 as uart9;
///USB on the go full speed
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#OTG_FS_DEVICE)
pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
impl core::fmt::Debug for OTG_FS_DEVICE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OTG_FS_DEVICE").finish()
    }
}
///USB on the go full speed
pub mod otg_fs_device;
///USB on the go full speed
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#OTG_FS_HOST)
pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
impl core::fmt::Debug for OTG_FS_HOST {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OTG_FS_HOST").finish()
    }
}
///USB on the go full speed
pub mod otg_fs_host;
///USB on the go full speed
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#OTG_FS_PWRCLK)
pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
impl core::fmt::Debug for OTG_FS_PWRCLK {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OTG_FS_PWRCLK").finish()
    }
}
///USB on the go full speed
pub mod otg_fs_pwrclk;
///USB on the go full speed
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#OTG_FS_GLOBAL)
pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
impl core::fmt::Debug for OTG_FS_GLOBAL {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OTG_FS_GLOBAL").finish()
    }
}
///USB on the go full speed
pub mod otg_fs_global;
///Window watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#WWDG)
pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
impl core::fmt::Debug for WWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WWDG").finish()
    }
}
///Window watchdog
pub mod wwdg;
///Flexible static memory controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#FSMC)
pub type FSMC = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
impl core::fmt::Debug for FSMC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FSMC").finish()
    }
}
///Flexible static memory controller
pub mod fsmc;
///ADC common registers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#ADC_Common)
pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4001_2300>;
impl core::fmt::Debug for ADC_COMMON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC_COMMON").finish()
    }
}
///ADC common registers
pub mod adc_common;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for UART5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART5").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::uart4 as uart5;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
pub type UART7 = crate::Periph<uart4::RegisterBlock, 0x4000_7800>;
impl core::fmt::Debug for UART7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART7").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::uart4 as uart7;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
pub type UART8 = crate::Periph<uart4::RegisterBlock, 0x4000_7c00>;
impl core::fmt::Debug for UART8 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART8").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::uart4 as uart8;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
/// All the peripherals.
#[allow(non_snake_case)]
pub struct Peripherals {
    ///AES
    pub AES: AES,
    ///TIM1
    pub TIM1: TIM1,
    ///TIM8
    pub TIM8: TIM8,
    ///ADC1
    pub ADC1: ADC1,
    ///TIM7
    pub TIM7: TIM7,
    ///TIM6
    pub TIM6: TIM6,
    ///CAN1
    pub CAN1: CAN1,
    ///CAN2
    pub CAN2: CAN2,
    ///CAN3
    pub CAN3: CAN3,
    ///CRC
    pub CRC: CRC,
    ///DBGMCU
    pub DBGMCU: DBGMCU,
    ///DFSDM2
    pub DFSDM2: DFSDM2,
    ///DFSDM1
    pub DFSDM1: DFSDM1,
    ///DAC
    pub DAC: DAC,
    ///DMA1
    pub DMA1: DMA1,
    ///DMA2
    pub DMA2: DMA2,
    ///EXTI
    pub EXTI: EXTI,
    ///FMPI2C1
    pub FMPI2C1: FMPI2C1,
    ///FLASH
    pub FLASH: FLASH,
    ///TIM12
    pub TIM12: TIM12,
    ///TIM10
    pub TIM10: TIM10,
    ///TIM13
    pub TIM13: TIM13,
    ///TIM14
    pub TIM14: TIM14,
    ///TIM9
    pub TIM9: TIM9,
    ///TIM3
    pub TIM3: TIM3,
    ///TIM4
    pub TIM4: TIM4,
    ///TIM2
    pub TIM2: TIM2,
    ///GPIOF
    pub GPIOF: GPIOF,
    ///GPIOH
    pub GPIOH: GPIOH,
    ///GPIOE
    pub GPIOE: GPIOE,
    ///GPIOC
    pub GPIOC: GPIOC,
    ///GPIOG
    pub GPIOG: GPIOG,
    ///GPIOD
    pub GPIOD: GPIOD,
    ///GPIOB
    pub GPIOB: GPIOB,
    ///GPIOA
    pub GPIOA: GPIOA,
    ///TIM11
    pub TIM11: TIM11,
    ///TIM5
    pub TIM5: TIM5,
    ///IWDG
    pub IWDG: IWDG,
    ///I2S2ext
    pub I2S2EXT: I2S2EXT,
    ///I2C1
    pub I2C1: I2C1,
    ///I2C2
    pub I2C2: I2C2,
    ///I2C3
    pub I2C3: I2C3,
    ///LPTIM
    pub LPTIM: LPTIM,
    ///PWR
    pub PWR: PWR,
    ///QUADSPI
    pub QUADSPI: QUADSPI,
    ///RNG
    pub RNG: RNG,
    ///RTC
    pub RTC: RTC,
    ///RCC
    pub RCC: RCC,
    ///SDIO
    pub SDIO: SDIO,
    ///SAI
    pub SAI: SAI,
    ///SPI1
    pub SPI1: SPI1,
    ///SPI5
    pub SPI5: SPI5,
    ///SPI4
    pub SPI4: SPI4,
    ///SPI2
    pub SPI2: SPI2,
    ///SPI6
    pub SPI6: SPI6,
    ///SPI3
    pub SPI3: SPI3,
    ///I2S3ext
    pub I2S3EXT: I2S3EXT,
    ///SYSCFG
    pub SYSCFG: SYSCFG,
    ///USART1
    pub USART1: USART1,
    ///USART3
    pub USART3: USART3,
    ///USART6
    pub USART6: USART6,
    ///USART2
    pub USART2: USART2,
    ///UART4
    pub UART4: UART4,
    ///UART10
    pub UART10: UART10,
    ///UART9
    pub UART9: UART9,
    ///OTG_FS_DEVICE
    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
    ///OTG_FS_HOST
    pub OTG_FS_HOST: OTG_FS_HOST,
    ///OTG_FS_PWRCLK
    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
    ///OTG_FS_GLOBAL
    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
    ///WWDG
    pub WWDG: WWDG,
    ///FSMC
    pub FSMC: FSMC,
    ///ADC_Common
    pub ADC_COMMON: ADC_COMMON,
    ///UART5
    pub UART5: UART5,
    ///UART7
    pub UART7: UART7,
    ///UART8
    pub UART8: UART8,
}
impl Peripherals {
    /// Returns all the peripherals *once*.
    #[cfg(feature = "critical-section")]
    #[inline]
    pub fn take() -> Option<Self> {
        critical_section::with(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                return None;
            }
            Some(unsafe { Peripherals::steal() })
        })
    }
    /// Unchecked version of `Peripherals::take`.
    ///
    /// # Safety
    ///
    /// Each of the returned peripherals must be used at most once.
    #[inline]
    pub unsafe fn steal() -> Self {
        DEVICE_PERIPHERALS = true;
        Peripherals {
            AES: AES::steal(),
            TIM1: TIM1::steal(),
            TIM8: TIM8::steal(),
            ADC1: ADC1::steal(),
            TIM7: TIM7::steal(),
            TIM6: TIM6::steal(),
            CAN1: CAN1::steal(),
            CAN2: CAN2::steal(),
            CAN3: CAN3::steal(),
            CRC: CRC::steal(),
            DBGMCU: DBGMCU::steal(),
            DFSDM2: DFSDM2::steal(),
            DFSDM1: DFSDM1::steal(),
            DAC: DAC::steal(),
            DMA1: DMA1::steal(),
            DMA2: DMA2::steal(),
            EXTI: EXTI::steal(),
            FMPI2C1: FMPI2C1::steal(),
            FLASH: FLASH::steal(),
            TIM12: TIM12::steal(),
            TIM10: TIM10::steal(),
            TIM13: TIM13::steal(),
            TIM14: TIM14::steal(),
            TIM9: TIM9::steal(),
            TIM3: TIM3::steal(),
            TIM4: TIM4::steal(),
            TIM2: TIM2::steal(),
            GPIOF: GPIOF::steal(),
            GPIOH: GPIOH::steal(),
            GPIOE: GPIOE::steal(),
            GPIOC: GPIOC::steal(),
            GPIOG: GPIOG::steal(),
            GPIOD: GPIOD::steal(),
            GPIOB: GPIOB::steal(),
            GPIOA: GPIOA::steal(),
            TIM11: TIM11::steal(),
            TIM5: TIM5::steal(),
            IWDG: IWDG::steal(),
            I2S2EXT: I2S2EXT::steal(),
            I2C1: I2C1::steal(),
            I2C2: I2C2::steal(),
            I2C3: I2C3::steal(),
            LPTIM: LPTIM::steal(),
            PWR: PWR::steal(),
            QUADSPI: QUADSPI::steal(),
            RNG: RNG::steal(),
            RTC: RTC::steal(),
            RCC: RCC::steal(),
            SDIO: SDIO::steal(),
            SAI: SAI::steal(),
            SPI1: SPI1::steal(),
            SPI5: SPI5::steal(),
            SPI4: SPI4::steal(),
            SPI2: SPI2::steal(),
            SPI6: SPI6::steal(),
            SPI3: SPI3::steal(),
            I2S3EXT: I2S3EXT::steal(),
            SYSCFG: SYSCFG::steal(),
            USART1: USART1::steal(),
            USART3: USART3::steal(),
            USART6: USART6::steal(),
            USART2: USART2::steal(),
            UART4: UART4::steal(),
            UART10: UART10::steal(),
            UART9: UART9::steal(),
            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
            OTG_FS_HOST: OTG_FS_HOST::steal(),
            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
            WWDG: WWDG::steal(),
            FSMC: FSMC::steal(),
            ADC_COMMON: ADC_COMMON::steal(),
            UART5: UART5::steal(),
            UART7: UART7::steal(),
            UART8: UART8::steal(),
        }
    }
}