#[doc = r" Value read from the register"]
pub struct R {
    bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
    bits: u32,
}
impl super::PLLI2SCFGR {
    #[doc = r" Modifies the contents of the register"]
    #[inline]
    pub fn modify<F>(&self, f: F)
    where
        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
    {
        let bits = self.register.get();
        let r = R { bits: bits };
        let mut w = W { bits: bits };
        f(&r, &mut w);
        self.register.set(w.bits);
    }
    #[doc = r" Reads the contents of the register"]
    #[inline]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
    #[doc = r" Writes to the register"]
    #[inline]
    pub fn write<F>(&self, f: F)
    where
        F: FnOnce(&mut W) -> &mut W,
    {
        let mut w = W::reset_value();
        f(&mut w);
        self.register.set(w.bits);
    }
    #[doc = r" Writes the reset value to the register"]
    #[inline]
    pub fn reset(&self) {
        self.write(|w| w)
    }
}
#[doc = r" Value of the field"]
pub struct PLLI2SRR {
    bits: u8,
}
impl PLLI2SRR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r" Value of the field"]
pub struct PLLI2SNR {
    bits: u16,
}
impl PLLI2SNR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u16 {
        self.bits
    }
}
#[doc = r" Value of the field"]
pub struct PLLI2SMR {
    bits: u8,
}
impl PLLI2SMR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = "Possible values of the field `PLLI2SSRC`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PLLI2SSRCR {
    #[doc = "HSE or HSI depending on PLLSRC of PLLCFGR"]
    HSE_HSI,
    #[doc = "External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry"]
    EXTERNAL,
}
impl PLLI2SSRCR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
    #[inline]
    pub fn bit_is_clear(&self) -> bool {
        !self.bit()
    }
    #[doc = r" Returns `true` if the bit is set (1)"]
    #[inline]
    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bit(&self) -> bool {
        match *self {
            PLLI2SSRCR::HSE_HSI => false,
            PLLI2SSRCR::EXTERNAL => true,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _from(value: bool) -> PLLI2SSRCR {
        match value {
            false => PLLI2SSRCR::HSE_HSI,
            true => PLLI2SSRCR::EXTERNAL,
        }
    }
    #[doc = "Checks if the value of the field is `HSE_HSI`"]
    #[inline]
    pub fn is_hse_hsi(&self) -> bool {
        *self == PLLI2SSRCR::HSE_HSI
    }
    #[doc = "Checks if the value of the field is `EXTERNAL`"]
    #[inline]
    pub fn is_external(&self) -> bool {
        *self == PLLI2SSRCR::EXTERNAL
    }
}
#[doc = r" Value of the field"]
pub struct PLLI2SQR {
    bits: u8,
}
impl PLLI2SQR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r" Proxy"]
pub struct _PLLI2SRW<'a> {
    w: &'a mut W,
}
impl<'a> _PLLI2SRW<'a> {
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 7;
        const OFFSET: u8 = 28;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = r" Proxy"]
pub struct _PLLI2SNW<'a> {
    w: &'a mut W,
}
impl<'a> _PLLI2SNW<'a> {
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u16) -> &'a mut W {
        const MASK: u16 = 511;
        const OFFSET: u8 = 6;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = r" Proxy"]
pub struct _PLLI2SMW<'a> {
    w: &'a mut W,
}
impl<'a> _PLLI2SMW<'a> {
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 63;
        const OFFSET: u8 = 0;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = "Values that can be written to the field `PLLI2SSRC`"]
pub enum PLLI2SSRCW {
    #[doc = "HSE or HSI depending on PLLSRC of PLLCFGR"]
    HSE_HSI,
    #[doc = "External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry"]
    EXTERNAL,
}
impl PLLI2SSRCW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline]
    pub fn _bits(&self) -> bool {
        match *self {
            PLLI2SSRCW::HSE_HSI => false,
            PLLI2SSRCW::EXTERNAL => true,
        }
    }
}
#[doc = r" Proxy"]
pub struct _PLLI2SSRCW<'a> {
    w: &'a mut W,
}
impl<'a> _PLLI2SSRCW<'a> {
    #[doc = r" Writes `variant` to the field"]
    #[inline]
    pub fn variant(self, variant: PLLI2SSRCW) -> &'a mut W {
        {
            self.bit(variant._bits())
        }
    }
    #[doc = "HSE or HSI depending on PLLSRC of PLLCFGR"]
    #[inline]
    pub fn hse_hsi(self) -> &'a mut W {
        self.variant(PLLI2SSRCW::HSE_HSI)
    }
    #[doc = "External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry"]
    #[inline]
    pub fn external(self) -> &'a mut W {
        self.variant(PLLI2SSRCW::EXTERNAL)
    }
    #[doc = r" Sets the field bit"]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r" Clears the field bit"]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub fn bit(self, value: bool) -> &'a mut W {
        const MASK: bool = true;
        const OFFSET: u8 = 22;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = r" Proxy"]
pub struct _PLLI2SQW<'a> {
    w: &'a mut W,
}
impl<'a> _PLLI2SQW<'a> {
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 15;
        const OFFSET: u8 = 24;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
impl R {
    #[doc = r" Value of the register as raw bits"]
    #[inline]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 28:30 - PLLI2S division factor for I2S clocks"]
    #[inline]
    pub fn plli2sr(&self) -> PLLI2SRR {
        let bits = {
            const MASK: u8 = 7;
            const OFFSET: u8 = 28;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        PLLI2SRR { bits }
    }
    #[doc = "Bits 6:14 - PLLI2S multiplication factor for VCO"]
    #[inline]
    pub fn plli2sn(&self) -> PLLI2SNR {
        let bits = {
            const MASK: u16 = 511;
            const OFFSET: u8 = 6;
            ((self.bits >> OFFSET) & MASK as u32) as u16
        };
        PLLI2SNR { bits }
    }
    #[doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
    #[inline]
    pub fn plli2sm(&self) -> PLLI2SMR {
        let bits = {
            const MASK: u8 = 63;
            const OFFSET: u8 = 0;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        PLLI2SMR { bits }
    }
    #[doc = "Bit 22 - PLLI2S entry clock source"]
    #[inline]
    pub fn plli2ssrc(&self) -> PLLI2SSRCR {
        PLLI2SSRCR::_from({
            const MASK: bool = true;
            const OFFSET: u8 = 22;
            ((self.bits >> OFFSET) & MASK as u32) != 0
        })
    }
    #[doc = "Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock"]
    #[inline]
    pub fn plli2sq(&self) -> PLLI2SQR {
        let bits = {
            const MASK: u8 = 15;
            const OFFSET: u8 = 24;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        PLLI2SQR { bits }
    }
}
impl W {
    #[doc = r" Reset value of the register"]
    #[inline]
    pub fn reset_value() -> W {
        W { bits: 536883200 }
    }
    #[doc = r" Writes raw bits to the register"]
    #[inline]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
    #[doc = "Bits 28:30 - PLLI2S division factor for I2S clocks"]
    #[inline]
    pub fn plli2sr(&mut self) -> _PLLI2SRW {
        _PLLI2SRW { w: self }
    }
    #[doc = "Bits 6:14 - PLLI2S multiplication factor for VCO"]
    #[inline]
    pub fn plli2sn(&mut self) -> _PLLI2SNW {
        _PLLI2SNW { w: self }
    }
    #[doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
    #[inline]
    pub fn plli2sm(&mut self) -> _PLLI2SMW {
        _PLLI2SMW { w: self }
    }
    #[doc = "Bit 22 - PLLI2S entry clock source"]
    #[inline]
    pub fn plli2ssrc(&mut self) -> _PLLI2SSRCW {
        _PLLI2SSRCW { w: self }
    }
    #[doc = "Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock"]
    #[inline]
    pub fn plli2sq(&mut self) -> _PLLI2SQW {
        _PLLI2SQW { w: self }
    }
}