#[doc = "Register `CR2` reader"]
pub struct R(crate::R<CR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR2` writer"]
pub struct W(crate::W<CR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Start conversion of regular channels\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SWSTART_A {
#[doc = "1: Starts conversion of regular channels"]
Start = 1,
}
impl From<SWSTART_A> for bool {
#[inline(always)]
fn from(variant: SWSTART_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SWSTART` reader - Start conversion of regular channels"]
pub type SWSTART_R = crate::BitReader<SWSTART_A>;
impl SWSTART_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> Option<SWSTART_A> {
match self.bits {
true => Some(SWSTART_A::Start),
_ => None,
}
}
#[doc = "Checks if the value of the field is `Start`"]
#[inline(always)]
pub fn is_start(&self) -> bool {
*self == SWSTART_A::Start
}
}
#[doc = "Field `SWSTART` writer - Start conversion of regular channels"]
pub type SWSTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, SWSTART_A, O>;
impl<'a, const O: u8> SWSTART_W<'a, O> {
#[doc = "Starts conversion of regular channels"]
#[inline(always)]
pub fn start(self) -> &'a mut W {
self.variant(SWSTART_A::Start)
}
}
#[doc = "External trigger enable for regular channels\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum EXTEN_A {
#[doc = "0: Trigger detection disabled"]
Disabled = 0,
#[doc = "1: Trigger detection on the rising edge"]
RisingEdge = 1,
#[doc = "2: Trigger detection on the falling edge"]
FallingEdge = 2,
#[doc = "3: Trigger detection on both the rising and falling edges"]
BothEdges = 3,
}
impl From<EXTEN_A> for u8 {
#[inline(always)]
fn from(variant: EXTEN_A) -> Self {
variant as _
}
}
#[doc = "Field `EXTEN` reader - External trigger enable for regular channels"]
pub type EXTEN_R = crate::FieldReader<u8, EXTEN_A>;
impl EXTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> EXTEN_A {
match self.bits {
0 => EXTEN_A::Disabled,
1 => EXTEN_A::RisingEdge,
2 => EXTEN_A::FallingEdge,
3 => EXTEN_A::BothEdges,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `Disabled`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == EXTEN_A::Disabled
}
#[doc = "Checks if the value of the field is `RisingEdge`"]
#[inline(always)]
pub fn is_rising_edge(&self) -> bool {
*self == EXTEN_A::RisingEdge
}
#[doc = "Checks if the value of the field is `FallingEdge`"]
#[inline(always)]
pub fn is_falling_edge(&self) -> bool {
*self == EXTEN_A::FallingEdge
}
#[doc = "Checks if the value of the field is `BothEdges`"]
#[inline(always)]
pub fn is_both_edges(&self) -> bool {
*self == EXTEN_A::BothEdges
}
}
#[doc = "Field `EXTEN` writer - External trigger enable for regular channels"]
pub type EXTEN_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR2_SPEC, u8, EXTEN_A, 2, O>;
impl<'a, const O: u8> EXTEN_W<'a, O> {
#[doc = "Trigger detection disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(EXTEN_A::Disabled)
}
#[doc = "Trigger detection on the rising edge"]
#[inline(always)]
pub fn rising_edge(self) -> &'a mut W {
self.variant(EXTEN_A::RisingEdge)
}
#[doc = "Trigger detection on the falling edge"]
#[inline(always)]
pub fn falling_edge(self) -> &'a mut W {
self.variant(EXTEN_A::FallingEdge)
}
#[doc = "Trigger detection on both the rising and falling edges"]
#[inline(always)]
pub fn both_edges(self) -> &'a mut W {
self.variant(EXTEN_A::BothEdges)
}
}
#[doc = "External event select for regular group\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum EXTSEL_A {
#[doc = "0: Timer 1 CC1 event"]
Tim1cc1 = 0,
#[doc = "1: Timer 1 CC2 event"]
Tim1cc2 = 1,
#[doc = "2: Timer 1 CC3 event"]
Tim1cc3 = 2,
#[doc = "3: Timer 2 CC2 event"]
Tim2cc2 = 3,
#[doc = "4: Timer 2 CC3 event"]
Tim2cc3 = 4,
#[doc = "5: Timer 2 CC4 event"]
Tim2cc4 = 5,
#[doc = "6: Timer 2 TRGO event"]
Tim2trgo = 6,
#[doc = "7: Timer 3 CC1 event"]
Tim3cc1 = 7,
#[doc = "8: Timer 3 TRGO event"]
Tim3trgo = 8,
#[doc = "9: Timer 4 CC4 event"]
Tim4cc4 = 9,
#[doc = "10: Timer 5 CC1 event"]
Tim5cc1 = 10,
#[doc = "11: Timer 5 CC2 event"]
Tim5cc2 = 11,
#[doc = "12: Timer 5 CC3 event"]
Tim5cc3 = 12,
#[doc = "13: Timer 8 CC1 event"]
Tim8cc1 = 13,
#[doc = "14: Timer 8 TRGO event"]
Tim8trgo = 14,
#[doc = "15: EXTI line 11"]
Exti11 = 15,
}
impl From<EXTSEL_A> for u8 {
#[inline(always)]
fn from(variant: EXTSEL_A) -> Self {
variant as _
}
}
#[doc = "Field `EXTSEL` reader - External event select for regular group"]
pub type EXTSEL_R = crate::FieldReader<u8, EXTSEL_A>;
impl EXTSEL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> EXTSEL_A {
match self.bits {
0 => EXTSEL_A::Tim1cc1,
1 => EXTSEL_A::Tim1cc2,
2 => EXTSEL_A::Tim1cc3,
3 => EXTSEL_A::Tim2cc2,
4 => EXTSEL_A::Tim2cc3,
5 => EXTSEL_A::Tim2cc4,
6 => EXTSEL_A::Tim2trgo,
7 => EXTSEL_A::Tim3cc1,
8 => EXTSEL_A::Tim3trgo,
9 => EXTSEL_A::Tim4cc4,
10 => EXTSEL_A::Tim5cc1,
11 => EXTSEL_A::Tim5cc2,
12 => EXTSEL_A::Tim5cc3,
13 => EXTSEL_A::Tim8cc1,
14 => EXTSEL_A::Tim8trgo,
15 => EXTSEL_A::Exti11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `Tim1cc1`"]
#[inline(always)]
pub fn is_tim1cc1(&self) -> bool {
*self == EXTSEL_A::Tim1cc1
}
#[doc = "Checks if the value of the field is `Tim1cc2`"]
#[inline(always)]
pub fn is_tim1cc2(&self) -> bool {
*self == EXTSEL_A::Tim1cc2
}
#[doc = "Checks if the value of the field is `Tim1cc3`"]
#[inline(always)]
pub fn is_tim1cc3(&self) -> bool {
*self == EXTSEL_A::Tim1cc3
}
#[doc = "Checks if the value of the field is `Tim2cc2`"]
#[inline(always)]
pub fn is_tim2cc2(&self) -> bool {
*self == EXTSEL_A::Tim2cc2
}
#[doc = "Checks if the value of the field is `Tim2cc3`"]
#[inline(always)]
pub fn is_tim2cc3(&self) -> bool {
*self == EXTSEL_A::Tim2cc3
}
#[doc = "Checks if the value of the field is `Tim2cc4`"]
#[inline(always)]
pub fn is_tim2cc4(&self) -> bool {
*self == EXTSEL_A::Tim2cc4
}
#[doc = "Checks if the value of the field is `Tim2trgo`"]
#[inline(always)]
pub fn is_tim2trgo(&self) -> bool {
*self == EXTSEL_A::Tim2trgo
}
#[doc = "Checks if the value of the field is `Tim3cc1`"]
#[inline(always)]
pub fn is_tim3cc1(&self) -> bool {
*self == EXTSEL_A::Tim3cc1
}
#[doc = "Checks if the value of the field is `Tim3trgo`"]
#[inline(always)]
pub fn is_tim3trgo(&self) -> bool {
*self == EXTSEL_A::Tim3trgo
}
#[doc = "Checks if the value of the field is `Tim4cc4`"]
#[inline(always)]
pub fn is_tim4cc4(&self) -> bool {
*self == EXTSEL_A::Tim4cc4
}
#[doc = "Checks if the value of the field is `Tim5cc1`"]
#[inline(always)]
pub fn is_tim5cc1(&self) -> bool {
*self == EXTSEL_A::Tim5cc1
}
#[doc = "Checks if the value of the field is `Tim5cc2`"]
#[inline(always)]
pub fn is_tim5cc2(&self) -> bool {
*self == EXTSEL_A::Tim5cc2
}
#[doc = "Checks if the value of the field is `Tim5cc3`"]
#[inline(always)]
pub fn is_tim5cc3(&self) -> bool {
*self == EXTSEL_A::Tim5cc3
}
#[doc = "Checks if the value of the field is `Tim8cc1`"]
#[inline(always)]
pub fn is_tim8cc1(&self) -> bool {
*self == EXTSEL_A::Tim8cc1
}
#[doc = "Checks if the value of the field is `Tim8trgo`"]
#[inline(always)]
pub fn is_tim8trgo(&self) -> bool {
*self == EXTSEL_A::Tim8trgo
}
#[doc = "Checks if the value of the field is `Exti11`"]
#[inline(always)]
pub fn is_exti11(&self) -> bool {
*self == EXTSEL_A::Exti11
}
}
#[doc = "Field `EXTSEL` writer - External event select for regular group"]
pub type EXTSEL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR2_SPEC, u8, EXTSEL_A, 4, O>;
impl<'a, const O: u8> EXTSEL_W<'a, O> {
#[doc = "Timer 1 CC1 event"]
#[inline(always)]
pub fn tim1cc1(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim1cc1)
}
#[doc = "Timer 1 CC2 event"]
#[inline(always)]
pub fn tim1cc2(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim1cc2)
}
#[doc = "Timer 1 CC3 event"]
#[inline(always)]
pub fn tim1cc3(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim1cc3)
}
#[doc = "Timer 2 CC2 event"]
#[inline(always)]
pub fn tim2cc2(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim2cc2)
}
#[doc = "Timer 2 CC3 event"]
#[inline(always)]
pub fn tim2cc3(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim2cc3)
}
#[doc = "Timer 2 CC4 event"]
#[inline(always)]
pub fn tim2cc4(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim2cc4)
}
#[doc = "Timer 2 TRGO event"]
#[inline(always)]
pub fn tim2trgo(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim2trgo)
}
#[doc = "Timer 3 CC1 event"]
#[inline(always)]
pub fn tim3cc1(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim3cc1)
}
#[doc = "Timer 3 TRGO event"]
#[inline(always)]
pub fn tim3trgo(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim3trgo)
}
#[doc = "Timer 4 CC4 event"]
#[inline(always)]
pub fn tim4cc4(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim4cc4)
}
#[doc = "Timer 5 CC1 event"]
#[inline(always)]
pub fn tim5cc1(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim5cc1)
}
#[doc = "Timer 5 CC2 event"]
#[inline(always)]
pub fn tim5cc2(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim5cc2)
}
#[doc = "Timer 5 CC3 event"]
#[inline(always)]
pub fn tim5cc3(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim5cc3)
}
#[doc = "Timer 8 CC1 event"]
#[inline(always)]
pub fn tim8cc1(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim8cc1)
}
#[doc = "Timer 8 TRGO event"]
#[inline(always)]
pub fn tim8trgo(self) -> &'a mut W {
self.variant(EXTSEL_A::Tim8trgo)
}
#[doc = "EXTI line 11"]
#[inline(always)]
pub fn exti11(self) -> &'a mut W {
self.variant(EXTSEL_A::Exti11)
}
}
#[doc = "Start conversion of injected channels\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum JSWSTART_A {
#[doc = "1: Starts conversion of injected channels"]
Start = 1,
}
impl From<JSWSTART_A> for bool {
#[inline(always)]
fn from(variant: JSWSTART_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `JSWSTART` reader - Start conversion of injected channels"]
pub type JSWSTART_R = crate::BitReader<JSWSTART_A>;
impl JSWSTART_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> Option<JSWSTART_A> {
match self.bits {
true => Some(JSWSTART_A::Start),
_ => None,
}
}
#[doc = "Checks if the value of the field is `Start`"]
#[inline(always)]
pub fn is_start(&self) -> bool {
*self == JSWSTART_A::Start
}
}
#[doc = "Field `JSWSTART` writer - Start conversion of injected channels"]
pub type JSWSTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, JSWSTART_A, O>;
impl<'a, const O: u8> JSWSTART_W<'a, O> {
#[doc = "Starts conversion of injected channels"]
#[inline(always)]
pub fn start(self) -> &'a mut W {
self.variant(JSWSTART_A::Start)
}
}
#[doc = "External trigger enable for injected channels\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum JEXTEN_A {
#[doc = "0: Trigger detection disabled"]
Disabled = 0,
#[doc = "1: Trigger detection on the rising edge"]
RisingEdge = 1,
#[doc = "2: Trigger detection on the falling edge"]
FallingEdge = 2,
#[doc = "3: Trigger detection on both the rising and falling edges"]
BothEdges = 3,
}
impl From<JEXTEN_A> for u8 {
#[inline(always)]
fn from(variant: JEXTEN_A) -> Self {
variant as _
}
}
#[doc = "Field `JEXTEN` reader - External trigger enable for injected channels"]
pub type JEXTEN_R = crate::FieldReader<u8, JEXTEN_A>;
impl JEXTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> JEXTEN_A {
match self.bits {
0 => JEXTEN_A::Disabled,
1 => JEXTEN_A::RisingEdge,
2 => JEXTEN_A::FallingEdge,
3 => JEXTEN_A::BothEdges,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `Disabled`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == JEXTEN_A::Disabled
}
#[doc = "Checks if the value of the field is `RisingEdge`"]
#[inline(always)]
pub fn is_rising_edge(&self) -> bool {
*self == JEXTEN_A::RisingEdge
}
#[doc = "Checks if the value of the field is `FallingEdge`"]
#[inline(always)]
pub fn is_falling_edge(&self) -> bool {
*self == JEXTEN_A::FallingEdge
}
#[doc = "Checks if the value of the field is `BothEdges`"]
#[inline(always)]
pub fn is_both_edges(&self) -> bool {
*self == JEXTEN_A::BothEdges
}
}
#[doc = "Field `JEXTEN` writer - External trigger enable for injected channels"]
pub type JEXTEN_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR2_SPEC, u8, JEXTEN_A, 2, O>;
impl<'a, const O: u8> JEXTEN_W<'a, O> {
#[doc = "Trigger detection disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(JEXTEN_A::Disabled)
}
#[doc = "Trigger detection on the rising edge"]
#[inline(always)]
pub fn rising_edge(self) -> &'a mut W {
self.variant(JEXTEN_A::RisingEdge)
}
#[doc = "Trigger detection on the falling edge"]
#[inline(always)]
pub fn falling_edge(self) -> &'a mut W {
self.variant(JEXTEN_A::FallingEdge)
}
#[doc = "Trigger detection on both the rising and falling edges"]
#[inline(always)]
pub fn both_edges(self) -> &'a mut W {
self.variant(JEXTEN_A::BothEdges)
}
}
#[doc = "External event select for injected group\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum JEXTSEL_A {
#[doc = "0: Timer 1 CC4 event"]
Tim1cc4 = 0,
#[doc = "1: Timer 1 TRGO event"]
Tim1trgo = 1,
#[doc = "2: Timer 2 CC1 event"]
Tim2cc1 = 2,
#[doc = "3: Timer 2 TRGO event"]
Tim2trgo = 3,
#[doc = "4: Timer 3 CC2 event"]
Tim3cc2 = 4,
#[doc = "5: Timer 3 CC4 event"]
Tim3cc4 = 5,
#[doc = "6: Timer 4 CC1 event"]
Tim4cc1 = 6,
#[doc = "7: Timer 4 CC2 event"]
Tim4cc2 = 7,
#[doc = "8: Timer 4 CC3 event"]
Tim4cc3 = 8,
#[doc = "9: Timer 4 TRGO event"]
Tim4trgo = 9,
#[doc = "10: Timer 5 CC4 event"]
Tim5cc4 = 10,
#[doc = "11: Timer 5 TRGO event"]
Tim5trgo = 11,
#[doc = "12: Timer 8 CC2 event"]
Tim8cc2 = 12,
#[doc = "13: Timer 8 CC3 event"]
Tim8cc3 = 13,
#[doc = "14: Timer 8 CC4 event"]
Tim8cc4 = 14,
#[doc = "15: EXTI line 15"]
Exti15 = 15,
}
impl From<JEXTSEL_A> for u8 {
#[inline(always)]
fn from(variant: JEXTSEL_A) -> Self {
variant as _
}
}
#[doc = "Field `JEXTSEL` reader - External event select for injected group"]
pub type JEXTSEL_R = crate::FieldReader<u8, JEXTSEL_A>;
impl JEXTSEL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> JEXTSEL_A {
match self.bits {
0 => JEXTSEL_A::Tim1cc4,
1 => JEXTSEL_A::Tim1trgo,
2 => JEXTSEL_A::Tim2cc1,
3 => JEXTSEL_A::Tim2trgo,
4 => JEXTSEL_A::Tim3cc2,
5 => JEXTSEL_A::Tim3cc4,
6 => JEXTSEL_A::Tim4cc1,
7 => JEXTSEL_A::Tim4cc2,
8 => JEXTSEL_A::Tim4cc3,
9 => JEXTSEL_A::Tim4trgo,
10 => JEXTSEL_A::Tim5cc4,
11 => JEXTSEL_A::Tim5trgo,
12 => JEXTSEL_A::Tim8cc2,
13 => JEXTSEL_A::Tim8cc3,
14 => JEXTSEL_A::Tim8cc4,
15 => JEXTSEL_A::Exti15,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `Tim1cc4`"]
#[inline(always)]
pub fn is_tim1cc4(&self) -> bool {
*self == JEXTSEL_A::Tim1cc4
}
#[doc = "Checks if the value of the field is `Tim1trgo`"]
#[inline(always)]
pub fn is_tim1trgo(&self) -> bool {
*self == JEXTSEL_A::Tim1trgo
}
#[doc = "Checks if the value of the field is `Tim2cc1`"]
#[inline(always)]
pub fn is_tim2cc1(&self) -> bool {
*self == JEXTSEL_A::Tim2cc1
}
#[doc = "Checks if the value of the field is `Tim2trgo`"]
#[inline(always)]
pub fn is_tim2trgo(&self) -> bool {
*self == JEXTSEL_A::Tim2trgo
}
#[doc = "Checks if the value of the field is `Tim3cc2`"]
#[inline(always)]
pub fn is_tim3cc2(&self) -> bool {
*self == JEXTSEL_A::Tim3cc2
}
#[doc = "Checks if the value of the field is `Tim3cc4`"]
#[inline(always)]
pub fn is_tim3cc4(&self) -> bool {
*self == JEXTSEL_A::Tim3cc4
}
#[doc = "Checks if the value of the field is `Tim4cc1`"]
#[inline(always)]
pub fn is_tim4cc1(&self) -> bool {
*self == JEXTSEL_A::Tim4cc1
}
#[doc = "Checks if the value of the field is `Tim4cc2`"]
#[inline(always)]
pub fn is_tim4cc2(&self) -> bool {
*self == JEXTSEL_A::Tim4cc2
}
#[doc = "Checks if the value of the field is `Tim4cc3`"]
#[inline(always)]
pub fn is_tim4cc3(&self) -> bool {
*self == JEXTSEL_A::Tim4cc3
}
#[doc = "Checks if the value of the field is `Tim4trgo`"]
#[inline(always)]
pub fn is_tim4trgo(&self) -> bool {
*self == JEXTSEL_A::Tim4trgo
}
#[doc = "Checks if the value of the field is `Tim5cc4`"]
#[inline(always)]
pub fn is_tim5cc4(&self) -> bool {
*self == JEXTSEL_A::Tim5cc4
}
#[doc = "Checks if the value of the field is `Tim5trgo`"]
#[inline(always)]
pub fn is_tim5trgo(&self) -> bool {
*self == JEXTSEL_A::Tim5trgo
}
#[doc = "Checks if the value of the field is `Tim8cc2`"]
#[inline(always)]
pub fn is_tim8cc2(&self) -> bool {
*self == JEXTSEL_A::Tim8cc2
}
#[doc = "Checks if the value of the field is `Tim8cc3`"]
#[inline(always)]
pub fn is_tim8cc3(&self) -> bool {
*self == JEXTSEL_A::Tim8cc3
}
#[doc = "Checks if the value of the field is `Tim8cc4`"]
#[inline(always)]
pub fn is_tim8cc4(&self) -> bool {
*self == JEXTSEL_A::Tim8cc4
}
#[doc = "Checks if the value of the field is `Exti15`"]
#[inline(always)]
pub fn is_exti15(&self) -> bool {
*self == JEXTSEL_A::Exti15
}
}
#[doc = "Field `JEXTSEL` writer - External event select for injected group"]
pub type JEXTSEL_W<'a, const O: u8> =
crate::FieldWriterSafe<'a, u32, CR2_SPEC, u8, JEXTSEL_A, 4, O>;
impl<'a, const O: u8> JEXTSEL_W<'a, O> {
#[doc = "Timer 1 CC4 event"]
#[inline(always)]
pub fn tim1cc4(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim1cc4)
}
#[doc = "Timer 1 TRGO event"]
#[inline(always)]
pub fn tim1trgo(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim1trgo)
}
#[doc = "Timer 2 CC1 event"]
#[inline(always)]
pub fn tim2cc1(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim2cc1)
}
#[doc = "Timer 2 TRGO event"]
#[inline(always)]
pub fn tim2trgo(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim2trgo)
}
#[doc = "Timer 3 CC2 event"]
#[inline(always)]
pub fn tim3cc2(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim3cc2)
}
#[doc = "Timer 3 CC4 event"]
#[inline(always)]
pub fn tim3cc4(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim3cc4)
}
#[doc = "Timer 4 CC1 event"]
#[inline(always)]
pub fn tim4cc1(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim4cc1)
}
#[doc = "Timer 4 CC2 event"]
#[inline(always)]
pub fn tim4cc2(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim4cc2)
}
#[doc = "Timer 4 CC3 event"]
#[inline(always)]
pub fn tim4cc3(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim4cc3)
}
#[doc = "Timer 4 TRGO event"]
#[inline(always)]
pub fn tim4trgo(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim4trgo)
}
#[doc = "Timer 5 CC4 event"]
#[inline(always)]
pub fn tim5cc4(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim5cc4)
}
#[doc = "Timer 5 TRGO event"]
#[inline(always)]
pub fn tim5trgo(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim5trgo)
}
#[doc = "Timer 8 CC2 event"]
#[inline(always)]
pub fn tim8cc2(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim8cc2)
}
#[doc = "Timer 8 CC3 event"]
#[inline(always)]
pub fn tim8cc3(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim8cc3)
}
#[doc = "Timer 8 CC4 event"]
#[inline(always)]
pub fn tim8cc4(self) -> &'a mut W {
self.variant(JEXTSEL_A::Tim8cc4)
}
#[doc = "EXTI line 15"]
#[inline(always)]
pub fn exti15(self) -> &'a mut W {
self.variant(JEXTSEL_A::Exti15)
}
}
#[doc = "Data alignment\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ALIGN_A {
#[doc = "0: Right alignment"]
Right = 0,
#[doc = "1: Left alignment"]
Left = 1,
}
impl From<ALIGN_A> for bool {
#[inline(always)]
fn from(variant: ALIGN_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ALIGN` reader - Data alignment"]
pub type ALIGN_R = crate::BitReader<ALIGN_A>;
impl ALIGN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> ALIGN_A {
match self.bits {
false => ALIGN_A::Right,
true => ALIGN_A::Left,
}
}
#[doc = "Checks if the value of the field is `Right`"]
#[inline(always)]
pub fn is_right(&self) -> bool {
*self == ALIGN_A::Right
}
#[doc = "Checks if the value of the field is `Left`"]
#[inline(always)]
pub fn is_left(&self) -> bool {
*self == ALIGN_A::Left
}
}
#[doc = "Field `ALIGN` writer - Data alignment"]
pub type ALIGN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, ALIGN_A, O>;
impl<'a, const O: u8> ALIGN_W<'a, O> {
#[doc = "Right alignment"]
#[inline(always)]
pub fn right(self) -> &'a mut W {
self.variant(ALIGN_A::Right)
}
#[doc = "Left alignment"]
#[inline(always)]
pub fn left(self) -> &'a mut W {
self.variant(ALIGN_A::Left)
}
}
#[doc = "End of conversion selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EOCS_A {
#[doc = "0: The EOC bit is set at the end of each sequence of regular conversions"]
EachSequence = 0,
#[doc = "1: The EOC bit is set at the end of each regular conversion"]
EachConversion = 1,
}
impl From<EOCS_A> for bool {
#[inline(always)]
fn from(variant: EOCS_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `EOCS` reader - End of conversion selection"]
pub type EOCS_R = crate::BitReader<EOCS_A>;
impl EOCS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> EOCS_A {
match self.bits {
false => EOCS_A::EachSequence,
true => EOCS_A::EachConversion,
}
}
#[doc = "Checks if the value of the field is `EachSequence`"]
#[inline(always)]
pub fn is_each_sequence(&self) -> bool {
*self == EOCS_A::EachSequence
}
#[doc = "Checks if the value of the field is `EachConversion`"]
#[inline(always)]
pub fn is_each_conversion(&self) -> bool {
*self == EOCS_A::EachConversion
}
}
#[doc = "Field `EOCS` writer - End of conversion selection"]
pub type EOCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, EOCS_A, O>;
impl<'a, const O: u8> EOCS_W<'a, O> {
#[doc = "The EOC bit is set at the end of each sequence of regular conversions"]
#[inline(always)]
pub fn each_sequence(self) -> &'a mut W {
self.variant(EOCS_A::EachSequence)
}
#[doc = "The EOC bit is set at the end of each regular conversion"]
#[inline(always)]
pub fn each_conversion(self) -> &'a mut W {
self.variant(EOCS_A::EachConversion)
}
}
#[doc = "DMA disable selection (for single ADC mode)\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DDS_A {
#[doc = "0: No new DMA request is issued after the last transfer"]
Single = 0,
#[doc = "1: DMA requests are issued as long as data are converted and DMA=1"]
Continuous = 1,
}
impl From<DDS_A> for bool {
#[inline(always)]
fn from(variant: DDS_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DDS` reader - DMA disable selection (for single ADC mode)"]
pub type DDS_R = crate::BitReader<DDS_A>;
impl DDS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> DDS_A {
match self.bits {
false => DDS_A::Single,
true => DDS_A::Continuous,
}
}
#[doc = "Checks if the value of the field is `Single`"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == DDS_A::Single
}
#[doc = "Checks if the value of the field is `Continuous`"]
#[inline(always)]
pub fn is_continuous(&self) -> bool {
*self == DDS_A::Continuous
}
}
#[doc = "Field `DDS` writer - DMA disable selection (for single ADC mode)"]
pub type DDS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, DDS_A, O>;
impl<'a, const O: u8> DDS_W<'a, O> {
#[doc = "No new DMA request is issued after the last transfer"]
#[inline(always)]
pub fn single(self) -> &'a mut W {
self.variant(DDS_A::Single)
}
#[doc = "DMA requests are issued as long as data are converted and DMA=1"]
#[inline(always)]
pub fn continuous(self) -> &'a mut W {
self.variant(DDS_A::Continuous)
}
}
#[doc = "Direct memory access mode (for single ADC mode)\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMA_A {
#[doc = "0: DMA mode disabled"]
Disabled = 0,
#[doc = "1: DMA mode enabled"]
Enabled = 1,
}
impl From<DMA_A> for bool {
#[inline(always)]
fn from(variant: DMA_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DMA` reader - Direct memory access mode (for single ADC mode)"]
pub type DMA_R = crate::BitReader<DMA_A>;
impl DMA_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> DMA_A {
match self.bits {
false => DMA_A::Disabled,
true => DMA_A::Enabled,
}
}
#[doc = "Checks if the value of the field is `Disabled`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == DMA_A::Disabled
}
#[doc = "Checks if the value of the field is `Enabled`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == DMA_A::Enabled
}
}
#[doc = "Field `DMA` writer - Direct memory access mode (for single ADC mode)"]
pub type DMA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, DMA_A, O>;
impl<'a, const O: u8> DMA_W<'a, O> {
#[doc = "DMA mode disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(DMA_A::Disabled)
}
#[doc = "DMA mode enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(DMA_A::Enabled)
}
}
#[doc = "Continuous conversion\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CONT_A {
#[doc = "0: Single conversion mode"]
Single = 0,
#[doc = "1: Continuous conversion mode"]
Continuous = 1,
}
impl From<CONT_A> for bool {
#[inline(always)]
fn from(variant: CONT_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CONT` reader - Continuous conversion"]
pub type CONT_R = crate::BitReader<CONT_A>;
impl CONT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> CONT_A {
match self.bits {
false => CONT_A::Single,
true => CONT_A::Continuous,
}
}
#[doc = "Checks if the value of the field is `Single`"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == CONT_A::Single
}
#[doc = "Checks if the value of the field is `Continuous`"]
#[inline(always)]
pub fn is_continuous(&self) -> bool {
*self == CONT_A::Continuous
}
}
#[doc = "Field `CONT` writer - Continuous conversion"]
pub type CONT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, CONT_A, O>;
impl<'a, const O: u8> CONT_W<'a, O> {
#[doc = "Single conversion mode"]
#[inline(always)]
pub fn single(self) -> &'a mut W {
self.variant(CONT_A::Single)
}
#[doc = "Continuous conversion mode"]
#[inline(always)]
pub fn continuous(self) -> &'a mut W {
self.variant(CONT_A::Continuous)
}
}
#[doc = "A/D Converter ON / OFF\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADON_A {
#[doc = "0: Disable ADC conversion and go to power down mode"]
Disabled = 0,
#[doc = "1: Enable ADC"]
Enabled = 1,
}
impl From<ADON_A> for bool {
#[inline(always)]
fn from(variant: ADON_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ADON` reader - A/D Converter ON / OFF"]
pub type ADON_R = crate::BitReader<ADON_A>;
impl ADON_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> ADON_A {
match self.bits {
false => ADON_A::Disabled,
true => ADON_A::Enabled,
}
}
#[doc = "Checks if the value of the field is `Disabled`"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == ADON_A::Disabled
}
#[doc = "Checks if the value of the field is `Enabled`"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == ADON_A::Enabled
}
}
#[doc = "Field `ADON` writer - A/D Converter ON / OFF"]
pub type ADON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, ADON_A, O>;
impl<'a, const O: u8> ADON_W<'a, O> {
#[doc = "Disable ADC conversion and go to power down mode"]
#[inline(always)]
pub fn disabled(self) -> &'a mut W {
self.variant(ADON_A::Disabled)
}
#[doc = "Enable ADC"]
#[inline(always)]
pub fn enabled(self) -> &'a mut W {
self.variant(ADON_A::Enabled)
}
}
impl R {
#[doc = "Bit 30 - Start conversion of regular channels"]
#[inline(always)]
pub fn swstart(&self) -> SWSTART_R {
SWSTART_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bits 28:29 - External trigger enable for regular channels"]
#[inline(always)]
pub fn exten(&self) -> EXTEN_R {
EXTEN_R::new(((self.bits >> 28) & 3) as u8)
}
#[doc = "Bits 24:27 - External event select for regular group"]
#[inline(always)]
pub fn extsel(&self) -> EXTSEL_R {
EXTSEL_R::new(((self.bits >> 24) & 0x0f) as u8)
}
#[doc = "Bit 22 - Start conversion of injected channels"]
#[inline(always)]
pub fn jswstart(&self) -> JSWSTART_R {
JSWSTART_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bits 20:21 - External trigger enable for injected channels"]
#[inline(always)]
pub fn jexten(&self) -> JEXTEN_R {
JEXTEN_R::new(((self.bits >> 20) & 3) as u8)
}
#[doc = "Bits 16:19 - External event select for injected group"]
#[inline(always)]
pub fn jextsel(&self) -> JEXTSEL_R {
JEXTSEL_R::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bit 11 - Data alignment"]
#[inline(always)]
pub fn align(&self) -> ALIGN_R {
ALIGN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 10 - End of conversion selection"]
#[inline(always)]
pub fn eocs(&self) -> EOCS_R {
EOCS_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 9 - DMA disable selection (for single ADC mode)"]
#[inline(always)]
pub fn dds(&self) -> DDS_R {
DDS_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 8 - Direct memory access mode (for single ADC mode)"]
#[inline(always)]
pub fn dma(&self) -> DMA_R {
DMA_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 1 - Continuous conversion"]
#[inline(always)]
pub fn cont(&self) -> CONT_R {
CONT_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 0 - A/D Converter ON / OFF"]
#[inline(always)]
pub fn adon(&self) -> ADON_R {
ADON_R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 30 - Start conversion of regular channels"]
#[inline(always)]
pub fn swstart(&mut self) -> SWSTART_W<30> {
SWSTART_W::new(self)
}
#[doc = "Bits 28:29 - External trigger enable for regular channels"]
#[inline(always)]
pub fn exten(&mut self) -> EXTEN_W<28> {
EXTEN_W::new(self)
}
#[doc = "Bits 24:27 - External event select for regular group"]
#[inline(always)]
pub fn extsel(&mut self) -> EXTSEL_W<24> {
EXTSEL_W::new(self)
}
#[doc = "Bit 22 - Start conversion of injected channels"]
#[inline(always)]
pub fn jswstart(&mut self) -> JSWSTART_W<22> {
JSWSTART_W::new(self)
}
#[doc = "Bits 20:21 - External trigger enable for injected channels"]
#[inline(always)]
pub fn jexten(&mut self) -> JEXTEN_W<20> {
JEXTEN_W::new(self)
}
#[doc = "Bits 16:19 - External event select for injected group"]
#[inline(always)]
pub fn jextsel(&mut self) -> JEXTSEL_W<16> {
JEXTSEL_W::new(self)
}
#[doc = "Bit 11 - Data alignment"]
#[inline(always)]
pub fn align(&mut self) -> ALIGN_W<11> {
ALIGN_W::new(self)
}
#[doc = "Bit 10 - End of conversion selection"]
#[inline(always)]
pub fn eocs(&mut self) -> EOCS_W<10> {
EOCS_W::new(self)
}
#[doc = "Bit 9 - DMA disable selection (for single ADC mode)"]
#[inline(always)]
pub fn dds(&mut self) -> DDS_W<9> {
DDS_W::new(self)
}
#[doc = "Bit 8 - Direct memory access mode (for single ADC mode)"]
#[inline(always)]
pub fn dma(&mut self) -> DMA_W<8> {
DMA_W::new(self)
}
#[doc = "Bit 1 - Continuous conversion"]
#[inline(always)]
pub fn cont(&mut self) -> CONT_W<1> {
CONT_W::new(self)
}
#[doc = "Bit 0 - A/D Converter ON / OFF"]
#[inline(always)]
pub fn adon(&mut self) -> ADON_W<0> {
ADON_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"]
pub struct CR2_SPEC;
impl crate::RegisterSpec for CR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr2::R](R) reader structure"]
impl crate::Readable for CR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"]
impl crate::Writable for CR2_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for CR2_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}