#[doc = "Reader of register CR2"]
pub type R = crate::R<u32, super::CR2>;
#[doc = "Writer for register CR2"]
pub type W = crate::W<u32, super::CR2>;
#[doc = "Register CR2 `reset()`'s with value 0"]
impl crate::ResetValue for super::CR2 {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "TI1 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TI1S_A {
#[doc = "0: The TIMx_CH1 pin is connected to TI1 input"]
NORMAL = 0,
#[doc = "1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
XOR = 1,
}
impl From<TI1S_A> for bool {
#[inline(always)]
fn from(variant: TI1S_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `TI1S`"]
pub type TI1S_R = crate::R<bool, TI1S_A>;
impl TI1S_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> TI1S_A {
match self.bits {
false => TI1S_A::NORMAL,
true => TI1S_A::XOR,
}
}
#[doc = "Checks if the value of the field is `NORMAL`"]
#[inline(always)]
pub fn is_normal(&self) -> bool {
*self == TI1S_A::NORMAL
}
#[doc = "Checks if the value of the field is `XOR`"]
#[inline(always)]
pub fn is_xor(&self) -> bool {
*self == TI1S_A::XOR
}
}
#[doc = "Write proxy for field `TI1S`"]
pub struct TI1S_W<'a> {
w: &'a mut W,
}
impl<'a> TI1S_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TI1S_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "The TIMx_CH1 pin is connected to TI1 input"]
#[inline(always)]
pub fn normal(self) -> &'a mut W {
self.variant(TI1S_A::NORMAL)
}
#[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
#[inline(always)]
pub fn xor(self) -> &'a mut W {
self.variant(TI1S_A::XOR)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
self.w
}
}
#[doc = "Master mode selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum MMS_A {
#[doc = "0: The UG bit from the TIMx_EGR register is used as trigger output"]
RESET = 0,
#[doc = "1: The counter enable signal, CNT_EN, is used as trigger output"]
ENABLE = 1,
#[doc = "2: The update event is selected as trigger output"]
UPDATE = 2,
#[doc = "3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
COMPAREPULSE = 3,
#[doc = "4: OC1REF signal is used as trigger output"]
COMPAREOC1 = 4,
#[doc = "5: OC2REF signal is used as trigger output"]
COMPAREOC2 = 5,
#[doc = "6: OC3REF signal is used as trigger output"]
COMPAREOC3 = 6,
#[doc = "7: OC4REF signal is used as trigger output"]
COMPAREOC4 = 7,
}
impl From<MMS_A> for u8 {
#[inline(always)]
fn from(variant: MMS_A) -> Self {
variant as _
}
}
#[doc = "Reader of field `MMS`"]
pub type MMS_R = crate::R<u8, MMS_A>;
impl MMS_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> MMS_A {
match self.bits {
0 => MMS_A::RESET,
1 => MMS_A::ENABLE,
2 => MMS_A::UPDATE,
3 => MMS_A::COMPAREPULSE,
4 => MMS_A::COMPAREOC1,
5 => MMS_A::COMPAREOC2,
6 => MMS_A::COMPAREOC3,
7 => MMS_A::COMPAREOC4,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `RESET`"]
#[inline(always)]
pub fn is_reset(&self) -> bool {
*self == MMS_A::RESET
}
#[doc = "Checks if the value of the field is `ENABLE`"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == MMS_A::ENABLE
}
#[doc = "Checks if the value of the field is `UPDATE`"]
#[inline(always)]
pub fn is_update(&self) -> bool {
*self == MMS_A::UPDATE
}
#[doc = "Checks if the value of the field is `COMPAREPULSE`"]
#[inline(always)]
pub fn is_compare_pulse(&self) -> bool {
*self == MMS_A::COMPAREPULSE
}
#[doc = "Checks if the value of the field is `COMPAREOC1`"]
#[inline(always)]
pub fn is_compare_oc1(&self) -> bool {
*self == MMS_A::COMPAREOC1
}
#[doc = "Checks if the value of the field is `COMPAREOC2`"]
#[inline(always)]
pub fn is_compare_oc2(&self) -> bool {
*self == MMS_A::COMPAREOC2
}
#[doc = "Checks if the value of the field is `COMPAREOC3`"]
#[inline(always)]
pub fn is_compare_oc3(&self) -> bool {
*self == MMS_A::COMPAREOC3
}
#[doc = "Checks if the value of the field is `COMPAREOC4`"]
#[inline(always)]
pub fn is_compare_oc4(&self) -> bool {
*self == MMS_A::COMPAREOC4
}
}
#[doc = "Write proxy for field `MMS`"]
pub struct MMS_W<'a> {
w: &'a mut W,
}
impl<'a> MMS_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: MMS_A) -> &'a mut W {
{
self.bits(variant.into())
}
}
#[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
#[inline(always)]
pub fn reset(self) -> &'a mut W {
self.variant(MMS_A::RESET)
}
#[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
#[inline(always)]
pub fn enable(self) -> &'a mut W {
self.variant(MMS_A::ENABLE)
}
#[doc = "The update event is selected as trigger output"]
#[inline(always)]
pub fn update(self) -> &'a mut W {
self.variant(MMS_A::UPDATE)
}
#[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
#[inline(always)]
pub fn compare_pulse(self) -> &'a mut W {
self.variant(MMS_A::COMPAREPULSE)
}
#[doc = "OC1REF signal is used as trigger output"]
#[inline(always)]
pub fn compare_oc1(self) -> &'a mut W {
self.variant(MMS_A::COMPAREOC1)
}
#[doc = "OC2REF signal is used as trigger output"]
#[inline(always)]
pub fn compare_oc2(self) -> &'a mut W {
self.variant(MMS_A::COMPAREOC2)
}
#[doc = "OC3REF signal is used as trigger output"]
#[inline(always)]
pub fn compare_oc3(self) -> &'a mut W {
self.variant(MMS_A::COMPAREOC3)
}
#[doc = "OC4REF signal is used as trigger output"]
#[inline(always)]
pub fn compare_oc4(self) -> &'a mut W {
self.variant(MMS_A::COMPAREOC4)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
self.w
}
}
#[doc = "Capture/compare DMA selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CCDS_A {
#[doc = "0: CCx DMA request sent when CCx event occurs"]
ONCOMPARE = 0,
#[doc = "1: CCx DMA request sent when update event occurs"]
ONUPDATE = 1,
}
impl From<CCDS_A> for bool {
#[inline(always)]
fn from(variant: CCDS_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `CCDS`"]
pub type CCDS_R = crate::R<bool, CCDS_A>;
impl CCDS_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> CCDS_A {
match self.bits {
false => CCDS_A::ONCOMPARE,
true => CCDS_A::ONUPDATE,
}
}
#[doc = "Checks if the value of the field is `ONCOMPARE`"]
#[inline(always)]
pub fn is_on_compare(&self) -> bool {
*self == CCDS_A::ONCOMPARE
}
#[doc = "Checks if the value of the field is `ONUPDATE`"]
#[inline(always)]
pub fn is_on_update(&self) -> bool {
*self == CCDS_A::ONUPDATE
}
}
#[doc = "Write proxy for field `CCDS`"]
pub struct CCDS_W<'a> {
w: &'a mut W,
}
impl<'a> CCDS_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CCDS_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "CCx DMA request sent when CCx event occurs"]
#[inline(always)]
pub fn on_compare(self) -> &'a mut W {
self.variant(CCDS_A::ONCOMPARE)
}
#[doc = "CCx DMA request sent when update event occurs"]
#[inline(always)]
pub fn on_update(self) -> &'a mut W {
self.variant(CCDS_A::ONUPDATE)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
self.w
}
}
impl R {
#[doc = "Bit 7 - TI1 selection"]
#[inline(always)]
pub fn ti1s(&self) -> TI1S_R {
TI1S_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bits 4:6 - Master mode selection"]
#[inline(always)]
pub fn mms(&self) -> MMS_R {
MMS_R::new(((self.bits >> 4) & 0x07) as u8)
}
#[doc = "Bit 3 - Capture/compare DMA selection"]
#[inline(always)]
pub fn ccds(&self) -> CCDS_R {
CCDS_R::new(((self.bits >> 3) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 7 - TI1 selection"]
#[inline(always)]
pub fn ti1s(&mut self) -> TI1S_W {
TI1S_W { w: self }
}
#[doc = "Bits 4:6 - Master mode selection"]
#[inline(always)]
pub fn mms(&mut self) -> MMS_W {
MMS_W { w: self }
}
#[doc = "Bit 3 - Capture/compare DMA selection"]
#[inline(always)]
pub fn ccds(&mut self) -> CCDS_W {
CCDS_W { w: self }
}
}