stm32f3/stm32f303/syscfg/
cfgr1.rs

1///Register `CFGR1` reader
2pub type R = crate::R<CFGR1rs>;
3///Register `CFGR1` writer
4pub type W = crate::W<CFGR1rs>;
5/**Memory mapping selection bits
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum MEM_MODE {
12    ///0: Main Flash memory mapped at 0x0000_0000
13    MainFlash = 0,
14    ///1: System Flash memory mapped at 0x0000_0000
15    SystemFlash = 1,
16    ///3: Embedded SRAM mapped at 0x0000_0000
17    Sram = 3,
18    ///4: FMC Bank (Only the first two banks) (Available on STM32F303xD/E only)
19    Fmc = 4,
20}
21impl From<MEM_MODE> for u8 {
22    #[inline(always)]
23    fn from(variant: MEM_MODE) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for MEM_MODE {
28    type Ux = u8;
29}
30impl crate::IsEnum for MEM_MODE {}
31///Field `MEM_MODE` reader - Memory mapping selection bits
32pub type MEM_MODE_R = crate::FieldReader<MEM_MODE>;
33impl MEM_MODE_R {
34    ///Get enumerated values variant
35    #[inline(always)]
36    pub const fn variant(&self) -> Option<MEM_MODE> {
37        match self.bits {
38            0 => Some(MEM_MODE::MainFlash),
39            1 => Some(MEM_MODE::SystemFlash),
40            3 => Some(MEM_MODE::Sram),
41            4 => Some(MEM_MODE::Fmc),
42            _ => None,
43        }
44    }
45    ///Main Flash memory mapped at 0x0000_0000
46    #[inline(always)]
47    pub fn is_main_flash(&self) -> bool {
48        *self == MEM_MODE::MainFlash
49    }
50    ///System Flash memory mapped at 0x0000_0000
51    #[inline(always)]
52    pub fn is_system_flash(&self) -> bool {
53        *self == MEM_MODE::SystemFlash
54    }
55    ///Embedded SRAM mapped at 0x0000_0000
56    #[inline(always)]
57    pub fn is_sram(&self) -> bool {
58        *self == MEM_MODE::Sram
59    }
60    ///FMC Bank (Only the first two banks) (Available on STM32F303xD/E only)
61    #[inline(always)]
62    pub fn is_fmc(&self) -> bool {
63        *self == MEM_MODE::Fmc
64    }
65}
66///Field `MEM_MODE` writer - Memory mapping selection bits
67pub type MEM_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, MEM_MODE>;
68impl<'a, REG> MEM_MODE_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    ///Main Flash memory mapped at 0x0000_0000
74    #[inline(always)]
75    pub fn main_flash(self) -> &'a mut crate::W<REG> {
76        self.variant(MEM_MODE::MainFlash)
77    }
78    ///System Flash memory mapped at 0x0000_0000
79    #[inline(always)]
80    pub fn system_flash(self) -> &'a mut crate::W<REG> {
81        self.variant(MEM_MODE::SystemFlash)
82    }
83    ///Embedded SRAM mapped at 0x0000_0000
84    #[inline(always)]
85    pub fn sram(self) -> &'a mut crate::W<REG> {
86        self.variant(MEM_MODE::Sram)
87    }
88    ///FMC Bank (Only the first two banks) (Available on STM32F303xD/E only)
89    #[inline(always)]
90    pub fn fmc(self) -> &'a mut crate::W<REG> {
91        self.variant(MEM_MODE::Fmc)
92    }
93}
94/**USB interrupt remap
95
96Value on reset: 0*/
97#[cfg_attr(feature = "defmt", derive(defmt::Format))]
98#[derive(Clone, Copy, Debug, PartialEq, Eq)]
99pub enum USB_IT_RMP {
100    ///0: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively
101    NotRemapped = 0,
102    ///1: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively
103    Remapped = 1,
104}
105impl From<USB_IT_RMP> for bool {
106    #[inline(always)]
107    fn from(variant: USB_IT_RMP) -> Self {
108        variant as u8 != 0
109    }
110}
111///Field `USB_IT_RMP` reader - USB interrupt remap
112pub type USB_IT_RMP_R = crate::BitReader<USB_IT_RMP>;
113impl USB_IT_RMP_R {
114    ///Get enumerated values variant
115    #[inline(always)]
116    pub const fn variant(&self) -> USB_IT_RMP {
117        match self.bits {
118            false => USB_IT_RMP::NotRemapped,
119            true => USB_IT_RMP::Remapped,
120        }
121    }
122    ///USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively
123    #[inline(always)]
124    pub fn is_not_remapped(&self) -> bool {
125        *self == USB_IT_RMP::NotRemapped
126    }
127    ///USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively
128    #[inline(always)]
129    pub fn is_remapped(&self) -> bool {
130        *self == USB_IT_RMP::Remapped
131    }
132}
133///Field `USB_IT_RMP` writer - USB interrupt remap
134pub type USB_IT_RMP_W<'a, REG> = crate::BitWriter<'a, REG, USB_IT_RMP>;
135impl<'a, REG> USB_IT_RMP_W<'a, REG>
136where
137    REG: crate::Writable + crate::RegisterSpec,
138{
139    ///USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively
140    #[inline(always)]
141    pub fn not_remapped(self) -> &'a mut crate::W<REG> {
142        self.variant(USB_IT_RMP::NotRemapped)
143    }
144    ///USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively
145    #[inline(always)]
146    pub fn remapped(self) -> &'a mut crate::W<REG> {
147        self.variant(USB_IT_RMP::Remapped)
148    }
149}
150/**Timer 1 ITR3 selection
151
152Value on reset: 0*/
153#[cfg_attr(feature = "defmt", derive(defmt::Format))]
154#[derive(Clone, Copy, Debug, PartialEq, Eq)]
155pub enum TIM1_ITR3_RMP {
156    ///0: TIM1_ITR3 = TIM4_TRGO in STM32F303xB/C and STM32F358xC devices
157    NotRemapped = 0,
158    ///1: TIM1_ITR3 = TIM17_OC
159    Remapped = 1,
160}
161impl From<TIM1_ITR3_RMP> for bool {
162    #[inline(always)]
163    fn from(variant: TIM1_ITR3_RMP) -> Self {
164        variant as u8 != 0
165    }
166}
167///Field `TIM1_ITR3_RMP` reader - Timer 1 ITR3 selection
168pub type TIM1_ITR3_RMP_R = crate::BitReader<TIM1_ITR3_RMP>;
169impl TIM1_ITR3_RMP_R {
170    ///Get enumerated values variant
171    #[inline(always)]
172    pub const fn variant(&self) -> TIM1_ITR3_RMP {
173        match self.bits {
174            false => TIM1_ITR3_RMP::NotRemapped,
175            true => TIM1_ITR3_RMP::Remapped,
176        }
177    }
178    ///TIM1_ITR3 = TIM4_TRGO in STM32F303xB/C and STM32F358xC devices
179    #[inline(always)]
180    pub fn is_not_remapped(&self) -> bool {
181        *self == TIM1_ITR3_RMP::NotRemapped
182    }
183    ///TIM1_ITR3 = TIM17_OC
184    #[inline(always)]
185    pub fn is_remapped(&self) -> bool {
186        *self == TIM1_ITR3_RMP::Remapped
187    }
188}
189///Field `TIM1_ITR3_RMP` writer - Timer 1 ITR3 selection
190pub type TIM1_ITR3_RMP_W<'a, REG> = crate::BitWriter<'a, REG, TIM1_ITR3_RMP>;
191impl<'a, REG> TIM1_ITR3_RMP_W<'a, REG>
192where
193    REG: crate::Writable + crate::RegisterSpec,
194{
195    ///TIM1_ITR3 = TIM4_TRGO in STM32F303xB/C and STM32F358xC devices
196    #[inline(always)]
197    pub fn not_remapped(self) -> &'a mut crate::W<REG> {
198        self.variant(TIM1_ITR3_RMP::NotRemapped)
199    }
200    ///TIM1_ITR3 = TIM17_OC
201    #[inline(always)]
202    pub fn remapped(self) -> &'a mut crate::W<REG> {
203        self.variant(TIM1_ITR3_RMP::Remapped)
204    }
205}
206/**DAC trigger remap (when TSEL = 001)
207
208Value on reset: 0*/
209#[cfg_attr(feature = "defmt", derive(defmt::Format))]
210#[derive(Clone, Copy, Debug, PartialEq, Eq)]
211pub enum DAC1_TRIG_RMP {
212    ///0: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices
213    NotRemapped = 0,
214    ///1: DAC trigger is TIM3_TRGO
215    Remapped = 1,
216}
217impl From<DAC1_TRIG_RMP> for bool {
218    #[inline(always)]
219    fn from(variant: DAC1_TRIG_RMP) -> Self {
220        variant as u8 != 0
221    }
222}
223///Field `DAC1_TRIG_RMP` reader - DAC trigger remap (when TSEL = 001)
224pub type DAC1_TRIG_RMP_R = crate::BitReader<DAC1_TRIG_RMP>;
225impl DAC1_TRIG_RMP_R {
226    ///Get enumerated values variant
227    #[inline(always)]
228    pub const fn variant(&self) -> DAC1_TRIG_RMP {
229        match self.bits {
230            false => DAC1_TRIG_RMP::NotRemapped,
231            true => DAC1_TRIG_RMP::Remapped,
232        }
233    }
234    ///DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices
235    #[inline(always)]
236    pub fn is_not_remapped(&self) -> bool {
237        *self == DAC1_TRIG_RMP::NotRemapped
238    }
239    ///DAC trigger is TIM3_TRGO
240    #[inline(always)]
241    pub fn is_remapped(&self) -> bool {
242        *self == DAC1_TRIG_RMP::Remapped
243    }
244}
245///Field `DAC1_TRIG_RMP` writer - DAC trigger remap (when TSEL = 001)
246pub type DAC1_TRIG_RMP_W<'a, REG> = crate::BitWriter<'a, REG, DAC1_TRIG_RMP>;
247impl<'a, REG> DAC1_TRIG_RMP_W<'a, REG>
248where
249    REG: crate::Writable + crate::RegisterSpec,
250{
251    ///DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices
252    #[inline(always)]
253    pub fn not_remapped(self) -> &'a mut crate::W<REG> {
254        self.variant(DAC1_TRIG_RMP::NotRemapped)
255    }
256    ///DAC trigger is TIM3_TRGO
257    #[inline(always)]
258    pub fn remapped(self) -> &'a mut crate::W<REG> {
259        self.variant(DAC1_TRIG_RMP::Remapped)
260    }
261}
262/**ADC24 DMA remapping bit
263
264Value on reset: 0*/
265#[cfg_attr(feature = "defmt", derive(defmt::Format))]
266#[derive(Clone, Copy, Debug, PartialEq, Eq)]
267pub enum ADC2_DMA_RMP {
268    ///0: ADC24 DMA requests mapped on DMA2 channels 1 and 2
269    NotRemapped = 0,
270    ///1: ADC24 DMA requests mapped on DMA2 channels 3 and 4
271    Remapped = 1,
272}
273impl From<ADC2_DMA_RMP> for bool {
274    #[inline(always)]
275    fn from(variant: ADC2_DMA_RMP) -> Self {
276        variant as u8 != 0
277    }
278}
279///Field `ADC2_DMA_RMP` reader - ADC24 DMA remapping bit
280pub type ADC2_DMA_RMP_R = crate::BitReader<ADC2_DMA_RMP>;
281impl ADC2_DMA_RMP_R {
282    ///Get enumerated values variant
283    #[inline(always)]
284    pub const fn variant(&self) -> ADC2_DMA_RMP {
285        match self.bits {
286            false => ADC2_DMA_RMP::NotRemapped,
287            true => ADC2_DMA_RMP::Remapped,
288        }
289    }
290    ///ADC24 DMA requests mapped on DMA2 channels 1 and 2
291    #[inline(always)]
292    pub fn is_not_remapped(&self) -> bool {
293        *self == ADC2_DMA_RMP::NotRemapped
294    }
295    ///ADC24 DMA requests mapped on DMA2 channels 3 and 4
296    #[inline(always)]
297    pub fn is_remapped(&self) -> bool {
298        *self == ADC2_DMA_RMP::Remapped
299    }
300}
301///Field `ADC2_DMA_RMP` writer - ADC24 DMA remapping bit
302pub type ADC2_DMA_RMP_W<'a, REG> = crate::BitWriter<'a, REG, ADC2_DMA_RMP>;
303impl<'a, REG> ADC2_DMA_RMP_W<'a, REG>
304where
305    REG: crate::Writable + crate::RegisterSpec,
306{
307    ///ADC24 DMA requests mapped on DMA2 channels 1 and 2
308    #[inline(always)]
309    pub fn not_remapped(self) -> &'a mut crate::W<REG> {
310        self.variant(ADC2_DMA_RMP::NotRemapped)
311    }
312    ///ADC24 DMA requests mapped on DMA2 channels 3 and 4
313    #[inline(always)]
314    pub fn remapped(self) -> &'a mut crate::W<REG> {
315        self.variant(ADC2_DMA_RMP::Remapped)
316    }
317}
318/**TIM16 DMA request remapping bit
319
320Value on reset: 0*/
321#[cfg_attr(feature = "defmt", derive(defmt::Format))]
322#[derive(Clone, Copy, Debug, PartialEq, Eq)]
323pub enum TIM16_DMA_RMP {
324    ///0: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3
325    NotRemapped = 0,
326    ///1: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4
327    Remapped = 1,
328}
329impl From<TIM16_DMA_RMP> for bool {
330    #[inline(always)]
331    fn from(variant: TIM16_DMA_RMP) -> Self {
332        variant as u8 != 0
333    }
334}
335///Field `TIM16_DMA_RMP` reader - TIM16 DMA request remapping bit
336pub type TIM16_DMA_RMP_R = crate::BitReader<TIM16_DMA_RMP>;
337impl TIM16_DMA_RMP_R {
338    ///Get enumerated values variant
339    #[inline(always)]
340    pub const fn variant(&self) -> TIM16_DMA_RMP {
341        match self.bits {
342            false => TIM16_DMA_RMP::NotRemapped,
343            true => TIM16_DMA_RMP::Remapped,
344        }
345    }
346    ///TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3
347    #[inline(always)]
348    pub fn is_not_remapped(&self) -> bool {
349        *self == TIM16_DMA_RMP::NotRemapped
350    }
351    ///TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4
352    #[inline(always)]
353    pub fn is_remapped(&self) -> bool {
354        *self == TIM16_DMA_RMP::Remapped
355    }
356}
357///Field `TIM16_DMA_RMP` writer - TIM16 DMA request remapping bit
358pub type TIM16_DMA_RMP_W<'a, REG> = crate::BitWriter<'a, REG, TIM16_DMA_RMP>;
359impl<'a, REG> TIM16_DMA_RMP_W<'a, REG>
360where
361    REG: crate::Writable + crate::RegisterSpec,
362{
363    ///TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3
364    #[inline(always)]
365    pub fn not_remapped(self) -> &'a mut crate::W<REG> {
366        self.variant(TIM16_DMA_RMP::NotRemapped)
367    }
368    ///TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4
369    #[inline(always)]
370    pub fn remapped(self) -> &'a mut crate::W<REG> {
371        self.variant(TIM16_DMA_RMP::Remapped)
372    }
373}
374/**TIM17 DMA request remapping bit
375
376Value on reset: 0*/
377#[cfg_attr(feature = "defmt", derive(defmt::Format))]
378#[derive(Clone, Copy, Debug, PartialEq, Eq)]
379pub enum TIM17_DMA_RMP {
380    ///0: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
381    NotRemapped = 0,
382    ///1: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2
383    Remapped = 1,
384}
385impl From<TIM17_DMA_RMP> for bool {
386    #[inline(always)]
387    fn from(variant: TIM17_DMA_RMP) -> Self {
388        variant as u8 != 0
389    }
390}
391///Field `TIM17_DMA_RMP` reader - TIM17 DMA request remapping bit
392pub type TIM17_DMA_RMP_R = crate::BitReader<TIM17_DMA_RMP>;
393impl TIM17_DMA_RMP_R {
394    ///Get enumerated values variant
395    #[inline(always)]
396    pub const fn variant(&self) -> TIM17_DMA_RMP {
397        match self.bits {
398            false => TIM17_DMA_RMP::NotRemapped,
399            true => TIM17_DMA_RMP::Remapped,
400        }
401    }
402    ///TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
403    #[inline(always)]
404    pub fn is_not_remapped(&self) -> bool {
405        *self == TIM17_DMA_RMP::NotRemapped
406    }
407    ///TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2
408    #[inline(always)]
409    pub fn is_remapped(&self) -> bool {
410        *self == TIM17_DMA_RMP::Remapped
411    }
412}
413///Field `TIM17_DMA_RMP` writer - TIM17 DMA request remapping bit
414pub type TIM17_DMA_RMP_W<'a, REG> = crate::BitWriter<'a, REG, TIM17_DMA_RMP>;
415impl<'a, REG> TIM17_DMA_RMP_W<'a, REG>
416where
417    REG: crate::Writable + crate::RegisterSpec,
418{
419    ///TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
420    #[inline(always)]
421    pub fn not_remapped(self) -> &'a mut crate::W<REG> {
422        self.variant(TIM17_DMA_RMP::NotRemapped)
423    }
424    ///TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2
425    #[inline(always)]
426    pub fn remapped(self) -> &'a mut crate::W<REG> {
427        self.variant(TIM17_DMA_RMP::Remapped)
428    }
429}
430/**TIM6 and DAC1 DMA request remapping bit
431
432Value on reset: 0*/
433#[cfg_attr(feature = "defmt", derive(defmt::Format))]
434#[derive(Clone, Copy, Debug, PartialEq, Eq)]
435pub enum TIM6_DAC1_CH1_DMA_RMP {
436    ///0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 in STM32F303xB/C and STM32F358xC
437    NotRemapped = 0,
438    ///1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3
439    Remapped = 1,
440}
441impl From<TIM6_DAC1_CH1_DMA_RMP> for bool {
442    #[inline(always)]
443    fn from(variant: TIM6_DAC1_CH1_DMA_RMP) -> Self {
444        variant as u8 != 0
445    }
446}
447///Field `TIM6_DAC1_CH1_DMA_RMP` reader - TIM6 and DAC1 DMA request remapping bit
448pub type TIM6_DAC1_CH1_DMA_RMP_R = crate::BitReader<TIM6_DAC1_CH1_DMA_RMP>;
449impl TIM6_DAC1_CH1_DMA_RMP_R {
450    ///Get enumerated values variant
451    #[inline(always)]
452    pub const fn variant(&self) -> TIM6_DAC1_CH1_DMA_RMP {
453        match self.bits {
454            false => TIM6_DAC1_CH1_DMA_RMP::NotRemapped,
455            true => TIM6_DAC1_CH1_DMA_RMP::Remapped,
456        }
457    }
458    ///TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 in STM32F303xB/C and STM32F358xC
459    #[inline(always)]
460    pub fn is_not_remapped(&self) -> bool {
461        *self == TIM6_DAC1_CH1_DMA_RMP::NotRemapped
462    }
463    ///TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3
464    #[inline(always)]
465    pub fn is_remapped(&self) -> bool {
466        *self == TIM6_DAC1_CH1_DMA_RMP::Remapped
467    }
468}
469///Field `TIM6_DAC1_CH1_DMA_RMP` writer - TIM6 and DAC1 DMA request remapping bit
470pub type TIM6_DAC1_CH1_DMA_RMP_W<'a, REG> = crate::BitWriter<'a, REG, TIM6_DAC1_CH1_DMA_RMP>;
471impl<'a, REG> TIM6_DAC1_CH1_DMA_RMP_W<'a, REG>
472where
473    REG: crate::Writable + crate::RegisterSpec,
474{
475    ///TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 in STM32F303xB/C and STM32F358xC
476    #[inline(always)]
477    pub fn not_remapped(self) -> &'a mut crate::W<REG> {
478        self.variant(TIM6_DAC1_CH1_DMA_RMP::NotRemapped)
479    }
480    ///TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3
481    #[inline(always)]
482    pub fn remapped(self) -> &'a mut crate::W<REG> {
483        self.variant(TIM6_DAC1_CH1_DMA_RMP::Remapped)
484    }
485}
486/**TIM7 and DAC2 DMA request remapping bit
487
488Value on reset: 0*/
489#[cfg_attr(feature = "defmt", derive(defmt::Format))]
490#[derive(Clone, Copy, Debug, PartialEq, Eq)]
491pub enum TIM7_DAC1_CH2_DMA_RMP {
492    ///0: TIM7_UP and DAC_CH2 DMA requests mapped on DMA2 channel 4 in STM32F303xB/C and STM32F358xC devices
493    NotRemapped = 0,
494    ///1: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4
495    Remapped = 1,
496}
497impl From<TIM7_DAC1_CH2_DMA_RMP> for bool {
498    #[inline(always)]
499    fn from(variant: TIM7_DAC1_CH2_DMA_RMP) -> Self {
500        variant as u8 != 0
501    }
502}
503///Field `TIM7_DAC1_CH2_DMA_RMP` reader - TIM7 and DAC2 DMA request remapping bit
504pub type TIM7_DAC1_CH2_DMA_RMP_R = crate::BitReader<TIM7_DAC1_CH2_DMA_RMP>;
505impl TIM7_DAC1_CH2_DMA_RMP_R {
506    ///Get enumerated values variant
507    #[inline(always)]
508    pub const fn variant(&self) -> TIM7_DAC1_CH2_DMA_RMP {
509        match self.bits {
510            false => TIM7_DAC1_CH2_DMA_RMP::NotRemapped,
511            true => TIM7_DAC1_CH2_DMA_RMP::Remapped,
512        }
513    }
514    ///TIM7_UP and DAC_CH2 DMA requests mapped on DMA2 channel 4 in STM32F303xB/C and STM32F358xC devices
515    #[inline(always)]
516    pub fn is_not_remapped(&self) -> bool {
517        *self == TIM7_DAC1_CH2_DMA_RMP::NotRemapped
518    }
519    ///TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4
520    #[inline(always)]
521    pub fn is_remapped(&self) -> bool {
522        *self == TIM7_DAC1_CH2_DMA_RMP::Remapped
523    }
524}
525///Field `TIM7_DAC1_CH2_DMA_RMP` writer - TIM7 and DAC2 DMA request remapping bit
526pub type TIM7_DAC1_CH2_DMA_RMP_W<'a, REG> = crate::BitWriter<'a, REG, TIM7_DAC1_CH2_DMA_RMP>;
527impl<'a, REG> TIM7_DAC1_CH2_DMA_RMP_W<'a, REG>
528where
529    REG: crate::Writable + crate::RegisterSpec,
530{
531    ///TIM7_UP and DAC_CH2 DMA requests mapped on DMA2 channel 4 in STM32F303xB/C and STM32F358xC devices
532    #[inline(always)]
533    pub fn not_remapped(self) -> &'a mut crate::W<REG> {
534        self.variant(TIM7_DAC1_CH2_DMA_RMP::NotRemapped)
535    }
536    ///TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4
537    #[inline(always)]
538    pub fn remapped(self) -> &'a mut crate::W<REG> {
539        self.variant(TIM7_DAC1_CH2_DMA_RMP::Remapped)
540    }
541}
542/**DAC2 channel1 DMA remap
543
544Value on reset: 0*/
545#[cfg_attr(feature = "defmt", derive(defmt::Format))]
546#[derive(Clone, Copy, Debug, PartialEq, Eq)]
547pub enum DAC2_CH1_DMA_RMP {
548    ///0: Not remapped
549    NotRemapped = 0,
550    ///1: DAC2_CH1 DMA requests mapped on DMA1 channel 5
551    Remapped = 1,
552}
553impl From<DAC2_CH1_DMA_RMP> for bool {
554    #[inline(always)]
555    fn from(variant: DAC2_CH1_DMA_RMP) -> Self {
556        variant as u8 != 0
557    }
558}
559///Field `DAC2_CH1_DMA_RMP` reader - DAC2 channel1 DMA remap
560pub type DAC2_CH1_DMA_RMP_R = crate::BitReader<DAC2_CH1_DMA_RMP>;
561impl DAC2_CH1_DMA_RMP_R {
562    ///Get enumerated values variant
563    #[inline(always)]
564    pub const fn variant(&self) -> DAC2_CH1_DMA_RMP {
565        match self.bits {
566            false => DAC2_CH1_DMA_RMP::NotRemapped,
567            true => DAC2_CH1_DMA_RMP::Remapped,
568        }
569    }
570    ///Not remapped
571    #[inline(always)]
572    pub fn is_not_remapped(&self) -> bool {
573        *self == DAC2_CH1_DMA_RMP::NotRemapped
574    }
575    ///DAC2_CH1 DMA requests mapped on DMA1 channel 5
576    #[inline(always)]
577    pub fn is_remapped(&self) -> bool {
578        *self == DAC2_CH1_DMA_RMP::Remapped
579    }
580}
581///Field `DAC2_CH1_DMA_RMP` writer - DAC2 channel1 DMA remap
582pub type DAC2_CH1_DMA_RMP_W<'a, REG> = crate::BitWriter<'a, REG, DAC2_CH1_DMA_RMP>;
583impl<'a, REG> DAC2_CH1_DMA_RMP_W<'a, REG>
584where
585    REG: crate::Writable + crate::RegisterSpec,
586{
587    ///Not remapped
588    #[inline(always)]
589    pub fn not_remapped(self) -> &'a mut crate::W<REG> {
590        self.variant(DAC2_CH1_DMA_RMP::NotRemapped)
591    }
592    ///DAC2_CH1 DMA requests mapped on DMA1 channel 5
593    #[inline(always)]
594    pub fn remapped(self) -> &'a mut crate::W<REG> {
595        self.variant(DAC2_CH1_DMA_RMP::Remapped)
596    }
597}
598/**Fast Mode Plus (FM+) driving capability activation bits.
599
600Value on reset: 0*/
601#[cfg_attr(feature = "defmt", derive(defmt::Format))]
602#[derive(Clone, Copy, Debug, PartialEq, Eq)]
603pub enum I2C_PB6_FMP {
604    ///0: PB6 pin operate in standard mode
605    Standard = 0,
606    ///1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed
607    Fmp = 1,
608}
609impl From<I2C_PB6_FMP> for bool {
610    #[inline(always)]
611    fn from(variant: I2C_PB6_FMP) -> Self {
612        variant as u8 != 0
613    }
614}
615///Field `I2C_PB6_FMP` reader - Fast Mode Plus (FM+) driving capability activation bits.
616pub type I2C_PB6_FMP_R = crate::BitReader<I2C_PB6_FMP>;
617impl I2C_PB6_FMP_R {
618    ///Get enumerated values variant
619    #[inline(always)]
620    pub const fn variant(&self) -> I2C_PB6_FMP {
621        match self.bits {
622            false => I2C_PB6_FMP::Standard,
623            true => I2C_PB6_FMP::Fmp,
624        }
625    }
626    ///PB6 pin operate in standard mode
627    #[inline(always)]
628    pub fn is_standard(&self) -> bool {
629        *self == I2C_PB6_FMP::Standard
630    }
631    ///I2C FM+ mode enabled on PB6 and the Speed control is bypassed
632    #[inline(always)]
633    pub fn is_fmp(&self) -> bool {
634        *self == I2C_PB6_FMP::Fmp
635    }
636}
637///Field `I2C_PB6_FMP` writer - Fast Mode Plus (FM+) driving capability activation bits.
638pub type I2C_PB6_FMP_W<'a, REG> = crate::BitWriter<'a, REG, I2C_PB6_FMP>;
639impl<'a, REG> I2C_PB6_FMP_W<'a, REG>
640where
641    REG: crate::Writable + crate::RegisterSpec,
642{
643    ///PB6 pin operate in standard mode
644    #[inline(always)]
645    pub fn standard(self) -> &'a mut crate::W<REG> {
646        self.variant(I2C_PB6_FMP::Standard)
647    }
648    ///I2C FM+ mode enabled on PB6 and the Speed control is bypassed
649    #[inline(always)]
650    pub fn fmp(self) -> &'a mut crate::W<REG> {
651        self.variant(I2C_PB6_FMP::Fmp)
652    }
653}
654/**Fast Mode Plus (FM+) driving capability activation bits.
655
656Value on reset: 0*/
657#[cfg_attr(feature = "defmt", derive(defmt::Format))]
658#[derive(Clone, Copy, Debug, PartialEq, Eq)]
659pub enum I2C_PB7_FMP {
660    ///0: PB7 pin operate in standard mode
661    Standard = 0,
662    ///1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed
663    Fmp = 1,
664}
665impl From<I2C_PB7_FMP> for bool {
666    #[inline(always)]
667    fn from(variant: I2C_PB7_FMP) -> Self {
668        variant as u8 != 0
669    }
670}
671///Field `I2C_PB7_FMP` reader - Fast Mode Plus (FM+) driving capability activation bits.
672pub type I2C_PB7_FMP_R = crate::BitReader<I2C_PB7_FMP>;
673impl I2C_PB7_FMP_R {
674    ///Get enumerated values variant
675    #[inline(always)]
676    pub const fn variant(&self) -> I2C_PB7_FMP {
677        match self.bits {
678            false => I2C_PB7_FMP::Standard,
679            true => I2C_PB7_FMP::Fmp,
680        }
681    }
682    ///PB7 pin operate in standard mode
683    #[inline(always)]
684    pub fn is_standard(&self) -> bool {
685        *self == I2C_PB7_FMP::Standard
686    }
687    ///I2C FM+ mode enabled on PB7 and the Speed control is bypassed
688    #[inline(always)]
689    pub fn is_fmp(&self) -> bool {
690        *self == I2C_PB7_FMP::Fmp
691    }
692}
693///Field `I2C_PB7_FMP` writer - Fast Mode Plus (FM+) driving capability activation bits.
694pub type I2C_PB7_FMP_W<'a, REG> = crate::BitWriter<'a, REG, I2C_PB7_FMP>;
695impl<'a, REG> I2C_PB7_FMP_W<'a, REG>
696where
697    REG: crate::Writable + crate::RegisterSpec,
698{
699    ///PB7 pin operate in standard mode
700    #[inline(always)]
701    pub fn standard(self) -> &'a mut crate::W<REG> {
702        self.variant(I2C_PB7_FMP::Standard)
703    }
704    ///I2C FM+ mode enabled on PB7 and the Speed control is bypassed
705    #[inline(always)]
706    pub fn fmp(self) -> &'a mut crate::W<REG> {
707        self.variant(I2C_PB7_FMP::Fmp)
708    }
709}
710/**Fast Mode Plus (FM+) driving capability activation bits.
711
712Value on reset: 0*/
713#[cfg_attr(feature = "defmt", derive(defmt::Format))]
714#[derive(Clone, Copy, Debug, PartialEq, Eq)]
715pub enum I2C_PB8_FMP {
716    ///0: PB8 pin operate in standard mode
717    Standard = 0,
718    ///1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed
719    Fmp = 1,
720}
721impl From<I2C_PB8_FMP> for bool {
722    #[inline(always)]
723    fn from(variant: I2C_PB8_FMP) -> Self {
724        variant as u8 != 0
725    }
726}
727///Field `I2C_PB8_FMP` reader - Fast Mode Plus (FM+) driving capability activation bits.
728pub type I2C_PB8_FMP_R = crate::BitReader<I2C_PB8_FMP>;
729impl I2C_PB8_FMP_R {
730    ///Get enumerated values variant
731    #[inline(always)]
732    pub const fn variant(&self) -> I2C_PB8_FMP {
733        match self.bits {
734            false => I2C_PB8_FMP::Standard,
735            true => I2C_PB8_FMP::Fmp,
736        }
737    }
738    ///PB8 pin operate in standard mode
739    #[inline(always)]
740    pub fn is_standard(&self) -> bool {
741        *self == I2C_PB8_FMP::Standard
742    }
743    ///I2C FM+ mode enabled on PB8 and the Speed control is bypassed
744    #[inline(always)]
745    pub fn is_fmp(&self) -> bool {
746        *self == I2C_PB8_FMP::Fmp
747    }
748}
749///Field `I2C_PB8_FMP` writer - Fast Mode Plus (FM+) driving capability activation bits.
750pub type I2C_PB8_FMP_W<'a, REG> = crate::BitWriter<'a, REG, I2C_PB8_FMP>;
751impl<'a, REG> I2C_PB8_FMP_W<'a, REG>
752where
753    REG: crate::Writable + crate::RegisterSpec,
754{
755    ///PB8 pin operate in standard mode
756    #[inline(always)]
757    pub fn standard(self) -> &'a mut crate::W<REG> {
758        self.variant(I2C_PB8_FMP::Standard)
759    }
760    ///I2C FM+ mode enabled on PB8 and the Speed control is bypassed
761    #[inline(always)]
762    pub fn fmp(self) -> &'a mut crate::W<REG> {
763        self.variant(I2C_PB8_FMP::Fmp)
764    }
765}
766/**Fast Mode Plus (FM+) driving capability activation bits.
767
768Value on reset: 0*/
769#[cfg_attr(feature = "defmt", derive(defmt::Format))]
770#[derive(Clone, Copy, Debug, PartialEq, Eq)]
771pub enum I2C_PB9_FMP {
772    ///0: PB9 pin operate in standard mode
773    Standard = 0,
774    ///1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed
775    Fmp = 1,
776}
777impl From<I2C_PB9_FMP> for bool {
778    #[inline(always)]
779    fn from(variant: I2C_PB9_FMP) -> Self {
780        variant as u8 != 0
781    }
782}
783///Field `I2C_PB9_FMP` reader - Fast Mode Plus (FM+) driving capability activation bits.
784pub type I2C_PB9_FMP_R = crate::BitReader<I2C_PB9_FMP>;
785impl I2C_PB9_FMP_R {
786    ///Get enumerated values variant
787    #[inline(always)]
788    pub const fn variant(&self) -> I2C_PB9_FMP {
789        match self.bits {
790            false => I2C_PB9_FMP::Standard,
791            true => I2C_PB9_FMP::Fmp,
792        }
793    }
794    ///PB9 pin operate in standard mode
795    #[inline(always)]
796    pub fn is_standard(&self) -> bool {
797        *self == I2C_PB9_FMP::Standard
798    }
799    ///I2C FM+ mode enabled on PB9 and the Speed control is bypassed
800    #[inline(always)]
801    pub fn is_fmp(&self) -> bool {
802        *self == I2C_PB9_FMP::Fmp
803    }
804}
805///Field `I2C_PB9_FMP` writer - Fast Mode Plus (FM+) driving capability activation bits.
806pub type I2C_PB9_FMP_W<'a, REG> = crate::BitWriter<'a, REG, I2C_PB9_FMP>;
807impl<'a, REG> I2C_PB9_FMP_W<'a, REG>
808where
809    REG: crate::Writable + crate::RegisterSpec,
810{
811    ///PB9 pin operate in standard mode
812    #[inline(always)]
813    pub fn standard(self) -> &'a mut crate::W<REG> {
814        self.variant(I2C_PB9_FMP::Standard)
815    }
816    ///I2C FM+ mode enabled on PB9 and the Speed control is bypassed
817    #[inline(always)]
818    pub fn fmp(self) -> &'a mut crate::W<REG> {
819        self.variant(I2C_PB9_FMP::Fmp)
820    }
821}
822/**I2C1 Fast Mode Plus
823
824Value on reset: 0*/
825#[cfg_attr(feature = "defmt", derive(defmt::Format))]
826#[derive(Clone, Copy, Debug, PartialEq, Eq)]
827pub enum I2C1_FMP {
828    ///0: FM+ mode is controlled by I2C_Pxx_FMP bits only
829    Standard = 0,
830    ///1: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits
831    Fmp = 1,
832}
833impl From<I2C1_FMP> for bool {
834    #[inline(always)]
835    fn from(variant: I2C1_FMP) -> Self {
836        variant as u8 != 0
837    }
838}
839///Field `I2C1_FMP` reader - I2C1 Fast Mode Plus
840pub type I2C1_FMP_R = crate::BitReader<I2C1_FMP>;
841impl I2C1_FMP_R {
842    ///Get enumerated values variant
843    #[inline(always)]
844    pub const fn variant(&self) -> I2C1_FMP {
845        match self.bits {
846            false => I2C1_FMP::Standard,
847            true => I2C1_FMP::Fmp,
848        }
849    }
850    ///FM+ mode is controlled by I2C_Pxx_FMP bits only
851    #[inline(always)]
852    pub fn is_standard(&self) -> bool {
853        *self == I2C1_FMP::Standard
854    }
855    ///FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits
856    #[inline(always)]
857    pub fn is_fmp(&self) -> bool {
858        *self == I2C1_FMP::Fmp
859    }
860}
861///Field `I2C1_FMP` writer - I2C1 Fast Mode Plus
862pub type I2C1_FMP_W<'a, REG> = crate::BitWriter<'a, REG, I2C1_FMP>;
863impl<'a, REG> I2C1_FMP_W<'a, REG>
864where
865    REG: crate::Writable + crate::RegisterSpec,
866{
867    ///FM+ mode is controlled by I2C_Pxx_FMP bits only
868    #[inline(always)]
869    pub fn standard(self) -> &'a mut crate::W<REG> {
870        self.variant(I2C1_FMP::Standard)
871    }
872    ///FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits
873    #[inline(always)]
874    pub fn fmp(self) -> &'a mut crate::W<REG> {
875        self.variant(I2C1_FMP::Fmp)
876    }
877}
878/**I2C2 Fast Mode Plus
879
880Value on reset: 0*/
881#[cfg_attr(feature = "defmt", derive(defmt::Format))]
882#[derive(Clone, Copy, Debug, PartialEq, Eq)]
883pub enum I2C2_FMP {
884    ///0: FM+ mode is controlled by I2C_Pxx_FMP bits only
885    Standard = 0,
886    ///1: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits
887    Fmp = 1,
888}
889impl From<I2C2_FMP> for bool {
890    #[inline(always)]
891    fn from(variant: I2C2_FMP) -> Self {
892        variant as u8 != 0
893    }
894}
895///Field `I2C2_FMP` reader - I2C2 Fast Mode Plus
896pub type I2C2_FMP_R = crate::BitReader<I2C2_FMP>;
897impl I2C2_FMP_R {
898    ///Get enumerated values variant
899    #[inline(always)]
900    pub const fn variant(&self) -> I2C2_FMP {
901        match self.bits {
902            false => I2C2_FMP::Standard,
903            true => I2C2_FMP::Fmp,
904        }
905    }
906    ///FM+ mode is controlled by I2C_Pxx_FMP bits only
907    #[inline(always)]
908    pub fn is_standard(&self) -> bool {
909        *self == I2C2_FMP::Standard
910    }
911    ///FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits
912    #[inline(always)]
913    pub fn is_fmp(&self) -> bool {
914        *self == I2C2_FMP::Fmp
915    }
916}
917///Field `I2C2_FMP` writer - I2C2 Fast Mode Plus
918pub type I2C2_FMP_W<'a, REG> = crate::BitWriter<'a, REG, I2C2_FMP>;
919impl<'a, REG> I2C2_FMP_W<'a, REG>
920where
921    REG: crate::Writable + crate::RegisterSpec,
922{
923    ///FM+ mode is controlled by I2C_Pxx_FMP bits only
924    #[inline(always)]
925    pub fn standard(self) -> &'a mut crate::W<REG> {
926        self.variant(I2C2_FMP::Standard)
927    }
928    ///FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits
929    #[inline(always)]
930    pub fn fmp(self) -> &'a mut crate::W<REG> {
931        self.variant(I2C2_FMP::Fmp)
932    }
933}
934/**Encoder mode
935
936Value on reset: 0*/
937#[cfg_attr(feature = "defmt", derive(defmt::Format))]
938#[derive(Clone, Copy, Debug, PartialEq, Eq)]
939#[repr(u8)]
940pub enum ENCODER_MODE {
941    ///0: No redirection
942    NoRedirection = 0,
943    ///1: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
944    MapTim2tim15 = 1,
945    ///2: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
946    MapTim3tim15 = 2,
947    ///3: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively (STM32F303xB/C and STM32F358xC devices only)
948    MapTim4tim15 = 3,
949}
950impl From<ENCODER_MODE> for u8 {
951    #[inline(always)]
952    fn from(variant: ENCODER_MODE) -> Self {
953        variant as _
954    }
955}
956impl crate::FieldSpec for ENCODER_MODE {
957    type Ux = u8;
958}
959impl crate::IsEnum for ENCODER_MODE {}
960///Field `ENCODER_MODE` reader - Encoder mode
961pub type ENCODER_MODE_R = crate::FieldReader<ENCODER_MODE>;
962impl ENCODER_MODE_R {
963    ///Get enumerated values variant
964    #[inline(always)]
965    pub const fn variant(&self) -> ENCODER_MODE {
966        match self.bits {
967            0 => ENCODER_MODE::NoRedirection,
968            1 => ENCODER_MODE::MapTim2tim15,
969            2 => ENCODER_MODE::MapTim3tim15,
970            3 => ENCODER_MODE::MapTim4tim15,
971            _ => unreachable!(),
972        }
973    }
974    ///No redirection
975    #[inline(always)]
976    pub fn is_no_redirection(&self) -> bool {
977        *self == ENCODER_MODE::NoRedirection
978    }
979    ///TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
980    #[inline(always)]
981    pub fn is_map_tim2tim15(&self) -> bool {
982        *self == ENCODER_MODE::MapTim2tim15
983    }
984    ///TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
985    #[inline(always)]
986    pub fn is_map_tim3tim15(&self) -> bool {
987        *self == ENCODER_MODE::MapTim3tim15
988    }
989    ///TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively (STM32F303xB/C and STM32F358xC devices only)
990    #[inline(always)]
991    pub fn is_map_tim4tim15(&self) -> bool {
992        *self == ENCODER_MODE::MapTim4tim15
993    }
994}
995///Field `ENCODER_MODE` writer - Encoder mode
996pub type ENCODER_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ENCODER_MODE, crate::Safe>;
997impl<'a, REG> ENCODER_MODE_W<'a, REG>
998where
999    REG: crate::Writable + crate::RegisterSpec,
1000    REG::Ux: From<u8>,
1001{
1002    ///No redirection
1003    #[inline(always)]
1004    pub fn no_redirection(self) -> &'a mut crate::W<REG> {
1005        self.variant(ENCODER_MODE::NoRedirection)
1006    }
1007    ///TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
1008    #[inline(always)]
1009    pub fn map_tim2tim15(self) -> &'a mut crate::W<REG> {
1010        self.variant(ENCODER_MODE::MapTim2tim15)
1011    }
1012    ///TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
1013    #[inline(always)]
1014    pub fn map_tim3tim15(self) -> &'a mut crate::W<REG> {
1015        self.variant(ENCODER_MODE::MapTim3tim15)
1016    }
1017    ///TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively (STM32F303xB/C and STM32F358xC devices only)
1018    #[inline(always)]
1019    pub fn map_tim4tim15(self) -> &'a mut crate::W<REG> {
1020        self.variant(ENCODER_MODE::MapTim4tim15)
1021    }
1022}
1023/**I2C3 Fast Mode Plus
1024
1025Value on reset: 0*/
1026#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1027#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1028pub enum I2C3_FMP {
1029    ///0: FM+ mode is controlled by I2C_Pxx_FMP bits only
1030    Standard = 0,
1031    ///1: FM+ mode is enabled on all I2C3 pins selected through selection through IOPORT control registers AF selection bits
1032    Fmp = 1,
1033}
1034impl From<I2C3_FMP> for bool {
1035    #[inline(always)]
1036    fn from(variant: I2C3_FMP) -> Self {
1037        variant as u8 != 0
1038    }
1039}
1040///Field `I2C3_FMP` reader - I2C3 Fast Mode Plus
1041pub type I2C3_FMP_R = crate::BitReader<I2C3_FMP>;
1042impl I2C3_FMP_R {
1043    ///Get enumerated values variant
1044    #[inline(always)]
1045    pub const fn variant(&self) -> I2C3_FMP {
1046        match self.bits {
1047            false => I2C3_FMP::Standard,
1048            true => I2C3_FMP::Fmp,
1049        }
1050    }
1051    ///FM+ mode is controlled by I2C_Pxx_FMP bits only
1052    #[inline(always)]
1053    pub fn is_standard(&self) -> bool {
1054        *self == I2C3_FMP::Standard
1055    }
1056    ///FM+ mode is enabled on all I2C3 pins selected through selection through IOPORT control registers AF selection bits
1057    #[inline(always)]
1058    pub fn is_fmp(&self) -> bool {
1059        *self == I2C3_FMP::Fmp
1060    }
1061}
1062///Field `I2C3_FMP` writer - I2C3 Fast Mode Plus
1063pub type I2C3_FMP_W<'a, REG> = crate::BitWriter<'a, REG, I2C3_FMP>;
1064impl<'a, REG> I2C3_FMP_W<'a, REG>
1065where
1066    REG: crate::Writable + crate::RegisterSpec,
1067{
1068    ///FM+ mode is controlled by I2C_Pxx_FMP bits only
1069    #[inline(always)]
1070    pub fn standard(self) -> &'a mut crate::W<REG> {
1071        self.variant(I2C3_FMP::Standard)
1072    }
1073    ///FM+ mode is enabled on all I2C3 pins selected through selection through IOPORT control registers AF selection bits
1074    #[inline(always)]
1075    pub fn fmp(self) -> &'a mut crate::W<REG> {
1076        self.variant(I2C3_FMP::Fmp)
1077    }
1078}
1079/**Invalid operation interrupt enable
1080
1081Value on reset: 0*/
1082#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1083#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1084pub enum FPU_IE0 {
1085    ///0: Invalid operation interrupt disable
1086    Disabled = 0,
1087    ///1: Invalid operation interrupt enable
1088    Enabled = 1,
1089}
1090impl From<FPU_IE0> for bool {
1091    #[inline(always)]
1092    fn from(variant: FPU_IE0) -> Self {
1093        variant as u8 != 0
1094    }
1095}
1096///Field `FPU_IE0` reader - Invalid operation interrupt enable
1097pub type FPU_IE0_R = crate::BitReader<FPU_IE0>;
1098impl FPU_IE0_R {
1099    ///Get enumerated values variant
1100    #[inline(always)]
1101    pub const fn variant(&self) -> FPU_IE0 {
1102        match self.bits {
1103            false => FPU_IE0::Disabled,
1104            true => FPU_IE0::Enabled,
1105        }
1106    }
1107    ///Invalid operation interrupt disable
1108    #[inline(always)]
1109    pub fn is_disabled(&self) -> bool {
1110        *self == FPU_IE0::Disabled
1111    }
1112    ///Invalid operation interrupt enable
1113    #[inline(always)]
1114    pub fn is_enabled(&self) -> bool {
1115        *self == FPU_IE0::Enabled
1116    }
1117}
1118///Field `FPU_IE0` writer - Invalid operation interrupt enable
1119pub type FPU_IE0_W<'a, REG> = crate::BitWriter<'a, REG, FPU_IE0>;
1120impl<'a, REG> FPU_IE0_W<'a, REG>
1121where
1122    REG: crate::Writable + crate::RegisterSpec,
1123{
1124    ///Invalid operation interrupt disable
1125    #[inline(always)]
1126    pub fn disabled(self) -> &'a mut crate::W<REG> {
1127        self.variant(FPU_IE0::Disabled)
1128    }
1129    ///Invalid operation interrupt enable
1130    #[inline(always)]
1131    pub fn enabled(self) -> &'a mut crate::W<REG> {
1132        self.variant(FPU_IE0::Enabled)
1133    }
1134}
1135/**Devide-by-zero interrupt enable
1136
1137Value on reset: 0*/
1138#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1139#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1140pub enum FPU_IE1 {
1141    ///0: Devide-by-zero interrupt disable
1142    Disabled = 0,
1143    ///1: Devide-by-zero interrupt enable
1144    Enabled = 1,
1145}
1146impl From<FPU_IE1> for bool {
1147    #[inline(always)]
1148    fn from(variant: FPU_IE1) -> Self {
1149        variant as u8 != 0
1150    }
1151}
1152///Field `FPU_IE1` reader - Devide-by-zero interrupt enable
1153pub type FPU_IE1_R = crate::BitReader<FPU_IE1>;
1154impl FPU_IE1_R {
1155    ///Get enumerated values variant
1156    #[inline(always)]
1157    pub const fn variant(&self) -> FPU_IE1 {
1158        match self.bits {
1159            false => FPU_IE1::Disabled,
1160            true => FPU_IE1::Enabled,
1161        }
1162    }
1163    ///Devide-by-zero interrupt disable
1164    #[inline(always)]
1165    pub fn is_disabled(&self) -> bool {
1166        *self == FPU_IE1::Disabled
1167    }
1168    ///Devide-by-zero interrupt enable
1169    #[inline(always)]
1170    pub fn is_enabled(&self) -> bool {
1171        *self == FPU_IE1::Enabled
1172    }
1173}
1174///Field `FPU_IE1` writer - Devide-by-zero interrupt enable
1175pub type FPU_IE1_W<'a, REG> = crate::BitWriter<'a, REG, FPU_IE1>;
1176impl<'a, REG> FPU_IE1_W<'a, REG>
1177where
1178    REG: crate::Writable + crate::RegisterSpec,
1179{
1180    ///Devide-by-zero interrupt disable
1181    #[inline(always)]
1182    pub fn disabled(self) -> &'a mut crate::W<REG> {
1183        self.variant(FPU_IE1::Disabled)
1184    }
1185    ///Devide-by-zero interrupt enable
1186    #[inline(always)]
1187    pub fn enabled(self) -> &'a mut crate::W<REG> {
1188        self.variant(FPU_IE1::Enabled)
1189    }
1190}
1191/**Underflow interrupt enable
1192
1193Value on reset: 0*/
1194#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1195#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1196pub enum FPU_IE2 {
1197    ///0: Underflow interrupt disable
1198    Disabled = 0,
1199    ///1: Underflow interrupt enable
1200    Enabled = 1,
1201}
1202impl From<FPU_IE2> for bool {
1203    #[inline(always)]
1204    fn from(variant: FPU_IE2) -> Self {
1205        variant as u8 != 0
1206    }
1207}
1208///Field `FPU_IE2` reader - Underflow interrupt enable
1209pub type FPU_IE2_R = crate::BitReader<FPU_IE2>;
1210impl FPU_IE2_R {
1211    ///Get enumerated values variant
1212    #[inline(always)]
1213    pub const fn variant(&self) -> FPU_IE2 {
1214        match self.bits {
1215            false => FPU_IE2::Disabled,
1216            true => FPU_IE2::Enabled,
1217        }
1218    }
1219    ///Underflow interrupt disable
1220    #[inline(always)]
1221    pub fn is_disabled(&self) -> bool {
1222        *self == FPU_IE2::Disabled
1223    }
1224    ///Underflow interrupt enable
1225    #[inline(always)]
1226    pub fn is_enabled(&self) -> bool {
1227        *self == FPU_IE2::Enabled
1228    }
1229}
1230///Field `FPU_IE2` writer - Underflow interrupt enable
1231pub type FPU_IE2_W<'a, REG> = crate::BitWriter<'a, REG, FPU_IE2>;
1232impl<'a, REG> FPU_IE2_W<'a, REG>
1233where
1234    REG: crate::Writable + crate::RegisterSpec,
1235{
1236    ///Underflow interrupt disable
1237    #[inline(always)]
1238    pub fn disabled(self) -> &'a mut crate::W<REG> {
1239        self.variant(FPU_IE2::Disabled)
1240    }
1241    ///Underflow interrupt enable
1242    #[inline(always)]
1243    pub fn enabled(self) -> &'a mut crate::W<REG> {
1244        self.variant(FPU_IE2::Enabled)
1245    }
1246}
1247/**Overflow interrupt enable
1248
1249Value on reset: 0*/
1250#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1251#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1252pub enum FPU_IE3 {
1253    ///0: Overflow interrupt disable
1254    Disabled = 0,
1255    ///1: Overflow interrupt enable
1256    Enabled = 1,
1257}
1258impl From<FPU_IE3> for bool {
1259    #[inline(always)]
1260    fn from(variant: FPU_IE3) -> Self {
1261        variant as u8 != 0
1262    }
1263}
1264///Field `FPU_IE3` reader - Overflow interrupt enable
1265pub type FPU_IE3_R = crate::BitReader<FPU_IE3>;
1266impl FPU_IE3_R {
1267    ///Get enumerated values variant
1268    #[inline(always)]
1269    pub const fn variant(&self) -> FPU_IE3 {
1270        match self.bits {
1271            false => FPU_IE3::Disabled,
1272            true => FPU_IE3::Enabled,
1273        }
1274    }
1275    ///Overflow interrupt disable
1276    #[inline(always)]
1277    pub fn is_disabled(&self) -> bool {
1278        *self == FPU_IE3::Disabled
1279    }
1280    ///Overflow interrupt enable
1281    #[inline(always)]
1282    pub fn is_enabled(&self) -> bool {
1283        *self == FPU_IE3::Enabled
1284    }
1285}
1286///Field `FPU_IE3` writer - Overflow interrupt enable
1287pub type FPU_IE3_W<'a, REG> = crate::BitWriter<'a, REG, FPU_IE3>;
1288impl<'a, REG> FPU_IE3_W<'a, REG>
1289where
1290    REG: crate::Writable + crate::RegisterSpec,
1291{
1292    ///Overflow interrupt disable
1293    #[inline(always)]
1294    pub fn disabled(self) -> &'a mut crate::W<REG> {
1295        self.variant(FPU_IE3::Disabled)
1296    }
1297    ///Overflow interrupt enable
1298    #[inline(always)]
1299    pub fn enabled(self) -> &'a mut crate::W<REG> {
1300        self.variant(FPU_IE3::Enabled)
1301    }
1302}
1303/**Input denormal interrupt enable
1304
1305Value on reset: 0*/
1306#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1307#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1308pub enum FPU_IE4 {
1309    ///0: Input denormal interrupt disable
1310    Disabled = 0,
1311    ///1: Input denormal interrupt enable
1312    Enabled = 1,
1313}
1314impl From<FPU_IE4> for bool {
1315    #[inline(always)]
1316    fn from(variant: FPU_IE4) -> Self {
1317        variant as u8 != 0
1318    }
1319}
1320///Field `FPU_IE4` reader - Input denormal interrupt enable
1321pub type FPU_IE4_R = crate::BitReader<FPU_IE4>;
1322impl FPU_IE4_R {
1323    ///Get enumerated values variant
1324    #[inline(always)]
1325    pub const fn variant(&self) -> FPU_IE4 {
1326        match self.bits {
1327            false => FPU_IE4::Disabled,
1328            true => FPU_IE4::Enabled,
1329        }
1330    }
1331    ///Input denormal interrupt disable
1332    #[inline(always)]
1333    pub fn is_disabled(&self) -> bool {
1334        *self == FPU_IE4::Disabled
1335    }
1336    ///Input denormal interrupt enable
1337    #[inline(always)]
1338    pub fn is_enabled(&self) -> bool {
1339        *self == FPU_IE4::Enabled
1340    }
1341}
1342///Field `FPU_IE4` writer - Input denormal interrupt enable
1343pub type FPU_IE4_W<'a, REG> = crate::BitWriter<'a, REG, FPU_IE4>;
1344impl<'a, REG> FPU_IE4_W<'a, REG>
1345where
1346    REG: crate::Writable + crate::RegisterSpec,
1347{
1348    ///Input denormal interrupt disable
1349    #[inline(always)]
1350    pub fn disabled(self) -> &'a mut crate::W<REG> {
1351        self.variant(FPU_IE4::Disabled)
1352    }
1353    ///Input denormal interrupt enable
1354    #[inline(always)]
1355    pub fn enabled(self) -> &'a mut crate::W<REG> {
1356        self.variant(FPU_IE4::Enabled)
1357    }
1358}
1359/**Inexact interrupt enable
1360
1361Value on reset: 0*/
1362#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1363#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1364pub enum FPU_IE5 {
1365    ///0: Inexact interrupt disable
1366    Disabled = 0,
1367    ///1: Inexact interrupt enable
1368    Enabled = 1,
1369}
1370impl From<FPU_IE5> for bool {
1371    #[inline(always)]
1372    fn from(variant: FPU_IE5) -> Self {
1373        variant as u8 != 0
1374    }
1375}
1376///Field `FPU_IE5` reader - Inexact interrupt enable
1377pub type FPU_IE5_R = crate::BitReader<FPU_IE5>;
1378impl FPU_IE5_R {
1379    ///Get enumerated values variant
1380    #[inline(always)]
1381    pub const fn variant(&self) -> FPU_IE5 {
1382        match self.bits {
1383            false => FPU_IE5::Disabled,
1384            true => FPU_IE5::Enabled,
1385        }
1386    }
1387    ///Inexact interrupt disable
1388    #[inline(always)]
1389    pub fn is_disabled(&self) -> bool {
1390        *self == FPU_IE5::Disabled
1391    }
1392    ///Inexact interrupt enable
1393    #[inline(always)]
1394    pub fn is_enabled(&self) -> bool {
1395        *self == FPU_IE5::Enabled
1396    }
1397}
1398///Field `FPU_IE5` writer - Inexact interrupt enable
1399pub type FPU_IE5_W<'a, REG> = crate::BitWriter<'a, REG, FPU_IE5>;
1400impl<'a, REG> FPU_IE5_W<'a, REG>
1401where
1402    REG: crate::Writable + crate::RegisterSpec,
1403{
1404    ///Inexact interrupt disable
1405    #[inline(always)]
1406    pub fn disabled(self) -> &'a mut crate::W<REG> {
1407        self.variant(FPU_IE5::Disabled)
1408    }
1409    ///Inexact interrupt enable
1410    #[inline(always)]
1411    pub fn enabled(self) -> &'a mut crate::W<REG> {
1412        self.variant(FPU_IE5::Enabled)
1413    }
1414}
1415impl R {
1416    ///Bits 0:2 - Memory mapping selection bits
1417    #[inline(always)]
1418    pub fn mem_mode(&self) -> MEM_MODE_R {
1419        MEM_MODE_R::new((self.bits & 7) as u8)
1420    }
1421    ///Bit 5 - USB interrupt remap
1422    #[inline(always)]
1423    pub fn usb_it_rmp(&self) -> USB_IT_RMP_R {
1424        USB_IT_RMP_R::new(((self.bits >> 5) & 1) != 0)
1425    }
1426    ///Bit 6 - Timer 1 ITR3 selection
1427    #[inline(always)]
1428    pub fn tim1_itr3_rmp(&self) -> TIM1_ITR3_RMP_R {
1429        TIM1_ITR3_RMP_R::new(((self.bits >> 6) & 1) != 0)
1430    }
1431    ///Bit 7 - DAC trigger remap (when TSEL = 001)
1432    #[inline(always)]
1433    pub fn dac1_trig_rmp(&self) -> DAC1_TRIG_RMP_R {
1434        DAC1_TRIG_RMP_R::new(((self.bits >> 7) & 1) != 0)
1435    }
1436    ///Bit 8 - ADC24 DMA remapping bit
1437    #[inline(always)]
1438    pub fn adc2_dma_rmp(&self) -> ADC2_DMA_RMP_R {
1439        ADC2_DMA_RMP_R::new(((self.bits >> 8) & 1) != 0)
1440    }
1441    ///Bit 11 - TIM16 DMA request remapping bit
1442    #[inline(always)]
1443    pub fn tim16_dma_rmp(&self) -> TIM16_DMA_RMP_R {
1444        TIM16_DMA_RMP_R::new(((self.bits >> 11) & 1) != 0)
1445    }
1446    ///Bit 12 - TIM17 DMA request remapping bit
1447    #[inline(always)]
1448    pub fn tim17_dma_rmp(&self) -> TIM17_DMA_RMP_R {
1449        TIM17_DMA_RMP_R::new(((self.bits >> 12) & 1) != 0)
1450    }
1451    ///Bit 13 - TIM6 and DAC1 DMA request remapping bit
1452    #[inline(always)]
1453    pub fn tim6_dac1_ch1_dma_rmp(&self) -> TIM6_DAC1_CH1_DMA_RMP_R {
1454        TIM6_DAC1_CH1_DMA_RMP_R::new(((self.bits >> 13) & 1) != 0)
1455    }
1456    ///Bit 14 - TIM7 and DAC2 DMA request remapping bit
1457    #[inline(always)]
1458    pub fn tim7_dac1_ch2_dma_rmp(&self) -> TIM7_DAC1_CH2_DMA_RMP_R {
1459        TIM7_DAC1_CH2_DMA_RMP_R::new(((self.bits >> 14) & 1) != 0)
1460    }
1461    ///Bit 15 - DAC2 channel1 DMA remap
1462    #[inline(always)]
1463    pub fn dac2_ch1_dma_rmp(&self) -> DAC2_CH1_DMA_RMP_R {
1464        DAC2_CH1_DMA_RMP_R::new(((self.bits >> 15) & 1) != 0)
1465    }
1466    ///Bit 16 - Fast Mode Plus (FM+) driving capability activation bits.
1467    #[inline(always)]
1468    pub fn i2c_pb6_fmp(&self) -> I2C_PB6_FMP_R {
1469        I2C_PB6_FMP_R::new(((self.bits >> 16) & 1) != 0)
1470    }
1471    ///Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.
1472    #[inline(always)]
1473    pub fn i2c_pb7_fmp(&self) -> I2C_PB7_FMP_R {
1474        I2C_PB7_FMP_R::new(((self.bits >> 17) & 1) != 0)
1475    }
1476    ///Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.
1477    #[inline(always)]
1478    pub fn i2c_pb8_fmp(&self) -> I2C_PB8_FMP_R {
1479        I2C_PB8_FMP_R::new(((self.bits >> 18) & 1) != 0)
1480    }
1481    ///Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.
1482    #[inline(always)]
1483    pub fn i2c_pb9_fmp(&self) -> I2C_PB9_FMP_R {
1484        I2C_PB9_FMP_R::new(((self.bits >> 19) & 1) != 0)
1485    }
1486    ///Bit 20 - I2C1 Fast Mode Plus
1487    #[inline(always)]
1488    pub fn i2c1_fmp(&self) -> I2C1_FMP_R {
1489        I2C1_FMP_R::new(((self.bits >> 20) & 1) != 0)
1490    }
1491    ///Bit 21 - I2C2 Fast Mode Plus
1492    #[inline(always)]
1493    pub fn i2c2_fmp(&self) -> I2C2_FMP_R {
1494        I2C2_FMP_R::new(((self.bits >> 21) & 1) != 0)
1495    }
1496    ///Bits 22:23 - Encoder mode
1497    #[inline(always)]
1498    pub fn encoder_mode(&self) -> ENCODER_MODE_R {
1499        ENCODER_MODE_R::new(((self.bits >> 22) & 3) as u8)
1500    }
1501    ///Bit 24 - I2C3 Fast Mode Plus
1502    #[inline(always)]
1503    pub fn i2c3_fmp(&self) -> I2C3_FMP_R {
1504        I2C3_FMP_R::new(((self.bits >> 24) & 1) != 0)
1505    }
1506    ///Bit 26 - Invalid operation interrupt enable
1507    #[inline(always)]
1508    pub fn fpu_ie0(&self) -> FPU_IE0_R {
1509        FPU_IE0_R::new(((self.bits >> 26) & 1) != 0)
1510    }
1511    ///Bit 27 - Devide-by-zero interrupt enable
1512    #[inline(always)]
1513    pub fn fpu_ie1(&self) -> FPU_IE1_R {
1514        FPU_IE1_R::new(((self.bits >> 27) & 1) != 0)
1515    }
1516    ///Bit 28 - Underflow interrupt enable
1517    #[inline(always)]
1518    pub fn fpu_ie2(&self) -> FPU_IE2_R {
1519        FPU_IE2_R::new(((self.bits >> 28) & 1) != 0)
1520    }
1521    ///Bit 29 - Overflow interrupt enable
1522    #[inline(always)]
1523    pub fn fpu_ie3(&self) -> FPU_IE3_R {
1524        FPU_IE3_R::new(((self.bits >> 29) & 1) != 0)
1525    }
1526    ///Bit 30 - Input denormal interrupt enable
1527    #[inline(always)]
1528    pub fn fpu_ie4(&self) -> FPU_IE4_R {
1529        FPU_IE4_R::new(((self.bits >> 30) & 1) != 0)
1530    }
1531    ///Bit 31 - Inexact interrupt enable
1532    #[inline(always)]
1533    pub fn fpu_ie5(&self) -> FPU_IE5_R {
1534        FPU_IE5_R::new(((self.bits >> 31) & 1) != 0)
1535    }
1536}
1537impl core::fmt::Debug for R {
1538    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1539        f.debug_struct("CFGR1")
1540            .field("mem_mode", &self.mem_mode())
1541            .field("usb_it_rmp", &self.usb_it_rmp())
1542            .field("tim1_itr3_rmp", &self.tim1_itr3_rmp())
1543            .field("dac1_trig_rmp", &self.dac1_trig_rmp())
1544            .field("adc2_dma_rmp", &self.adc2_dma_rmp())
1545            .field("tim16_dma_rmp", &self.tim16_dma_rmp())
1546            .field("tim17_dma_rmp", &self.tim17_dma_rmp())
1547            .field("tim6_dac1_ch1_dma_rmp", &self.tim6_dac1_ch1_dma_rmp())
1548            .field("tim7_dac1_ch2_dma_rmp", &self.tim7_dac1_ch2_dma_rmp())
1549            .field("i2c_pb6_fmp", &self.i2c_pb6_fmp())
1550            .field("i2c_pb7_fmp", &self.i2c_pb7_fmp())
1551            .field("i2c_pb8_fmp", &self.i2c_pb8_fmp())
1552            .field("i2c_pb9_fmp", &self.i2c_pb9_fmp())
1553            .field("i2c1_fmp", &self.i2c1_fmp())
1554            .field("i2c2_fmp", &self.i2c2_fmp())
1555            .field("encoder_mode", &self.encoder_mode())
1556            .field("fpu_ie5", &self.fpu_ie5())
1557            .field("fpu_ie4", &self.fpu_ie4())
1558            .field("fpu_ie3", &self.fpu_ie3())
1559            .field("fpu_ie2", &self.fpu_ie2())
1560            .field("fpu_ie1", &self.fpu_ie1())
1561            .field("fpu_ie0", &self.fpu_ie0())
1562            .field("dac2_ch1_dma_rmp", &self.dac2_ch1_dma_rmp())
1563            .field("i2c3_fmp", &self.i2c3_fmp())
1564            .finish()
1565    }
1566}
1567impl W {
1568    ///Bits 0:2 - Memory mapping selection bits
1569    #[inline(always)]
1570    pub fn mem_mode(&mut self) -> MEM_MODE_W<CFGR1rs> {
1571        MEM_MODE_W::new(self, 0)
1572    }
1573    ///Bit 5 - USB interrupt remap
1574    #[inline(always)]
1575    pub fn usb_it_rmp(&mut self) -> USB_IT_RMP_W<CFGR1rs> {
1576        USB_IT_RMP_W::new(self, 5)
1577    }
1578    ///Bit 6 - Timer 1 ITR3 selection
1579    #[inline(always)]
1580    pub fn tim1_itr3_rmp(&mut self) -> TIM1_ITR3_RMP_W<CFGR1rs> {
1581        TIM1_ITR3_RMP_W::new(self, 6)
1582    }
1583    ///Bit 7 - DAC trigger remap (when TSEL = 001)
1584    #[inline(always)]
1585    pub fn dac1_trig_rmp(&mut self) -> DAC1_TRIG_RMP_W<CFGR1rs> {
1586        DAC1_TRIG_RMP_W::new(self, 7)
1587    }
1588    ///Bit 8 - ADC24 DMA remapping bit
1589    #[inline(always)]
1590    pub fn adc2_dma_rmp(&mut self) -> ADC2_DMA_RMP_W<CFGR1rs> {
1591        ADC2_DMA_RMP_W::new(self, 8)
1592    }
1593    ///Bit 11 - TIM16 DMA request remapping bit
1594    #[inline(always)]
1595    pub fn tim16_dma_rmp(&mut self) -> TIM16_DMA_RMP_W<CFGR1rs> {
1596        TIM16_DMA_RMP_W::new(self, 11)
1597    }
1598    ///Bit 12 - TIM17 DMA request remapping bit
1599    #[inline(always)]
1600    pub fn tim17_dma_rmp(&mut self) -> TIM17_DMA_RMP_W<CFGR1rs> {
1601        TIM17_DMA_RMP_W::new(self, 12)
1602    }
1603    ///Bit 13 - TIM6 and DAC1 DMA request remapping bit
1604    #[inline(always)]
1605    pub fn tim6_dac1_ch1_dma_rmp(&mut self) -> TIM6_DAC1_CH1_DMA_RMP_W<CFGR1rs> {
1606        TIM6_DAC1_CH1_DMA_RMP_W::new(self, 13)
1607    }
1608    ///Bit 14 - TIM7 and DAC2 DMA request remapping bit
1609    #[inline(always)]
1610    pub fn tim7_dac1_ch2_dma_rmp(&mut self) -> TIM7_DAC1_CH2_DMA_RMP_W<CFGR1rs> {
1611        TIM7_DAC1_CH2_DMA_RMP_W::new(self, 14)
1612    }
1613    ///Bit 15 - DAC2 channel1 DMA remap
1614    #[inline(always)]
1615    pub fn dac2_ch1_dma_rmp(&mut self) -> DAC2_CH1_DMA_RMP_W<CFGR1rs> {
1616        DAC2_CH1_DMA_RMP_W::new(self, 15)
1617    }
1618    ///Bit 16 - Fast Mode Plus (FM+) driving capability activation bits.
1619    #[inline(always)]
1620    pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<CFGR1rs> {
1621        I2C_PB6_FMP_W::new(self, 16)
1622    }
1623    ///Bit 17 - Fast Mode Plus (FM+) driving capability activation bits.
1624    #[inline(always)]
1625    pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<CFGR1rs> {
1626        I2C_PB7_FMP_W::new(self, 17)
1627    }
1628    ///Bit 18 - Fast Mode Plus (FM+) driving capability activation bits.
1629    #[inline(always)]
1630    pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<CFGR1rs> {
1631        I2C_PB8_FMP_W::new(self, 18)
1632    }
1633    ///Bit 19 - Fast Mode Plus (FM+) driving capability activation bits.
1634    #[inline(always)]
1635    pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<CFGR1rs> {
1636        I2C_PB9_FMP_W::new(self, 19)
1637    }
1638    ///Bit 20 - I2C1 Fast Mode Plus
1639    #[inline(always)]
1640    pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<CFGR1rs> {
1641        I2C1_FMP_W::new(self, 20)
1642    }
1643    ///Bit 21 - I2C2 Fast Mode Plus
1644    #[inline(always)]
1645    pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<CFGR1rs> {
1646        I2C2_FMP_W::new(self, 21)
1647    }
1648    ///Bits 22:23 - Encoder mode
1649    #[inline(always)]
1650    pub fn encoder_mode(&mut self) -> ENCODER_MODE_W<CFGR1rs> {
1651        ENCODER_MODE_W::new(self, 22)
1652    }
1653    ///Bit 24 - I2C3 Fast Mode Plus
1654    #[inline(always)]
1655    pub fn i2c3_fmp(&mut self) -> I2C3_FMP_W<CFGR1rs> {
1656        I2C3_FMP_W::new(self, 24)
1657    }
1658    ///Bit 26 - Invalid operation interrupt enable
1659    #[inline(always)]
1660    pub fn fpu_ie0(&mut self) -> FPU_IE0_W<CFGR1rs> {
1661        FPU_IE0_W::new(self, 26)
1662    }
1663    ///Bit 27 - Devide-by-zero interrupt enable
1664    #[inline(always)]
1665    pub fn fpu_ie1(&mut self) -> FPU_IE1_W<CFGR1rs> {
1666        FPU_IE1_W::new(self, 27)
1667    }
1668    ///Bit 28 - Underflow interrupt enable
1669    #[inline(always)]
1670    pub fn fpu_ie2(&mut self) -> FPU_IE2_W<CFGR1rs> {
1671        FPU_IE2_W::new(self, 28)
1672    }
1673    ///Bit 29 - Overflow interrupt enable
1674    #[inline(always)]
1675    pub fn fpu_ie3(&mut self) -> FPU_IE3_W<CFGR1rs> {
1676        FPU_IE3_W::new(self, 29)
1677    }
1678    ///Bit 30 - Input denormal interrupt enable
1679    #[inline(always)]
1680    pub fn fpu_ie4(&mut self) -> FPU_IE4_W<CFGR1rs> {
1681        FPU_IE4_W::new(self, 30)
1682    }
1683    ///Bit 31 - Inexact interrupt enable
1684    #[inline(always)]
1685    pub fn fpu_ie5(&mut self) -> FPU_IE5_W<CFGR1rs> {
1686        FPU_IE5_W::new(self, 31)
1687    }
1688}
1689/**configuration register 1
1690
1691You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1692
1693See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#SYSCFG:CFGR1)*/
1694pub struct CFGR1rs;
1695impl crate::RegisterSpec for CFGR1rs {
1696    type Ux = u32;
1697}
1698///`read()` method returns [`cfgr1::R`](R) reader structure
1699impl crate::Readable for CFGR1rs {}
1700///`write(|w| ..)` method takes [`cfgr1::W`](W) writer structure
1701impl crate::Writable for CFGR1rs {
1702    type Safety = crate::Unsafe;
1703}
1704///`reset()` method sets CFGR1 to value 0
1705impl crate::Resettable for CFGR1rs {}
stm32f3/stm32f303/syscfg/cfgr1.rs

stm32f3/stm32f303/syscfg/
cfgr1.rs
