stm32f3/stm32f303/rcc/
apb1rstr.rs

1///Register `APB1RSTR` reader
2pub type R = crate::R<APB1RSTRrs>;
3///Register `APB1RSTR` writer
4pub type W = crate::W<APB1RSTRrs>;
5/**Timer 2 reset
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum TIM2RST {
11    ///1: Reset the selected module
12    Reset = 1,
13}
14impl From<TIM2RST> for bool {
15    #[inline(always)]
16    fn from(variant: TIM2RST) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `TIM2RST` reader - Timer 2 reset
21pub type TIM2RST_R = crate::BitReader<TIM2RST>;
22impl TIM2RST_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> Option<TIM2RST> {
26        match self.bits {
27            true => Some(TIM2RST::Reset),
28            _ => None,
29        }
30    }
31    ///Reset the selected module
32    #[inline(always)]
33    pub fn is_reset(&self) -> bool {
34        *self == TIM2RST::Reset
35    }
36}
37///Field `TIM2RST` writer - Timer 2 reset
38pub type TIM2RST_W<'a, REG> = crate::BitWriter<'a, REG, TIM2RST>;
39impl<'a, REG> TIM2RST_W<'a, REG>
40where
41    REG: crate::Writable + crate::RegisterSpec,
42{
43    ///Reset the selected module
44    #[inline(always)]
45    pub fn reset(self) -> &'a mut crate::W<REG> {
46        self.variant(TIM2RST::Reset)
47    }
48}
49///Field `TIM3RST` reader - Timer 3 reset
50pub use TIM2RST_R as TIM3RST_R;
51///Field `TIM4RST` reader - Timer 14 reset
52pub use TIM2RST_R as TIM4RST_R;
53///Field `TIM6RST` reader - Timer 6 reset
54pub use TIM2RST_R as TIM6RST_R;
55///Field `TIM7RST` reader - Timer 7 reset
56pub use TIM2RST_R as TIM7RST_R;
57///Field `WWDGRST` reader - Window watchdog reset
58pub use TIM2RST_R as WWDGRST_R;
59///Field `SPI2RST` reader - SPI2 reset
60pub use TIM2RST_R as SPI2RST_R;
61///Field `SPI3RST` reader - SPI3 reset
62pub use TIM2RST_R as SPI3RST_R;
63///Field `USART2RST` reader - USART 2 reset
64pub use TIM2RST_R as USART2RST_R;
65///Field `USART3RST` reader - USART3 reset
66pub use TIM2RST_R as USART3RST_R;
67///Field `UART4RST` reader - UART 4 reset
68pub use TIM2RST_R as UART4RST_R;
69///Field `UART5RST` reader - UART 5 reset
70pub use TIM2RST_R as UART5RST_R;
71///Field `I2C1RST` reader - I2C1 reset
72pub use TIM2RST_R as I2C1RST_R;
73///Field `I2C2RST` reader - I2C2 reset
74pub use TIM2RST_R as I2C2RST_R;
75///Field `USBRST` reader - USB reset
76pub use TIM2RST_R as USBRST_R;
77///Field `CANRST` reader - CAN reset
78pub use TIM2RST_R as CANRST_R;
79///Field `DAC2RST` reader - DAC2 interface reset
80pub use TIM2RST_R as DAC2RST_R;
81///Field `PWRRST` reader - Power interface reset
82pub use TIM2RST_R as PWRRST_R;
83///Field `DAC1RST` reader - DAC interface reset
84pub use TIM2RST_R as DAC1RST_R;
85///Field `I2C3RST` reader - I2C3 reset
86pub use TIM2RST_R as I2C3RST_R;
87///Field `TIM3RST` writer - Timer 3 reset
88pub use TIM2RST_W as TIM3RST_W;
89///Field `TIM4RST` writer - Timer 14 reset
90pub use TIM2RST_W as TIM4RST_W;
91///Field `TIM6RST` writer - Timer 6 reset
92pub use TIM2RST_W as TIM6RST_W;
93///Field `TIM7RST` writer - Timer 7 reset
94pub use TIM2RST_W as TIM7RST_W;
95///Field `WWDGRST` writer - Window watchdog reset
96pub use TIM2RST_W as WWDGRST_W;
97///Field `SPI2RST` writer - SPI2 reset
98pub use TIM2RST_W as SPI2RST_W;
99///Field `SPI3RST` writer - SPI3 reset
100pub use TIM2RST_W as SPI3RST_W;
101///Field `USART2RST` writer - USART 2 reset
102pub use TIM2RST_W as USART2RST_W;
103///Field `USART3RST` writer - USART3 reset
104pub use TIM2RST_W as USART3RST_W;
105///Field `UART4RST` writer - UART 4 reset
106pub use TIM2RST_W as UART4RST_W;
107///Field `UART5RST` writer - UART 5 reset
108pub use TIM2RST_W as UART5RST_W;
109///Field `I2C1RST` writer - I2C1 reset
110pub use TIM2RST_W as I2C1RST_W;
111///Field `I2C2RST` writer - I2C2 reset
112pub use TIM2RST_W as I2C2RST_W;
113///Field `USBRST` writer - USB reset
114pub use TIM2RST_W as USBRST_W;
115///Field `CANRST` writer - CAN reset
116pub use TIM2RST_W as CANRST_W;
117///Field `DAC2RST` writer - DAC2 interface reset
118pub use TIM2RST_W as DAC2RST_W;
119///Field `PWRRST` writer - Power interface reset
120pub use TIM2RST_W as PWRRST_W;
121///Field `DAC1RST` writer - DAC interface reset
122pub use TIM2RST_W as DAC1RST_W;
123///Field `I2C3RST` writer - I2C3 reset
124pub use TIM2RST_W as I2C3RST_W;
125impl R {
126    ///Bit 0 - Timer 2 reset
127    #[inline(always)]
128    pub fn tim2rst(&self) -> TIM2RST_R {
129        TIM2RST_R::new((self.bits & 1) != 0)
130    }
131    ///Bit 1 - Timer 3 reset
132    #[inline(always)]
133    pub fn tim3rst(&self) -> TIM3RST_R {
134        TIM3RST_R::new(((self.bits >> 1) & 1) != 0)
135    }
136    ///Bit 2 - Timer 14 reset
137    #[inline(always)]
138    pub fn tim4rst(&self) -> TIM4RST_R {
139        TIM4RST_R::new(((self.bits >> 2) & 1) != 0)
140    }
141    ///Bit 4 - Timer 6 reset
142    #[inline(always)]
143    pub fn tim6rst(&self) -> TIM6RST_R {
144        TIM6RST_R::new(((self.bits >> 4) & 1) != 0)
145    }
146    ///Bit 5 - Timer 7 reset
147    #[inline(always)]
148    pub fn tim7rst(&self) -> TIM7RST_R {
149        TIM7RST_R::new(((self.bits >> 5) & 1) != 0)
150    }
151    ///Bit 11 - Window watchdog reset
152    #[inline(always)]
153    pub fn wwdgrst(&self) -> WWDGRST_R {
154        WWDGRST_R::new(((self.bits >> 11) & 1) != 0)
155    }
156    ///Bit 14 - SPI2 reset
157    #[inline(always)]
158    pub fn spi2rst(&self) -> SPI2RST_R {
159        SPI2RST_R::new(((self.bits >> 14) & 1) != 0)
160    }
161    ///Bit 15 - SPI3 reset
162    #[inline(always)]
163    pub fn spi3rst(&self) -> SPI3RST_R {
164        SPI3RST_R::new(((self.bits >> 15) & 1) != 0)
165    }
166    ///Bit 17 - USART 2 reset
167    #[inline(always)]
168    pub fn usart2rst(&self) -> USART2RST_R {
169        USART2RST_R::new(((self.bits >> 17) & 1) != 0)
170    }
171    ///Bit 18 - USART3 reset
172    #[inline(always)]
173    pub fn usart3rst(&self) -> USART3RST_R {
174        USART3RST_R::new(((self.bits >> 18) & 1) != 0)
175    }
176    ///Bit 19 - UART 4 reset
177    #[inline(always)]
178    pub fn uart4rst(&self) -> UART4RST_R {
179        UART4RST_R::new(((self.bits >> 19) & 1) != 0)
180    }
181    ///Bit 20 - UART 5 reset
182    #[inline(always)]
183    pub fn uart5rst(&self) -> UART5RST_R {
184        UART5RST_R::new(((self.bits >> 20) & 1) != 0)
185    }
186    ///Bit 21 - I2C1 reset
187    #[inline(always)]
188    pub fn i2c1rst(&self) -> I2C1RST_R {
189        I2C1RST_R::new(((self.bits >> 21) & 1) != 0)
190    }
191    ///Bit 22 - I2C2 reset
192    #[inline(always)]
193    pub fn i2c2rst(&self) -> I2C2RST_R {
194        I2C2RST_R::new(((self.bits >> 22) & 1) != 0)
195    }
196    ///Bit 23 - USB reset
197    #[inline(always)]
198    pub fn usbrst(&self) -> USBRST_R {
199        USBRST_R::new(((self.bits >> 23) & 1) != 0)
200    }
201    ///Bit 25 - CAN reset
202    #[inline(always)]
203    pub fn canrst(&self) -> CANRST_R {
204        CANRST_R::new(((self.bits >> 25) & 1) != 0)
205    }
206    ///Bit 26 - DAC2 interface reset
207    #[inline(always)]
208    pub fn dac2rst(&self) -> DAC2RST_R {
209        DAC2RST_R::new(((self.bits >> 26) & 1) != 0)
210    }
211    ///Bit 28 - Power interface reset
212    #[inline(always)]
213    pub fn pwrrst(&self) -> PWRRST_R {
214        PWRRST_R::new(((self.bits >> 28) & 1) != 0)
215    }
216    ///Bit 29 - DAC interface reset
217    #[inline(always)]
218    pub fn dac1rst(&self) -> DAC1RST_R {
219        DAC1RST_R::new(((self.bits >> 29) & 1) != 0)
220    }
221    ///Bit 30 - I2C3 reset
222    #[inline(always)]
223    pub fn i2c3rst(&self) -> I2C3RST_R {
224        I2C3RST_R::new(((self.bits >> 30) & 1) != 0)
225    }
226}
227impl core::fmt::Debug for R {
228    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
229        f.debug_struct("APB1RSTR")
230            .field("tim2rst", &self.tim2rst())
231            .field("tim3rst", &self.tim3rst())
232            .field("tim4rst", &self.tim4rst())
233            .field("tim6rst", &self.tim6rst())
234            .field("tim7rst", &self.tim7rst())
235            .field("wwdgrst", &self.wwdgrst())
236            .field("spi2rst", &self.spi2rst())
237            .field("spi3rst", &self.spi3rst())
238            .field("usart2rst", &self.usart2rst())
239            .field("usart3rst", &self.usart3rst())
240            .field("uart4rst", &self.uart4rst())
241            .field("uart5rst", &self.uart5rst())
242            .field("i2c1rst", &self.i2c1rst())
243            .field("i2c2rst", &self.i2c2rst())
244            .field("usbrst", &self.usbrst())
245            .field("canrst", &self.canrst())
246            .field("pwrrst", &self.pwrrst())
247            .field("dac1rst", &self.dac1rst())
248            .field("i2c3rst", &self.i2c3rst())
249            .field("dac2rst", &self.dac2rst())
250            .finish()
251    }
252}
253impl W {
254    ///Bit 0 - Timer 2 reset
255    #[inline(always)]
256    pub fn tim2rst(&mut self) -> TIM2RST_W<APB1RSTRrs> {
257        TIM2RST_W::new(self, 0)
258    }
259    ///Bit 1 - Timer 3 reset
260    #[inline(always)]
261    pub fn tim3rst(&mut self) -> TIM3RST_W<APB1RSTRrs> {
262        TIM3RST_W::new(self, 1)
263    }
264    ///Bit 2 - Timer 14 reset
265    #[inline(always)]
266    pub fn tim4rst(&mut self) -> TIM4RST_W<APB1RSTRrs> {
267        TIM4RST_W::new(self, 2)
268    }
269    ///Bit 4 - Timer 6 reset
270    #[inline(always)]
271    pub fn tim6rst(&mut self) -> TIM6RST_W<APB1RSTRrs> {
272        TIM6RST_W::new(self, 4)
273    }
274    ///Bit 5 - Timer 7 reset
275    #[inline(always)]
276    pub fn tim7rst(&mut self) -> TIM7RST_W<APB1RSTRrs> {
277        TIM7RST_W::new(self, 5)
278    }
279    ///Bit 11 - Window watchdog reset
280    #[inline(always)]
281    pub fn wwdgrst(&mut self) -> WWDGRST_W<APB1RSTRrs> {
282        WWDGRST_W::new(self, 11)
283    }
284    ///Bit 14 - SPI2 reset
285    #[inline(always)]
286    pub fn spi2rst(&mut self) -> SPI2RST_W<APB1RSTRrs> {
287        SPI2RST_W::new(self, 14)
288    }
289    ///Bit 15 - SPI3 reset
290    #[inline(always)]
291    pub fn spi3rst(&mut self) -> SPI3RST_W<APB1RSTRrs> {
292        SPI3RST_W::new(self, 15)
293    }
294    ///Bit 17 - USART 2 reset
295    #[inline(always)]
296    pub fn usart2rst(&mut self) -> USART2RST_W<APB1RSTRrs> {
297        USART2RST_W::new(self, 17)
298    }
299    ///Bit 18 - USART3 reset
300    #[inline(always)]
301    pub fn usart3rst(&mut self) -> USART3RST_W<APB1RSTRrs> {
302        USART3RST_W::new(self, 18)
303    }
304    ///Bit 19 - UART 4 reset
305    #[inline(always)]
306    pub fn uart4rst(&mut self) -> UART4RST_W<APB1RSTRrs> {
307        UART4RST_W::new(self, 19)
308    }
309    ///Bit 20 - UART 5 reset
310    #[inline(always)]
311    pub fn uart5rst(&mut self) -> UART5RST_W<APB1RSTRrs> {
312        UART5RST_W::new(self, 20)
313    }
314    ///Bit 21 - I2C1 reset
315    #[inline(always)]
316    pub fn i2c1rst(&mut self) -> I2C1RST_W<APB1RSTRrs> {
317        I2C1RST_W::new(self, 21)
318    }
319    ///Bit 22 - I2C2 reset
320    #[inline(always)]
321    pub fn i2c2rst(&mut self) -> I2C2RST_W<APB1RSTRrs> {
322        I2C2RST_W::new(self, 22)
323    }
324    ///Bit 23 - USB reset
325    #[inline(always)]
326    pub fn usbrst(&mut self) -> USBRST_W<APB1RSTRrs> {
327        USBRST_W::new(self, 23)
328    }
329    ///Bit 25 - CAN reset
330    #[inline(always)]
331    pub fn canrst(&mut self) -> CANRST_W<APB1RSTRrs> {
332        CANRST_W::new(self, 25)
333    }
334    ///Bit 26 - DAC2 interface reset
335    #[inline(always)]
336    pub fn dac2rst(&mut self) -> DAC2RST_W<APB1RSTRrs> {
337        DAC2RST_W::new(self, 26)
338    }
339    ///Bit 28 - Power interface reset
340    #[inline(always)]
341    pub fn pwrrst(&mut self) -> PWRRST_W<APB1RSTRrs> {
342        PWRRST_W::new(self, 28)
343    }
344    ///Bit 29 - DAC interface reset
345    #[inline(always)]
346    pub fn dac1rst(&mut self) -> DAC1RST_W<APB1RSTRrs> {
347        DAC1RST_W::new(self, 29)
348    }
349    ///Bit 30 - I2C3 reset
350    #[inline(always)]
351    pub fn i2c3rst(&mut self) -> I2C3RST_W<APB1RSTRrs> {
352        I2C3RST_W::new(self, 30)
353    }
354}
355/**APB1 peripheral reset register (RCC_APB1RSTR)
356
357You can [`read`](crate::Reg::read) this register and get [`apb1rstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1rstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
358
359See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#RCC:APB1RSTR)*/
360pub struct APB1RSTRrs;
361impl crate::RegisterSpec for APB1RSTRrs {
362    type Ux = u32;
363}
364///`read()` method returns [`apb1rstr::R`](R) reader structure
365impl crate::Readable for APB1RSTRrs {}
366///`write(|w| ..)` method takes [`apb1rstr::W`](W) writer structure
367impl crate::Writable for APB1RSTRrs {
368    type Safety = crate::Unsafe;
369}
370///`reset()` method sets APB1RSTR to value 0
371impl crate::Resettable for APB1RSTRrs {}
stm32f3/stm32f303/rcc/apb1rstr.rs

stm32f3/stm32f303/rcc/
apb1rstr.rs
