stm32f3/stm32f303/
fmc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    bcr1: BCR1,
6    btr: (),
7    _reserved2: [u8; 0x04],
8    bcr: (),
9    _reserved3: [u8; 0x58],
10    pcr: (),
11    _reserved4: [u8; 0x04],
12    sr: (),
13    _reserved5: [u8; 0x04],
14    pmem: (),
15    _reserved6: [u8; 0x04],
16    patt: (),
17    _reserved7: [u8; 0x08],
18    eccr: (),
19    _reserved8: [u8; 0x3c],
20    pio4: PIO4,
21    _reserved9: [u8; 0x50],
22    bwtr: (),
23}
24impl RegisterBlock {
25    ///0x00 - SRAM/NOR-Flash chip-select control register 1
26    #[inline(always)]
27    pub const fn bcr1(&self) -> &BCR1 {
28        &self.bcr1
29    }
30    ///0x04..0x14 - SRAM/NOR-Flash chip-select timing register %s
31    ///
32    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BTR1` register.</div>
33    #[inline(always)]
34    pub const fn btr(&self, n: usize) -> &BTR {
35        #[allow(clippy::no_effect)]
36        [(); 4][n];
37        unsafe {
38            &*core::ptr::from_ref(self)
39                .cast::<u8>()
40                .add(4)
41                .add(8 * n)
42                .cast()
43        }
44    }
45    ///Iterator for array of:
46    ///0x04..0x14 - SRAM/NOR-Flash chip-select timing register %s
47    #[inline(always)]
48    pub fn btr_iter(&self) -> impl Iterator<Item = &BTR> {
49        (0..4).map(move |n| unsafe {
50            &*core::ptr::from_ref(self)
51                .cast::<u8>()
52                .add(4)
53                .add(8 * n)
54                .cast()
55        })
56    }
57    ///0x04 - SRAM/NOR-Flash chip-select timing register 1
58    #[inline(always)]
59    pub const fn btr1(&self) -> &BTR {
60        self.btr(0)
61    }
62    ///0x0c - SRAM/NOR-Flash chip-select timing register 2
63    #[inline(always)]
64    pub const fn btr2(&self) -> &BTR {
65        self.btr(1)
66    }
67    ///0x14 - SRAM/NOR-Flash chip-select timing register 3
68    #[inline(always)]
69    pub const fn btr3(&self) -> &BTR {
70        self.btr(2)
71    }
72    ///0x1c - SRAM/NOR-Flash chip-select timing register 4
73    #[inline(always)]
74    pub const fn btr4(&self) -> &BTR {
75        self.btr(3)
76    }
77    ///0x08..0x14 - SRAM/NOR-Flash chip-select control register %s
78    ///
79    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BCR2` register.</div>
80    #[inline(always)]
81    pub const fn bcr(&self, n: usize) -> &BCR {
82        #[allow(clippy::no_effect)]
83        [(); 3][n];
84        unsafe {
85            &*core::ptr::from_ref(self)
86                .cast::<u8>()
87                .add(8)
88                .add(8 * n)
89                .cast()
90        }
91    }
92    ///Iterator for array of:
93    ///0x08..0x14 - SRAM/NOR-Flash chip-select control register %s
94    #[inline(always)]
95    pub fn bcr_iter(&self) -> impl Iterator<Item = &BCR> {
96        (0..3).map(move |n| unsafe {
97            &*core::ptr::from_ref(self)
98                .cast::<u8>()
99                .add(8)
100                .add(8 * n)
101                .cast()
102        })
103    }
104    ///0x08 - SRAM/NOR-Flash chip-select control register 2
105    #[inline(always)]
106    pub const fn bcr2(&self) -> &BCR {
107        self.bcr(0)
108    }
109    ///0x10 - SRAM/NOR-Flash chip-select control register 3
110    #[inline(always)]
111    pub const fn bcr3(&self) -> &BCR {
112        self.bcr(1)
113    }
114    ///0x18 - SRAM/NOR-Flash chip-select control register 4
115    #[inline(always)]
116    pub const fn bcr4(&self) -> &BCR {
117        self.bcr(2)
118    }
119    ///0x60..0x6c - PC Card/NAND Flash control register %s
120    ///
121    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `PCR2` register.</div>
122    #[inline(always)]
123    pub const fn pcr(&self, n: usize) -> &PCR {
124        #[allow(clippy::no_effect)]
125        [(); 3][n];
126        unsafe {
127            &*core::ptr::from_ref(self)
128                .cast::<u8>()
129                .add(96)
130                .add(32 * n)
131                .cast()
132        }
133    }
134    ///Iterator for array of:
135    ///0x60..0x6c - PC Card/NAND Flash control register %s
136    #[inline(always)]
137    pub fn pcr_iter(&self) -> impl Iterator<Item = &PCR> {
138        (0..3).map(move |n| unsafe {
139            &*core::ptr::from_ref(self)
140                .cast::<u8>()
141                .add(96)
142                .add(32 * n)
143                .cast()
144        })
145    }
146    ///0x60 - PC Card/NAND Flash control register 2
147    #[inline(always)]
148    pub const fn pcr2(&self) -> &PCR {
149        self.pcr(0)
150    }
151    ///0x80 - PC Card/NAND Flash control register 3
152    #[inline(always)]
153    pub const fn pcr3(&self) -> &PCR {
154        self.pcr(1)
155    }
156    ///0xa0 - PC Card/NAND Flash control register 4
157    #[inline(always)]
158    pub const fn pcr4(&self) -> &PCR {
159        self.pcr(2)
160    }
161    ///0x64..0x70 - FIFO status and interrupt register %s
162    ///
163    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `SR2` register.</div>
164    #[inline(always)]
165    pub const fn sr(&self, n: usize) -> &SR {
166        #[allow(clippy::no_effect)]
167        [(); 3][n];
168        unsafe {
169            &*core::ptr::from_ref(self)
170                .cast::<u8>()
171                .add(100)
172                .add(32 * n)
173                .cast()
174        }
175    }
176    ///Iterator for array of:
177    ///0x64..0x70 - FIFO status and interrupt register %s
178    #[inline(always)]
179    pub fn sr_iter(&self) -> impl Iterator<Item = &SR> {
180        (0..3).map(move |n| unsafe {
181            &*core::ptr::from_ref(self)
182                .cast::<u8>()
183                .add(100)
184                .add(32 * n)
185                .cast()
186        })
187    }
188    ///0x64 - FIFO status and interrupt register 2
189    #[inline(always)]
190    pub const fn sr2(&self) -> &SR {
191        self.sr(0)
192    }
193    ///0x84 - FIFO status and interrupt register 3
194    #[inline(always)]
195    pub const fn sr3(&self) -> &SR {
196        self.sr(1)
197    }
198    ///0xa4 - FIFO status and interrupt register 4
199    #[inline(always)]
200    pub const fn sr4(&self) -> &SR {
201        self.sr(2)
202    }
203    ///0x68..0x74 - Common memory space timing register %s
204    ///
205    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `PMEM2` register.</div>
206    #[inline(always)]
207    pub const fn pmem(&self, n: usize) -> &PMEM {
208        #[allow(clippy::no_effect)]
209        [(); 3][n];
210        unsafe {
211            &*core::ptr::from_ref(self)
212                .cast::<u8>()
213                .add(104)
214                .add(32 * n)
215                .cast()
216        }
217    }
218    ///Iterator for array of:
219    ///0x68..0x74 - Common memory space timing register %s
220    #[inline(always)]
221    pub fn pmem_iter(&self) -> impl Iterator<Item = &PMEM> {
222        (0..3).map(move |n| unsafe {
223            &*core::ptr::from_ref(self)
224                .cast::<u8>()
225                .add(104)
226                .add(32 * n)
227                .cast()
228        })
229    }
230    ///0x68 - Common memory space timing register 2
231    #[inline(always)]
232    pub const fn pmem2(&self) -> &PMEM {
233        self.pmem(0)
234    }
235    ///0x88 - Common memory space timing register 3
236    #[inline(always)]
237    pub const fn pmem3(&self) -> &PMEM {
238        self.pmem(1)
239    }
240    ///0xa8 - Common memory space timing register 4
241    #[inline(always)]
242    pub const fn pmem4(&self) -> &PMEM {
243        self.pmem(2)
244    }
245    ///0x6c..0x78 - Attribute memory space timing register %s
246    ///
247    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `PATT2` register.</div>
248    #[inline(always)]
249    pub const fn patt(&self, n: usize) -> &PATT {
250        #[allow(clippy::no_effect)]
251        [(); 3][n];
252        unsafe {
253            &*core::ptr::from_ref(self)
254                .cast::<u8>()
255                .add(108)
256                .add(32 * n)
257                .cast()
258        }
259    }
260    ///Iterator for array of:
261    ///0x6c..0x78 - Attribute memory space timing register %s
262    #[inline(always)]
263    pub fn patt_iter(&self) -> impl Iterator<Item = &PATT> {
264        (0..3).map(move |n| unsafe {
265            &*core::ptr::from_ref(self)
266                .cast::<u8>()
267                .add(108)
268                .add(32 * n)
269                .cast()
270        })
271    }
272    ///0x6c - Attribute memory space timing register 2
273    #[inline(always)]
274    pub const fn patt2(&self) -> &PATT {
275        self.patt(0)
276    }
277    ///0x8c - Attribute memory space timing register 3
278    #[inline(always)]
279    pub const fn patt3(&self) -> &PATT {
280        self.patt(1)
281    }
282    ///0xac - Attribute memory space timing register 4
283    #[inline(always)]
284    pub const fn patt4(&self) -> &PATT {
285        self.patt(2)
286    }
287    ///0x74..0x7c - ECC result register %s
288    ///
289    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `ECCR2` register.</div>
290    #[inline(always)]
291    pub const fn eccr(&self, n: usize) -> &ECCR {
292        #[allow(clippy::no_effect)]
293        [(); 2][n];
294        unsafe {
295            &*core::ptr::from_ref(self)
296                .cast::<u8>()
297                .add(116)
298                .add(32 * n)
299                .cast()
300        }
301    }
302    ///Iterator for array of:
303    ///0x74..0x7c - ECC result register %s
304    #[inline(always)]
305    pub fn eccr_iter(&self) -> impl Iterator<Item = &ECCR> {
306        (0..2).map(move |n| unsafe {
307            &*core::ptr::from_ref(self)
308                .cast::<u8>()
309                .add(116)
310                .add(32 * n)
311                .cast()
312        })
313    }
314    ///0x74 - ECC result register 2
315    #[inline(always)]
316    pub const fn eccr2(&self) -> &ECCR {
317        self.eccr(0)
318    }
319    ///0x94 - ECC result register 3
320    #[inline(always)]
321    pub const fn eccr3(&self) -> &ECCR {
322        self.eccr(1)
323    }
324    ///0xb0 - I/O space timing register 4
325    #[inline(always)]
326    pub const fn pio4(&self) -> &PIO4 {
327        &self.pio4
328    }
329    ///0x104..0x114 - SRAM/NOR-Flash write timing registers %s
330    ///
331    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BWTR1` register.</div>
332    #[inline(always)]
333    pub const fn bwtr(&self, n: usize) -> &BWTR {
334        #[allow(clippy::no_effect)]
335        [(); 4][n];
336        unsafe {
337            &*core::ptr::from_ref(self)
338                .cast::<u8>()
339                .add(260)
340                .add(8 * n)
341                .cast()
342        }
343    }
344    ///Iterator for array of:
345    ///0x104..0x114 - SRAM/NOR-Flash write timing registers %s
346    #[inline(always)]
347    pub fn bwtr_iter(&self) -> impl Iterator<Item = &BWTR> {
348        (0..4).map(move |n| unsafe {
349            &*core::ptr::from_ref(self)
350                .cast::<u8>()
351                .add(260)
352                .add(8 * n)
353                .cast()
354        })
355    }
356    ///0x104 - SRAM/NOR-Flash write timing registers 1
357    #[inline(always)]
358    pub const fn bwtr1(&self) -> &BWTR {
359        self.bwtr(0)
360    }
361    ///0x10c - SRAM/NOR-Flash write timing registers 2
362    #[inline(always)]
363    pub const fn bwtr2(&self) -> &BWTR {
364        self.bwtr(1)
365    }
366    ///0x114 - SRAM/NOR-Flash write timing registers 3
367    #[inline(always)]
368    pub const fn bwtr3(&self) -> &BWTR {
369        self.bwtr(2)
370    }
371    ///0x11c - SRAM/NOR-Flash write timing registers 4
372    #[inline(always)]
373    pub const fn bwtr4(&self) -> &BWTR {
374        self.bwtr(3)
375    }
376}
377/**BCR1 (rw) register accessor: SRAM/NOR-Flash chip-select control register 1
378
379You can [`read`](crate::Reg::read) this register and get [`bcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
380
381See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC:BCR1)
382
383For information about available fields see [`mod@bcr1`] module*/
384pub type BCR1 = crate::Reg<bcr1::BCR1rs>;
385///SRAM/NOR-Flash chip-select control register 1
386pub mod bcr1;
387/**BTR (rw) register accessor: SRAM/NOR-Flash chip-select timing register %s
388
389You can [`read`](crate::Reg::read) this register and get [`btr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
390
391See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC:BTR[1])
392
393For information about available fields see [`mod@btr`] module*/
394pub type BTR = crate::Reg<btr::BTRrs>;
395///SRAM/NOR-Flash chip-select timing register %s
396pub mod btr;
397/**BCR (rw) register accessor: SRAM/NOR-Flash chip-select control register %s
398
399You can [`read`](crate::Reg::read) this register and get [`bcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
400
401See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC:BCR[2])
402
403For information about available fields see [`mod@bcr`] module*/
404pub type BCR = crate::Reg<bcr::BCRrs>;
405///SRAM/NOR-Flash chip-select control register %s
406pub mod bcr;
407/**PCR (rw) register accessor: PC Card/NAND Flash control register %s
408
409You can [`read`](crate::Reg::read) this register and get [`pcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
410
411See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC:PCR[2])
412
413For information about available fields see [`mod@pcr`] module*/
414pub type PCR = crate::Reg<pcr::PCRrs>;
415///PC Card/NAND Flash control register %s
416pub mod pcr;
417/**SR (rw) register accessor: FIFO status and interrupt register %s
418
419You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
420
421See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC:SR[2])
422
423For information about available fields see [`mod@sr`] module*/
424pub type SR = crate::Reg<sr::SRrs>;
425///FIFO status and interrupt register %s
426pub mod sr;
427/**PMEM (rw) register accessor: Common memory space timing register %s
428
429You can [`read`](crate::Reg::read) this register and get [`pmem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
430
431See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC:PMEM[2])
432
433For information about available fields see [`mod@pmem`] module*/
434pub type PMEM = crate::Reg<pmem::PMEMrs>;
435///Common memory space timing register %s
436pub mod pmem;
437/**PATT (rw) register accessor: Attribute memory space timing register %s
438
439You can [`read`](crate::Reg::read) this register and get [`patt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`patt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
440
441See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC:PATT[2])
442
443For information about available fields see [`mod@patt`] module*/
444pub type PATT = crate::Reg<patt::PATTrs>;
445///Attribute memory space timing register %s
446pub mod patt;
447/**ECCR (r) register accessor: ECC result register %s
448
449You can [`read`](crate::Reg::read) this register and get [`eccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
450
451See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC:ECCR[2])
452
453For information about available fields see [`mod@eccr`] module*/
454pub type ECCR = crate::Reg<eccr::ECCRrs>;
455///ECC result register %s
456pub mod eccr;
457/**PIO4 (rw) register accessor: I/O space timing register 4
458
459You can [`read`](crate::Reg::read) this register and get [`pio4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
460
461See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC:PIO4)
462
463For information about available fields see [`mod@pio4`] module*/
464pub type PIO4 = crate::Reg<pio4::PIO4rs>;
465///I/O space timing register 4
466pub mod pio4;
467/**BWTR (rw) register accessor: SRAM/NOR-Flash write timing registers %s
468
469You can [`read`](crate::Reg::read) this register and get [`bwtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bwtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
470
471See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC:BWTR[1])
472
473For information about available fields see [`mod@bwtr`] module*/
474pub type BWTR = crate::Reg<bwtr::BWTRrs>;
475///SRAM/NOR-Flash write timing registers %s
476pub mod bwtr;
stm32f3/stm32f303/fmc.rs

stm32f3/stm32f303/
fmc.rs
