stm32f3/stm32f303/flash/
acr.rs

1///Register `ACR` reader
2pub type R = crate::R<ACRrs>;
3///Register `ACR` writer
4pub type W = crate::W<ACRrs>;
5/**LATENCY
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum LATENCY {
12    ///0: 0 wait states, if 0 < HCLK <= 24 MHz
13    Ws0 = 0,
14    ///1: 1 wait state, if 24 < HCLK <= 48 MHz
15    Ws1 = 1,
16    ///2: 2 wait states, if 48 < HCLK <= 72 MHz
17    Ws2 = 2,
18}
19impl From<LATENCY> for u8 {
20    #[inline(always)]
21    fn from(variant: LATENCY) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for LATENCY {
26    type Ux = u8;
27}
28impl crate::IsEnum for LATENCY {}
29///Field `LATENCY` reader - LATENCY
30pub type LATENCY_R = crate::FieldReader<LATENCY>;
31impl LATENCY_R {
32    ///Get enumerated values variant
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<LATENCY> {
35        match self.bits {
36            0 => Some(LATENCY::Ws0),
37            1 => Some(LATENCY::Ws1),
38            2 => Some(LATENCY::Ws2),
39            _ => None,
40        }
41    }
42    ///0 wait states, if 0 < HCLK <= 24 MHz
43    #[inline(always)]
44    pub fn is_ws0(&self) -> bool {
45        *self == LATENCY::Ws0
46    }
47    ///1 wait state, if 24 < HCLK <= 48 MHz
48    #[inline(always)]
49    pub fn is_ws1(&self) -> bool {
50        *self == LATENCY::Ws1
51    }
52    ///2 wait states, if 48 < HCLK <= 72 MHz
53    #[inline(always)]
54    pub fn is_ws2(&self) -> bool {
55        *self == LATENCY::Ws2
56    }
57}
58///Field `LATENCY` writer - LATENCY
59pub type LATENCY_W<'a, REG> = crate::FieldWriter<'a, REG, 3, LATENCY>;
60impl<'a, REG> LATENCY_W<'a, REG>
61where
62    REG: crate::Writable + crate::RegisterSpec,
63    REG::Ux: From<u8>,
64{
65    ///0 wait states, if 0 < HCLK <= 24 MHz
66    #[inline(always)]
67    pub fn ws0(self) -> &'a mut crate::W<REG> {
68        self.variant(LATENCY::Ws0)
69    }
70    ///1 wait state, if 24 < HCLK <= 48 MHz
71    #[inline(always)]
72    pub fn ws1(self) -> &'a mut crate::W<REG> {
73        self.variant(LATENCY::Ws1)
74    }
75    ///2 wait states, if 48 < HCLK <= 72 MHz
76    #[inline(always)]
77    pub fn ws2(self) -> &'a mut crate::W<REG> {
78        self.variant(LATENCY::Ws2)
79    }
80}
81/**Flash half cycle access enable
82
83Value on reset: 0*/
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86pub enum HLFCYA {
87    ///0: Half cycle is disabled
88    Disabled = 0,
89    ///1: Half cycle is enabled
90    Enabled = 1,
91}
92impl From<HLFCYA> for bool {
93    #[inline(always)]
94    fn from(variant: HLFCYA) -> Self {
95        variant as u8 != 0
96    }
97}
98///Field `HLFCYA` reader - Flash half cycle access enable
99pub type HLFCYA_R = crate::BitReader<HLFCYA>;
100impl HLFCYA_R {
101    ///Get enumerated values variant
102    #[inline(always)]
103    pub const fn variant(&self) -> HLFCYA {
104        match self.bits {
105            false => HLFCYA::Disabled,
106            true => HLFCYA::Enabled,
107        }
108    }
109    ///Half cycle is disabled
110    #[inline(always)]
111    pub fn is_disabled(&self) -> bool {
112        *self == HLFCYA::Disabled
113    }
114    ///Half cycle is enabled
115    #[inline(always)]
116    pub fn is_enabled(&self) -> bool {
117        *self == HLFCYA::Enabled
118    }
119}
120///Field `HLFCYA` writer - Flash half cycle access enable
121pub type HLFCYA_W<'a, REG> = crate::BitWriter<'a, REG, HLFCYA>;
122impl<'a, REG> HLFCYA_W<'a, REG>
123where
124    REG: crate::Writable + crate::RegisterSpec,
125{
126    ///Half cycle is disabled
127    #[inline(always)]
128    pub fn disabled(self) -> &'a mut crate::W<REG> {
129        self.variant(HLFCYA::Disabled)
130    }
131    ///Half cycle is enabled
132    #[inline(always)]
133    pub fn enabled(self) -> &'a mut crate::W<REG> {
134        self.variant(HLFCYA::Enabled)
135    }
136}
137/**PRFTBE
138
139Value on reset: 1*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum PRFTBE {
143    ///0: Prefetch is disabled
144    Disabled = 0,
145    ///1: Prefetch is enabled
146    Enabled = 1,
147}
148impl From<PRFTBE> for bool {
149    #[inline(always)]
150    fn from(variant: PRFTBE) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `PRFTBE` reader - PRFTBE
155pub type PRFTBE_R = crate::BitReader<PRFTBE>;
156impl PRFTBE_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> PRFTBE {
160        match self.bits {
161            false => PRFTBE::Disabled,
162            true => PRFTBE::Enabled,
163        }
164    }
165    ///Prefetch is disabled
166    #[inline(always)]
167    pub fn is_disabled(&self) -> bool {
168        *self == PRFTBE::Disabled
169    }
170    ///Prefetch is enabled
171    #[inline(always)]
172    pub fn is_enabled(&self) -> bool {
173        *self == PRFTBE::Enabled
174    }
175}
176///Field `PRFTBE` writer - PRFTBE
177pub type PRFTBE_W<'a, REG> = crate::BitWriter<'a, REG, PRFTBE>;
178impl<'a, REG> PRFTBE_W<'a, REG>
179where
180    REG: crate::Writable + crate::RegisterSpec,
181{
182    ///Prefetch is disabled
183    #[inline(always)]
184    pub fn disabled(self) -> &'a mut crate::W<REG> {
185        self.variant(PRFTBE::Disabled)
186    }
187    ///Prefetch is enabled
188    #[inline(always)]
189    pub fn enabled(self) -> &'a mut crate::W<REG> {
190        self.variant(PRFTBE::Enabled)
191    }
192}
193/**PRFTBS
194
195Value on reset: 1*/
196#[cfg_attr(feature = "defmt", derive(defmt::Format))]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198pub enum PRFTBS {
199    ///0: Prefetch buffer is disabled
200    Disabled = 0,
201    ///1: Prefetch buffer is enabled
202    Enabled = 1,
203}
204impl From<PRFTBS> for bool {
205    #[inline(always)]
206    fn from(variant: PRFTBS) -> Self {
207        variant as u8 != 0
208    }
209}
210///Field `PRFTBS` reader - PRFTBS
211pub type PRFTBS_R = crate::BitReader<PRFTBS>;
212impl PRFTBS_R {
213    ///Get enumerated values variant
214    #[inline(always)]
215    pub const fn variant(&self) -> PRFTBS {
216        match self.bits {
217            false => PRFTBS::Disabled,
218            true => PRFTBS::Enabled,
219        }
220    }
221    ///Prefetch buffer is disabled
222    #[inline(always)]
223    pub fn is_disabled(&self) -> bool {
224        *self == PRFTBS::Disabled
225    }
226    ///Prefetch buffer is enabled
227    #[inline(always)]
228    pub fn is_enabled(&self) -> bool {
229        *self == PRFTBS::Enabled
230    }
231}
232impl R {
233    ///Bits 0:2 - LATENCY
234    #[inline(always)]
235    pub fn latency(&self) -> LATENCY_R {
236        LATENCY_R::new((self.bits & 7) as u8)
237    }
238    ///Bit 3 - Flash half cycle access enable
239    #[inline(always)]
240    pub fn hlfcya(&self) -> HLFCYA_R {
241        HLFCYA_R::new(((self.bits >> 3) & 1) != 0)
242    }
243    ///Bit 4 - PRFTBE
244    #[inline(always)]
245    pub fn prftbe(&self) -> PRFTBE_R {
246        PRFTBE_R::new(((self.bits >> 4) & 1) != 0)
247    }
248    ///Bit 5 - PRFTBS
249    #[inline(always)]
250    pub fn prftbs(&self) -> PRFTBS_R {
251        PRFTBS_R::new(((self.bits >> 5) & 1) != 0)
252    }
253}
254impl core::fmt::Debug for R {
255    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
256        f.debug_struct("ACR")
257            .field("latency", &self.latency())
258            .field("prftbe", &self.prftbe())
259            .field("prftbs", &self.prftbs())
260            .field("hlfcya", &self.hlfcya())
261            .finish()
262    }
263}
264impl W {
265    ///Bits 0:2 - LATENCY
266    #[inline(always)]
267    pub fn latency(&mut self) -> LATENCY_W<ACRrs> {
268        LATENCY_W::new(self, 0)
269    }
270    ///Bit 3 - Flash half cycle access enable
271    #[inline(always)]
272    pub fn hlfcya(&mut self) -> HLFCYA_W<ACRrs> {
273        HLFCYA_W::new(self, 3)
274    }
275    ///Bit 4 - PRFTBE
276    #[inline(always)]
277    pub fn prftbe(&mut self) -> PRFTBE_W<ACRrs> {
278        PRFTBE_W::new(self, 4)
279    }
280}
281/**Flash access control register
282
283You can [`read`](crate::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
284
285See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FLASH:ACR)*/
286pub struct ACRrs;
287impl crate::RegisterSpec for ACRrs {
288    type Ux = u32;
289}
290///`read()` method returns [`acr::R`](R) reader structure
291impl crate::Readable for ACRrs {}
292///`write(|w| ..)` method takes [`acr::W`](W) writer structure
293impl crate::Writable for ACRrs {
294    type Safety = crate::Unsafe;
295}
296///`reset()` method sets ACR to value 0x30
297impl crate::Resettable for ACRrs {
298    const RESET_VALUE: u32 = 0x30;
299}
stm32f3/stm32f303/flash/acr.rs

stm32f3/stm32f303/flash/
acr.rs
