stm32f3 0.16.0

/*!Peripheral access API for STM32F302 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))

You can find an overview of the generated API [here].

API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.

[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
[repository]: https://github.com/rust-embedded/svd2rust*/
///Number available in the NVIC for configuring priority
pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
    fn WWDG();
    fn PVD();
    fn TAMP_STAMP();
    fn RTC_WKUP();
    fn FLASH();
    fn RCC();
    fn EXTI0();
    fn EXTI1();
    fn EXTI2_TSC();
    fn EXTI3();
    fn EXTI4();
    fn DMA1_CH1();
    fn DMA1_CH2();
    fn DMA1_CH3();
    fn DMA1_CH4();
    fn DMA1_CH5();
    fn DMA1_CH6();
    fn DMA1_CH7();
    fn ADC1_2();
    fn USB_HP_CAN_TX();
    fn USB_LP_CAN_RX0();
    fn CAN_RX1();
    fn CAN_SCE();
    fn EXTI9_5();
    fn TIM1_BRK_TIM15();
    fn TIM1_UP_TIM16();
    fn TIM1_TRG_COM_TIM17();
    fn TIM1_CC();
    fn TIM2();
    fn TIM3();
    fn TIM4();
    fn I2C1_EV_EXTI23();
    fn I2C1_ER();
    fn I2C2_EV_EXTI24();
    fn I2C2_ER();
    fn SPI1();
    fn SPI2();
    fn USART1_EXTI25();
    fn USART2_EXTI26();
    fn USART3_EXTI28();
    fn EXTI15_10();
    fn RTCALARM();
    fn USB_WKUP();
    fn TIM8_BRK();
    fn TIM8_UP();
    fn TIM8_TRG_COM();
    fn TIM8_CC();
    fn FMC();
    fn SPI3();
    fn UART4_EXTI34();
    fn UART5_EXTI35();
    fn TIM6_DACUNDER();
    fn TIM7();
    fn DMA2_CH1();
    fn DMA2_CH2();
    fn DMA2_CH3();
    fn DMA2_CH4();
    fn DMA2_CH5();
    fn COMP1_2_3();
    fn COMP4_5_6();
    fn USB_HP();
    fn USB_LP();
    fn USB_WKUP_EXTI();
    fn FPU();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
    _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 82] = [
    Vector { _handler: WWDG },
    Vector { _handler: PVD },
    Vector {
        _handler: TAMP_STAMP,
    },
    Vector { _handler: RTC_WKUP },
    Vector { _handler: FLASH },
    Vector { _handler: RCC },
    Vector { _handler: EXTI0 },
    Vector { _handler: EXTI1 },
    Vector {
        _handler: EXTI2_TSC,
    },
    Vector { _handler: EXTI3 },
    Vector { _handler: EXTI4 },
    Vector { _handler: DMA1_CH1 },
    Vector { _handler: DMA1_CH2 },
    Vector { _handler: DMA1_CH3 },
    Vector { _handler: DMA1_CH4 },
    Vector { _handler: DMA1_CH5 },
    Vector { _handler: DMA1_CH6 },
    Vector { _handler: DMA1_CH7 },
    Vector { _handler: ADC1_2 },
    Vector {
        _handler: USB_HP_CAN_TX,
    },
    Vector {
        _handler: USB_LP_CAN_RX0,
    },
    Vector { _handler: CAN_RX1 },
    Vector { _handler: CAN_SCE },
    Vector { _handler: EXTI9_5 },
    Vector {
        _handler: TIM1_BRK_TIM15,
    },
    Vector {
        _handler: TIM1_UP_TIM16,
    },
    Vector {
        _handler: TIM1_TRG_COM_TIM17,
    },
    Vector { _handler: TIM1_CC },
    Vector { _handler: TIM2 },
    Vector { _handler: TIM3 },
    Vector { _handler: TIM4 },
    Vector {
        _handler: I2C1_EV_EXTI23,
    },
    Vector { _handler: I2C1_ER },
    Vector {
        _handler: I2C2_EV_EXTI24,
    },
    Vector { _handler: I2C2_ER },
    Vector { _handler: SPI1 },
    Vector { _handler: SPI2 },
    Vector {
        _handler: USART1_EXTI25,
    },
    Vector {
        _handler: USART2_EXTI26,
    },
    Vector {
        _handler: USART3_EXTI28,
    },
    Vector {
        _handler: EXTI15_10,
    },
    Vector { _handler: RTCALARM },
    Vector { _handler: USB_WKUP },
    Vector { _handler: TIM8_BRK },
    Vector { _handler: TIM8_UP },
    Vector {
        _handler: TIM8_TRG_COM,
    },
    Vector { _handler: TIM8_CC },
    Vector { _reserved: 0 },
    Vector { _handler: FMC },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: SPI3 },
    Vector {
        _handler: UART4_EXTI34,
    },
    Vector {
        _handler: UART5_EXTI35,
    },
    Vector {
        _handler: TIM6_DACUNDER,
    },
    Vector { _handler: TIM7 },
    Vector { _handler: DMA2_CH1 },
    Vector { _handler: DMA2_CH2 },
    Vector { _handler: DMA2_CH3 },
    Vector { _handler: DMA2_CH4 },
    Vector { _handler: DMA2_CH5 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector {
        _handler: COMP1_2_3,
    },
    Vector {
        _handler: COMP4_5_6,
    },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: USB_HP },
    Vector { _handler: USB_LP },
    Vector {
        _handler: USB_WKUP_EXTI,
    },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: FPU },
];
///Enumeration of all the interrupts.
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
    ///0 - Window Watchdog interrupt
    WWDG = 0,
    ///1 - PVD through EXTI line detection interrupt
    PVD = 1,
    ///2 - Tamper and TimeStamp interrupts
    TAMP_STAMP = 2,
    ///3 - RTC Wakeup interrupt through the EXTI line
    RTC_WKUP = 3,
    ///4 - Flash global interrupt
    FLASH = 4,
    ///5 - RCC global interrupt
    RCC = 5,
    ///6 - EXTI Line0 interrupt
    EXTI0 = 6,
    ///7 - EXTI Line3 interrupt
    EXTI1 = 7,
    ///8 - EXTI Line2 and Touch sensing interrupts
    EXTI2_TSC = 8,
    ///9 - EXTI Line3 interrupt
    EXTI3 = 9,
    ///10 - EXTI Line4 interrupt
    EXTI4 = 10,
    ///11 - DMA1 channel 1 interrupt
    DMA1_CH1 = 11,
    ///12 - DMA1 channel 2 interrupt
    DMA1_CH2 = 12,
    ///13 - DMA1 channel 3 interrupt
    DMA1_CH3 = 13,
    ///14 - DMA1 channel 4 interrupt
    DMA1_CH4 = 14,
    ///15 - DMA1 channel 5 interrupt
    DMA1_CH5 = 15,
    ///16 - DMA1 channel 6 interrupt
    DMA1_CH6 = 16,
    ///17 - DMA1 channel 7interrupt
    DMA1_CH7 = 17,
    ///18 - ADC1 and ADC2 global interrupt
    ADC1_2 = 18,
    ///19 - USB High Priority/CAN_TX interrupts
    USB_HP_CAN_TX = 19,
    ///20 - USB Low Priority/CAN_RX0 interrupts
    USB_LP_CAN_RX0 = 20,
    ///21 - CAN_RX1 interrupt
    CAN_RX1 = 21,
    ///22 - CAN_SCE interrupt
    CAN_SCE = 22,
    ///23 - EXTI Line5 to Line9 interrupts
    EXTI9_5 = 23,
    ///24 - TIM1 Break/TIM15 global interruts
    TIM1_BRK_TIM15 = 24,
    ///25 - TIM1 Update/TIM16 global interrupts
    TIM1_UP_TIM16 = 25,
    ///26 - TIM1 trigger and commutation/TIM17 interrupts
    TIM1_TRG_COM_TIM17 = 26,
    ///27 - TIM1 capture compare interrupt
    TIM1_CC = 27,
    ///28 - TIM2 global interrupt
    TIM2 = 28,
    ///29 - TIM3 global interrupt
    TIM3 = 29,
    ///30 - TIM4 global interrupt
    TIM4 = 30,
    ///31 - I2C1 event interrupt and EXTI Line23 interrupt
    I2C1_EV_EXTI23 = 31,
    ///32 - I2C1 error interrupt
    I2C1_ER = 32,
    ///33 - I2C2 event interrupt & EXTI Line24 interrupt
    I2C2_EV_EXTI24 = 33,
    ///34 - I2C2 error interrupt
    I2C2_ER = 34,
    ///35 - SPI1 global interrupt
    SPI1 = 35,
    ///36 - SPI2 global interrupt
    SPI2 = 36,
    ///37 - USART1 global interrupt and EXTI Line 25 interrupt
    USART1_EXTI25 = 37,
    ///38 - USART2 global interrupt and EXTI Line 26 interrupt
    USART2_EXTI26 = 38,
    ///39 - USART3 global interrupt and EXTI Line 28 interrupt
    USART3_EXTI28 = 39,
    ///40 - EXTI Line15 to Line10 interrupts
    EXTI15_10 = 40,
    ///41 - RTC alarm interrupt
    RTCALARM = 41,
    ///42 - USB wakeup from Suspend
    USB_WKUP = 42,
    ///43 - TIM8 break interrupt
    TIM8_BRK = 43,
    ///44 - TIM8 update interrupt
    TIM8_UP = 44,
    ///45 - TIM8 Trigger and commutation interrupts
    TIM8_TRG_COM = 45,
    ///46 - TIM8 capture compare interrupt
    TIM8_CC = 46,
    ///48 - FSMC global interrupt
    FMC = 48,
    ///51 - SPI3 global interrupt
    SPI3 = 51,
    ///52 - UART4 global and EXTI Line 34 interrupts
    UART4_EXTI34 = 52,
    ///53 - UART5 global and EXTI Line 35 interrupts
    UART5_EXTI35 = 53,
    ///54 - TIM6 global and DAC12 underrun interrupts
    TIM6_DACUNDER = 54,
    ///55 - TIM7 global interrupt
    TIM7 = 55,
    ///56 - DMA2 channel1 global interrupt
    DMA2_CH1 = 56,
    ///57 - DMA2 channel2 global interrupt
    DMA2_CH2 = 57,
    ///58 - DMA2 channel3 global interrupt
    DMA2_CH3 = 58,
    ///59 - DMA2 channel4 global interrupt
    DMA2_CH4 = 59,
    ///60 - DMA2 channel5 global interrupt
    DMA2_CH5 = 60,
    ///64 - COMP1_2_3 interrupt combined with EXTI lines 21, 22, 29
    COMP1_2_3 = 64,
    ///65 - COMP4_5_6 interrupt combined with EXTI lines 30, 31, 32
    COMP4_5_6 = 65,
    ///74 - USB High priority interrupt
    USB_HP = 74,
    ///75 - USB Low priority interrupt
    USB_LP = 75,
    ///76 - USB wakeup from Suspend and EXTI Line 18
    USB_WKUP_EXTI = 76,
    ///81 - Floating point unit interrupt
    FPU = 81,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#GPIOA)
pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4800_0000>;
impl core::fmt::Debug for GPIOA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOA").finish()
    }
}
///General-purpose I/Os
pub mod gpioa;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#GPIOB)
pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4800_0400>;
impl core::fmt::Debug for GPIOB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOB").finish()
    }
}
///General-purpose I/Os
pub mod gpiob;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#GPIOC)
pub type GPIOC = crate::Periph<gpioc::RegisterBlock, 0x4800_0800>;
impl core::fmt::Debug for GPIOC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOC").finish()
    }
}
///General-purpose I/Os
pub mod gpioc;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#GPIOC)
pub type GPIOD = crate::Periph<gpioc::RegisterBlock, 0x4800_0c00>;
impl core::fmt::Debug for GPIOD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOD").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpiod;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#GPIOC)
pub type GPIOE = crate::Periph<gpioc::RegisterBlock, 0x4800_1000>;
impl core::fmt::Debug for GPIOE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOE").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpioe;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#GPIOC)
pub type GPIOF = crate::Periph<gpioc::RegisterBlock, 0x4800_1400>;
impl core::fmt::Debug for GPIOF {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOF").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpiof;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#GPIOC)
pub type GPIOG = crate::Periph<gpioc::RegisterBlock, 0x4800_1800>;
impl core::fmt::Debug for GPIOG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOG").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpiog;
///General-purpose I/Os
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#GPIOC)
pub type GPIOH = crate::Periph<gpioc::RegisterBlock, 0x4800_1c00>;
impl core::fmt::Debug for GPIOH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOH").finish()
    }
}
///General-purpose I/Os
pub use self::gpioc as gpioh;
///Touch sensing controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TSC)
pub type TSC = crate::Periph<tsc::RegisterBlock, 0x4002_4000>;
impl core::fmt::Debug for TSC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TSC").finish()
    }
}
///Touch sensing controller
pub mod tsc;
///cyclic redundancy check calculation unit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#CRC)
pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
impl core::fmt::Debug for CRC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRC").finish()
    }
}
///cyclic redundancy check calculation unit
pub mod crc;
///Flash
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#FLASH)
pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
impl core::fmt::Debug for FLASH {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FLASH").finish()
    }
}
///Flash
pub mod flash;
///Reset and clock control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#RCC)
pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
impl core::fmt::Debug for RCC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RCC").finish()
    }
}
///Reset and clock control
pub mod rcc;
///DMA controller 1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#DMA1)
pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for DMA1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA1").finish()
    }
}
///DMA controller 1
pub mod dma1;
///DMA controller 1
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#DMA1)
pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
impl core::fmt::Debug for DMA2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA2").finish()
    }
}
///DMA controller 1
pub use self::dma1 as dma2;
///General purpose timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM2)
pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for TIM2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM2").finish()
    }
}
///General purpose timer
pub mod tim2;
///General purpose timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM3)
pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
impl core::fmt::Debug for TIM3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM3").finish()
    }
}
///General purpose timer
pub mod tim3;
///General purpose timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM3)
pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
impl core::fmt::Debug for TIM4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM4").finish()
    }
}
///General purpose timer
pub use self::tim3 as tim4;
///General purpose timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM15)
pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for TIM15 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM15").finish()
    }
}
///General purpose timers
pub mod tim15;
///General-purpose-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM16)
pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4001_4400>;
impl core::fmt::Debug for TIM16 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM16").finish()
    }
}
///General-purpose-timers
pub mod tim16;
///General purpose timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM17)
pub type TIM17 = crate::Periph<tim17::RegisterBlock, 0x4001_4800>;
impl core::fmt::Debug for TIM17 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM17").finish()
    }
}
///General purpose timer
pub mod tim17;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#USART1)
pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
impl core::fmt::Debug for USART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART1").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub mod usart1;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#USART1)
pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
impl core::fmt::Debug for USART2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART2").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart2;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#USART1)
pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
impl core::fmt::Debug for USART3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USART3").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as usart3;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#USART1)
pub type UART4 = crate::Periph<usart1::RegisterBlock, 0x4000_4c00>;
impl core::fmt::Debug for UART4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART4").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as uart4;
///Universal synchronous asynchronous receiver transmitter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#USART1)
pub type UART5 = crate::Periph<usart1::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for UART5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART5").finish()
    }
}
///Universal synchronous asynchronous receiver transmitter
pub use self::usart1 as uart5;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#SPI1)
pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for SPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI1").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub mod spi1;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#SPI1)
pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
impl core::fmt::Debug for SPI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI2").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub use self::spi1 as spi2;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#SPI1)
pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
impl core::fmt::Debug for SPI3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI3").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub use self::spi1 as spi3;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#SPI1)
pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4001_3c00>;
impl core::fmt::Debug for SPI4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI4").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub use self::spi1 as spi4;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#I2S2ext)
pub type I2S2EXT = crate::Periph<i2s2ext::RegisterBlock, 0x4000_3400>;
impl core::fmt::Debug for I2S2EXT {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2S2EXT").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub mod i2s2ext;
///Serial peripheral interface/Inter-IC sound
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#I2S2ext)
pub type I2S3EXT = crate::Periph<i2s2ext::RegisterBlock, 0x4000_4000>;
impl core::fmt::Debug for I2S3EXT {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2S3EXT").finish()
    }
}
///Serial peripheral interface/Inter-IC sound
pub use self::i2s2ext as i2s3ext;
///External interrupt/event controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#EXTI)
pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
impl core::fmt::Debug for EXTI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EXTI").finish()
    }
}
///External interrupt/event controller
pub mod exti;
///Power control
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#PWR)
pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
impl core::fmt::Debug for PWR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PWR").finish()
    }
}
///Power control
pub mod pwr;
///Controller area network
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#CAN)
pub type CAN = crate::Periph<can::RegisterBlock, 0x4000_6400>;
impl core::fmt::Debug for CAN {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CAN").finish()
    }
}
///Controller area network
pub mod can;
///Universal serial bus full-speed device interface
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#USB)
pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
impl core::fmt::Debug for USB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USB").finish()
    }
}
///Universal serial bus full-speed device interface
pub mod usb;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#I2C1)
pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
impl core::fmt::Debug for I2C1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C1").finish()
    }
}
///Inter-integrated circuit
pub mod i2c1;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#I2C1)
pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
impl core::fmt::Debug for I2C2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C2").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c2;
///Inter-integrated circuit
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#I2C1)
pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_7800>;
impl core::fmt::Debug for I2C3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C3").finish()
    }
}
///Inter-integrated circuit
pub use self::i2c1 as i2c3;
///Independent watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#IWDG)
pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for IWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IWDG").finish()
    }
}
///Independent watchdog
pub mod iwdg;
///Window watchdog
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#WWDG)
pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
impl core::fmt::Debug for WWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WWDG").finish()
    }
}
///Window watchdog
pub mod wwdg;
///Real-time clock
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#RTC)
pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
impl core::fmt::Debug for RTC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RTC").finish()
    }
}
///Real-time clock
pub mod rtc;
///Basic timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM6)
pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for TIM6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM6").finish()
    }
}
///Basic timers
pub mod tim6;
///Basic timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM6)
pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
impl core::fmt::Debug for TIM7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM7").finish()
    }
}
///Basic timers
pub use self::tim6 as tim7;
///Digital-to-analog converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#DAC1)
pub type DAC1 = crate::Periph<dac1::RegisterBlock, 0x4000_7400>;
impl core::fmt::Debug for DAC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC1").finish()
    }
}
///Digital-to-analog converter
pub mod dac1;
///Debug support
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#DBGMCU)
pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
impl core::fmt::Debug for DBGMCU {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DBGMCU").finish()
    }
}
///Debug support
pub mod dbgmcu;
///Advanced timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1)
pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
impl core::fmt::Debug for TIM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM1").finish()
    }
}
///Advanced timer
pub mod tim1;
///Advanced timer
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM1)
pub type TIM20 = crate::Periph<tim1::RegisterBlock, 0x4001_5000>;
impl core::fmt::Debug for TIM20 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM20").finish()
    }
}
///Advanced timer
pub use self::tim1 as tim20;
///Advanced-timers
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#TIM8)
pub type TIM8 = crate::Periph<tim8::RegisterBlock, 0x4001_3400>;
impl core::fmt::Debug for TIM8 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIM8").finish()
    }
}
///Advanced-timers
pub mod tim8;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#ADC1)
pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x5000_0000>;
impl core::fmt::Debug for ADC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC1").finish()
    }
}
///Analog-to-Digital Converter
pub mod adc1;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#ADC1)
pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x5000_0100>;
impl core::fmt::Debug for ADC2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC2").finish()
    }
}
///Analog-to-Digital Converter
pub use self::adc1 as adc2;
///Analog-to-Digital Converter
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#ADC1_2)
pub type ADC1_2 = crate::Periph<adc1_2::RegisterBlock, 0x5000_0300>;
impl core::fmt::Debug for ADC1_2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC1_2").finish()
    }
}
///Analog-to-Digital Converter
pub mod adc1_2;
///Flexible memory controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#FMC)
pub type FMC = crate::Periph<fmc::RegisterBlock, 0xa000_0000>;
impl core::fmt::Debug for FMC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FMC").finish()
    }
}
///Flexible memory controller
pub mod fmc;
///System configuration controller
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#SYSCFG)
pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for SYSCFG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYSCFG").finish()
    }
}
///System configuration controller
pub mod syscfg;
///Operational Amplifier
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#OPAMP)
pub type OPAMP = crate::Periph<opamp::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for OPAMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OPAMP").finish()
    }
}
///Operational Amplifier
pub mod opamp;
///General purpose comparators
///
///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F302.html#COMP)
pub type COMP = crate::Periph<comp::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for COMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("COMP").finish()
    }
}
///General purpose comparators
pub mod comp;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
/// All the peripherals.
#[allow(non_snake_case)]
pub struct Peripherals {
    ///GPIOA
    pub GPIOA: GPIOA,
    ///GPIOB
    pub GPIOB: GPIOB,
    ///GPIOC
    pub GPIOC: GPIOC,
    ///GPIOD
    pub GPIOD: GPIOD,
    ///GPIOE
    pub GPIOE: GPIOE,
    ///GPIOF
    pub GPIOF: GPIOF,
    ///GPIOG
    pub GPIOG: GPIOG,
    ///GPIOH
    pub GPIOH: GPIOH,
    ///TSC
    pub TSC: TSC,
    ///CRC
    pub CRC: CRC,
    ///FLASH
    pub FLASH: FLASH,
    ///RCC
    pub RCC: RCC,
    ///DMA1
    pub DMA1: DMA1,
    ///DMA2
    pub DMA2: DMA2,
    ///TIM2
    pub TIM2: TIM2,
    ///TIM3
    pub TIM3: TIM3,
    ///TIM4
    pub TIM4: TIM4,
    ///TIM15
    pub TIM15: TIM15,
    ///TIM16
    pub TIM16: TIM16,
    ///TIM17
    pub TIM17: TIM17,
    ///USART1
    pub USART1: USART1,
    ///USART2
    pub USART2: USART2,
    ///USART3
    pub USART3: USART3,
    ///UART4
    pub UART4: UART4,
    ///UART5
    pub UART5: UART5,
    ///SPI1
    pub SPI1: SPI1,
    ///SPI2
    pub SPI2: SPI2,
    ///SPI3
    pub SPI3: SPI3,
    ///SPI4
    pub SPI4: SPI4,
    ///I2S2ext
    pub I2S2EXT: I2S2EXT,
    ///I2S3ext
    pub I2S3EXT: I2S3EXT,
    ///EXTI
    pub EXTI: EXTI,
    ///PWR
    pub PWR: PWR,
    ///CAN
    pub CAN: CAN,
    ///USB
    pub USB: USB,
    ///I2C1
    pub I2C1: I2C1,
    ///I2C2
    pub I2C2: I2C2,
    ///I2C3
    pub I2C3: I2C3,
    ///IWDG
    pub IWDG: IWDG,
    ///WWDG
    pub WWDG: WWDG,
    ///RTC
    pub RTC: RTC,
    ///TIM6
    pub TIM6: TIM6,
    ///TIM7
    pub TIM7: TIM7,
    ///DAC1
    pub DAC1: DAC1,
    ///DBGMCU
    pub DBGMCU: DBGMCU,
    ///TIM1
    pub TIM1: TIM1,
    ///TIM20
    pub TIM20: TIM20,
    ///TIM8
    pub TIM8: TIM8,
    ///ADC1
    pub ADC1: ADC1,
    ///ADC2
    pub ADC2: ADC2,
    ///ADC1_2
    pub ADC1_2: ADC1_2,
    ///FMC
    pub FMC: FMC,
    ///SYSCFG
    pub SYSCFG: SYSCFG,
    ///OPAMP
    pub OPAMP: OPAMP,
    ///COMP
    pub COMP: COMP,
}
impl Peripherals {
    /// Returns all the peripherals *once*.
    #[cfg(feature = "critical-section")]
    #[inline]
    pub fn take() -> Option<Self> {
        critical_section::with(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                return None;
            }
            Some(unsafe { Peripherals::steal() })
        })
    }
    /// Unchecked version of `Peripherals::take`.
    ///
    /// # Safety
    ///
    /// Each of the returned peripherals must be used at most once.
    #[inline]
    pub unsafe fn steal() -> Self {
        DEVICE_PERIPHERALS = true;
        Peripherals {
            GPIOA: GPIOA::steal(),
            GPIOB: GPIOB::steal(),
            GPIOC: GPIOC::steal(),
            GPIOD: GPIOD::steal(),
            GPIOE: GPIOE::steal(),
            GPIOF: GPIOF::steal(),
            GPIOG: GPIOG::steal(),
            GPIOH: GPIOH::steal(),
            TSC: TSC::steal(),
            CRC: CRC::steal(),
            FLASH: FLASH::steal(),
            RCC: RCC::steal(),
            DMA1: DMA1::steal(),
            DMA2: DMA2::steal(),
            TIM2: TIM2::steal(),
            TIM3: TIM3::steal(),
            TIM4: TIM4::steal(),
            TIM15: TIM15::steal(),
            TIM16: TIM16::steal(),
            TIM17: TIM17::steal(),
            USART1: USART1::steal(),
            USART2: USART2::steal(),
            USART3: USART3::steal(),
            UART4: UART4::steal(),
            UART5: UART5::steal(),
            SPI1: SPI1::steal(),
            SPI2: SPI2::steal(),
            SPI3: SPI3::steal(),
            SPI4: SPI4::steal(),
            I2S2EXT: I2S2EXT::steal(),
            I2S3EXT: I2S3EXT::steal(),
            EXTI: EXTI::steal(),
            PWR: PWR::steal(),
            CAN: CAN::steal(),
            USB: USB::steal(),
            I2C1: I2C1::steal(),
            I2C2: I2C2::steal(),
            I2C3: I2C3::steal(),
            IWDG: IWDG::steal(),
            WWDG: WWDG::steal(),
            RTC: RTC::steal(),
            TIM6: TIM6::steal(),
            TIM7: TIM7::steal(),
            DAC1: DAC1::steal(),
            DBGMCU: DBGMCU::steal(),
            TIM1: TIM1::steal(),
            TIM20: TIM20::steal(),
            TIM8: TIM8::steal(),
            ADC1: ADC1::steal(),
            ADC2: ADC2::steal(),
            ADC1_2: ADC1_2::steal(),
            FMC: FMC::steal(),
            SYSCFG: SYSCFG::steal(),
            OPAMP: OPAMP::steal(),
            COMP: COMP::steal(),
        }
    }
}