pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
fn WWDG();
fn PVD();
fn TAMP_STAMP();
fn RTC_WKUP();
fn FLASH();
fn RCC();
fn EXTI0();
fn EXTI1();
fn EXTI2_TSC();
fn EXTI3();
fn EXTI4();
fn DMA1_CH1();
fn DMA1_CH2();
fn DMA1_CH3();
fn DMA1_CH4();
fn DMA1_CH5();
fn DMA1_CH6();
fn DMA1_CH7();
fn ADC1_2();
fn USB_HP_CAN_TX();
fn USB_LP_CAN_RX0();
fn CAN_RX1();
fn CAN_SCE();
fn EXTI9_5();
fn TIM1_BRK_TIM15();
fn TIM1_UP_TIM16();
fn TIM1_TRG_COM_TIM17();
fn TIM1_CC();
fn TIM2();
fn TIM3();
fn TIM4();
fn I2C1_EV_EXTI23();
fn I2C1_ER();
fn I2C2_EV_EXTI24();
fn I2C2_ER();
fn SPI1();
fn SPI2();
fn USART1_EXTI25();
fn USART2_EXTI26();
fn USART3_EXTI28();
fn EXTI15_10();
fn RTCALARM();
fn USB_WKUP();
fn TIM8_BRK();
fn TIM8_UP();
fn TIM8_TRG_COM();
fn TIM8_CC();
fn FMC();
fn SPI3();
fn UART4_EXTI34();
fn UART5_EXTI35();
fn TIM6_DACUNDER();
fn TIM7();
fn DMA2_CH1();
fn DMA2_CH2();
fn DMA2_CH3();
fn DMA2_CH4();
fn DMA2_CH5();
fn COMP1_2_3();
fn COMP4_5_6();
fn USB_HP();
fn USB_LP();
fn USB_WKUP_EXTI();
fn FPU();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 82] = [
Vector { _handler: WWDG },
Vector { _handler: PVD },
Vector {
_handler: TAMP_STAMP,
},
Vector { _handler: RTC_WKUP },
Vector { _handler: FLASH },
Vector { _handler: RCC },
Vector { _handler: EXTI0 },
Vector { _handler: EXTI1 },
Vector {
_handler: EXTI2_TSC,
},
Vector { _handler: EXTI3 },
Vector { _handler: EXTI4 },
Vector { _handler: DMA1_CH1 },
Vector { _handler: DMA1_CH2 },
Vector { _handler: DMA1_CH3 },
Vector { _handler: DMA1_CH4 },
Vector { _handler: DMA1_CH5 },
Vector { _handler: DMA1_CH6 },
Vector { _handler: DMA1_CH7 },
Vector { _handler: ADC1_2 },
Vector {
_handler: USB_HP_CAN_TX,
},
Vector {
_handler: USB_LP_CAN_RX0,
},
Vector { _handler: CAN_RX1 },
Vector { _handler: CAN_SCE },
Vector { _handler: EXTI9_5 },
Vector {
_handler: TIM1_BRK_TIM15,
},
Vector {
_handler: TIM1_UP_TIM16,
},
Vector {
_handler: TIM1_TRG_COM_TIM17,
},
Vector { _handler: TIM1_CC },
Vector { _handler: TIM2 },
Vector { _handler: TIM3 },
Vector { _handler: TIM4 },
Vector {
_handler: I2C1_EV_EXTI23,
},
Vector { _handler: I2C1_ER },
Vector {
_handler: I2C2_EV_EXTI24,
},
Vector { _handler: I2C2_ER },
Vector { _handler: SPI1 },
Vector { _handler: SPI2 },
Vector {
_handler: USART1_EXTI25,
},
Vector {
_handler: USART2_EXTI26,
},
Vector {
_handler: USART3_EXTI28,
},
Vector {
_handler: EXTI15_10,
},
Vector { _handler: RTCALARM },
Vector { _handler: USB_WKUP },
Vector { _handler: TIM8_BRK },
Vector { _handler: TIM8_UP },
Vector {
_handler: TIM8_TRG_COM,
},
Vector { _handler: TIM8_CC },
Vector { _reserved: 0 },
Vector { _handler: FMC },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: SPI3 },
Vector {
_handler: UART4_EXTI34,
},
Vector {
_handler: UART5_EXTI35,
},
Vector {
_handler: TIM6_DACUNDER,
},
Vector { _handler: TIM7 },
Vector { _handler: DMA2_CH1 },
Vector { _handler: DMA2_CH2 },
Vector { _handler: DMA2_CH3 },
Vector { _handler: DMA2_CH4 },
Vector { _handler: DMA2_CH5 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector {
_handler: COMP1_2_3,
},
Vector {
_handler: COMP4_5_6,
},
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: USB_HP },
Vector { _handler: USB_LP },
Vector {
_handler: USB_WKUP_EXTI,
},
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: FPU },
];
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
WWDG = 0,
PVD = 1,
TAMP_STAMP = 2,
RTC_WKUP = 3,
FLASH = 4,
RCC = 5,
EXTI0 = 6,
EXTI1 = 7,
EXTI2_TSC = 8,
EXTI3 = 9,
EXTI4 = 10,
DMA1_CH1 = 11,
DMA1_CH2 = 12,
DMA1_CH3 = 13,
DMA1_CH4 = 14,
DMA1_CH5 = 15,
DMA1_CH6 = 16,
DMA1_CH7 = 17,
ADC1_2 = 18,
USB_HP_CAN_TX = 19,
USB_LP_CAN_RX0 = 20,
CAN_RX1 = 21,
CAN_SCE = 22,
EXTI9_5 = 23,
TIM1_BRK_TIM15 = 24,
TIM1_UP_TIM16 = 25,
TIM1_TRG_COM_TIM17 = 26,
TIM1_CC = 27,
TIM2 = 28,
TIM3 = 29,
TIM4 = 30,
I2C1_EV_EXTI23 = 31,
I2C1_ER = 32,
I2C2_EV_EXTI24 = 33,
I2C2_ER = 34,
SPI1 = 35,
SPI2 = 36,
USART1_EXTI25 = 37,
USART2_EXTI26 = 38,
USART3_EXTI28 = 39,
EXTI15_10 = 40,
RTCALARM = 41,
USB_WKUP = 42,
TIM8_BRK = 43,
TIM8_UP = 44,
TIM8_TRG_COM = 45,
TIM8_CC = 46,
FMC = 48,
SPI3 = 51,
UART4_EXTI34 = 52,
UART5_EXTI35 = 53,
TIM6_DACUNDER = 54,
TIM7 = 55,
DMA2_CH1 = 56,
DMA2_CH2 = 57,
DMA2_CH3 = 58,
DMA2_CH4 = 59,
DMA2_CH5 = 60,
COMP1_2_3 = 64,
COMP4_5_6 = 65,
USB_HP = 74,
USB_LP = 75,
USB_WKUP_EXTI = 76,
FPU = 81,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
#[inline(always)]
fn number(self) -> u16 {
self as u16
}
}
pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4800_0000>;
impl core::fmt::Debug for GPIOA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOA").finish()
}
}
pub mod gpioa;
pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4800_0400>;
impl core::fmt::Debug for GPIOB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOB").finish()
}
}
pub mod gpiob;
pub type GPIOC = crate::Periph<gpioc::RegisterBlock, 0x4800_0800>;
impl core::fmt::Debug for GPIOC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOC").finish()
}
}
pub mod gpioc;
pub type GPIOD = crate::Periph<gpioc::RegisterBlock, 0x4800_0c00>;
impl core::fmt::Debug for GPIOD {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOD").finish()
}
}
pub use self::gpioc as gpiod;
pub type GPIOE = crate::Periph<gpioc::RegisterBlock, 0x4800_1000>;
impl core::fmt::Debug for GPIOE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOE").finish()
}
}
pub use self::gpioc as gpioe;
pub type GPIOF = crate::Periph<gpioc::RegisterBlock, 0x4800_1400>;
impl core::fmt::Debug for GPIOF {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOF").finish()
}
}
pub use self::gpioc as gpiof;
pub type GPIOG = crate::Periph<gpioc::RegisterBlock, 0x4800_1800>;
impl core::fmt::Debug for GPIOG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOG").finish()
}
}
pub use self::gpioc as gpiog;
pub type GPIOH = crate::Periph<gpioc::RegisterBlock, 0x4800_1c00>;
impl core::fmt::Debug for GPIOH {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOH").finish()
}
}
pub use self::gpioc as gpioh;
pub type TSC = crate::Periph<tsc::RegisterBlock, 0x4002_4000>;
impl core::fmt::Debug for TSC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TSC").finish()
}
}
pub mod tsc;
pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
impl core::fmt::Debug for CRC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRC").finish()
}
}
pub mod crc;
pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
impl core::fmt::Debug for FLASH {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH").finish()
}
}
pub mod flash;
pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
impl core::fmt::Debug for RCC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RCC").finish()
}
}
pub mod rcc;
pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for DMA1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA1").finish()
}
}
pub mod dma1;
pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
impl core::fmt::Debug for DMA2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA2").finish()
}
}
pub use self::dma1 as dma2;
pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for TIM2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM2").finish()
}
}
pub mod tim2;
pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
impl core::fmt::Debug for TIM3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM3").finish()
}
}
pub mod tim3;
pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
impl core::fmt::Debug for TIM4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM4").finish()
}
}
pub use self::tim3 as tim4;
pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for TIM15 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM15").finish()
}
}
pub mod tim15;
pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4001_4400>;
impl core::fmt::Debug for TIM16 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM16").finish()
}
}
pub mod tim16;
pub type TIM17 = crate::Periph<tim17::RegisterBlock, 0x4001_4800>;
impl core::fmt::Debug for TIM17 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM17").finish()
}
}
pub mod tim17;
pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
impl core::fmt::Debug for USART1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART1").finish()
}
}
pub mod usart1;
pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
impl core::fmt::Debug for USART2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART2").finish()
}
}
pub use self::usart1 as usart2;
pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
impl core::fmt::Debug for USART3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USART3").finish()
}
}
pub use self::usart1 as usart3;
pub type UART4 = crate::Periph<usart1::RegisterBlock, 0x4000_4c00>;
impl core::fmt::Debug for UART4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART4").finish()
}
}
pub use self::usart1 as uart4;
pub type UART5 = crate::Periph<usart1::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for UART5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART5").finish()
}
}
pub use self::usart1 as uart5;
pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for SPI1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI1").finish()
}
}
pub mod spi1;
pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
impl core::fmt::Debug for SPI2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI2").finish()
}
}
pub use self::spi1 as spi2;
pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
impl core::fmt::Debug for SPI3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI3").finish()
}
}
pub use self::spi1 as spi3;
pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4001_3c00>;
impl core::fmt::Debug for SPI4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI4").finish()
}
}
pub use self::spi1 as spi4;
pub type I2S2EXT = crate::Periph<i2s2ext::RegisterBlock, 0x4000_3400>;
impl core::fmt::Debug for I2S2EXT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2S2EXT").finish()
}
}
pub mod i2s2ext;
pub type I2S3EXT = crate::Periph<i2s2ext::RegisterBlock, 0x4000_4000>;
impl core::fmt::Debug for I2S3EXT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2S3EXT").finish()
}
}
pub use self::i2s2ext as i2s3ext;
pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
impl core::fmt::Debug for EXTI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EXTI").finish()
}
}
pub mod exti;
pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
impl core::fmt::Debug for PWR {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PWR").finish()
}
}
pub mod pwr;
pub type CAN = crate::Periph<can::RegisterBlock, 0x4000_6400>;
impl core::fmt::Debug for CAN {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN").finish()
}
}
pub mod can;
pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
impl core::fmt::Debug for USB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB").finish()
}
}
pub mod usb;
pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
impl core::fmt::Debug for I2C1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C1").finish()
}
}
pub mod i2c1;
pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
impl core::fmt::Debug for I2C2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C2").finish()
}
}
pub use self::i2c1 as i2c2;
pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_7800>;
impl core::fmt::Debug for I2C3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C3").finish()
}
}
pub use self::i2c1 as i2c3;
pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for IWDG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IWDG").finish()
}
}
pub mod iwdg;
pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
impl core::fmt::Debug for WWDG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WWDG").finish()
}
}
pub mod wwdg;
pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
impl core::fmt::Debug for RTC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTC").finish()
}
}
pub mod rtc;
pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for TIM6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM6").finish()
}
}
pub mod tim6;
pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
impl core::fmt::Debug for TIM7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM7").finish()
}
}
pub use self::tim6 as tim7;
pub type DAC1 = crate::Periph<dac1::RegisterBlock, 0x4000_7400>;
impl core::fmt::Debug for DAC1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DAC1").finish()
}
}
pub mod dac1;
pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
impl core::fmt::Debug for DBGMCU {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DBGMCU").finish()
}
}
pub mod dbgmcu;
pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
impl core::fmt::Debug for TIM1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM1").finish()
}
}
pub mod tim1;
pub type TIM20 = crate::Periph<tim1::RegisterBlock, 0x4001_5000>;
impl core::fmt::Debug for TIM20 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM20").finish()
}
}
pub use self::tim1 as tim20;
pub type TIM8 = crate::Periph<tim8::RegisterBlock, 0x4001_3400>;
impl core::fmt::Debug for TIM8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM8").finish()
}
}
pub mod tim8;
pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x5000_0000>;
impl core::fmt::Debug for ADC1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC1").finish()
}
}
pub mod adc1;
pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x5000_0100>;
impl core::fmt::Debug for ADC2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC2").finish()
}
}
pub use self::adc1 as adc2;
pub type ADC1_2 = crate::Periph<adc1_2::RegisterBlock, 0x5000_0300>;
impl core::fmt::Debug for ADC1_2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC1_2").finish()
}
}
pub mod adc1_2;
pub type FMC = crate::Periph<fmc::RegisterBlock, 0xa000_0000>;
impl core::fmt::Debug for FMC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FMC").finish()
}
}
pub mod fmc;
pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for SYSCFG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SYSCFG").finish()
}
}
pub mod syscfg;
pub type OPAMP = crate::Periph<opamp::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for OPAMP {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OPAMP").finish()
}
}
pub mod opamp;
pub type COMP = crate::Periph<comp::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for COMP {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("COMP").finish()
}
}
pub mod comp;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[allow(non_snake_case)]
pub struct Peripherals {
pub GPIOA: GPIOA,
pub GPIOB: GPIOB,
pub GPIOC: GPIOC,
pub GPIOD: GPIOD,
pub GPIOE: GPIOE,
pub GPIOF: GPIOF,
pub GPIOG: GPIOG,
pub GPIOH: GPIOH,
pub TSC: TSC,
pub CRC: CRC,
pub FLASH: FLASH,
pub RCC: RCC,
pub DMA1: DMA1,
pub DMA2: DMA2,
pub TIM2: TIM2,
pub TIM3: TIM3,
pub TIM4: TIM4,
pub TIM15: TIM15,
pub TIM16: TIM16,
pub TIM17: TIM17,
pub USART1: USART1,
pub USART2: USART2,
pub USART3: USART3,
pub UART4: UART4,
pub UART5: UART5,
pub SPI1: SPI1,
pub SPI2: SPI2,
pub SPI3: SPI3,
pub SPI4: SPI4,
pub I2S2EXT: I2S2EXT,
pub I2S3EXT: I2S3EXT,
pub EXTI: EXTI,
pub PWR: PWR,
pub CAN: CAN,
pub USB: USB,
pub I2C1: I2C1,
pub I2C2: I2C2,
pub I2C3: I2C3,
pub IWDG: IWDG,
pub WWDG: WWDG,
pub RTC: RTC,
pub TIM6: TIM6,
pub TIM7: TIM7,
pub DAC1: DAC1,
pub DBGMCU: DBGMCU,
pub TIM1: TIM1,
pub TIM20: TIM20,
pub TIM8: TIM8,
pub ADC1: ADC1,
pub ADC2: ADC2,
pub ADC1_2: ADC1_2,
pub FMC: FMC,
pub SYSCFG: SYSCFG,
pub OPAMP: OPAMP,
pub COMP: COMP,
}
impl Peripherals {
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
GPIOA: GPIOA::steal(),
GPIOB: GPIOB::steal(),
GPIOC: GPIOC::steal(),
GPIOD: GPIOD::steal(),
GPIOE: GPIOE::steal(),
GPIOF: GPIOF::steal(),
GPIOG: GPIOG::steal(),
GPIOH: GPIOH::steal(),
TSC: TSC::steal(),
CRC: CRC::steal(),
FLASH: FLASH::steal(),
RCC: RCC::steal(),
DMA1: DMA1::steal(),
DMA2: DMA2::steal(),
TIM2: TIM2::steal(),
TIM3: TIM3::steal(),
TIM4: TIM4::steal(),
TIM15: TIM15::steal(),
TIM16: TIM16::steal(),
TIM17: TIM17::steal(),
USART1: USART1::steal(),
USART2: USART2::steal(),
USART3: USART3::steal(),
UART4: UART4::steal(),
UART5: UART5::steal(),
SPI1: SPI1::steal(),
SPI2: SPI2::steal(),
SPI3: SPI3::steal(),
SPI4: SPI4::steal(),
I2S2EXT: I2S2EXT::steal(),
I2S3EXT: I2S3EXT::steal(),
EXTI: EXTI::steal(),
PWR: PWR::steal(),
CAN: CAN::steal(),
USB: USB::steal(),
I2C1: I2C1::steal(),
I2C2: I2C2::steal(),
I2C3: I2C3::steal(),
IWDG: IWDG::steal(),
WWDG: WWDG::steal(),
RTC: RTC::steal(),
TIM6: TIM6::steal(),
TIM7: TIM7::steal(),
DAC1: DAC1::steal(),
DBGMCU: DBGMCU::steal(),
TIM1: TIM1::steal(),
TIM20: TIM20::steal(),
TIM8: TIM8::steal(),
ADC1: ADC1::steal(),
ADC2: ADC2::steal(),
ADC1_2: ADC1_2::steal(),
FMC: FMC::steal(),
SYSCFG: SYSCFG::steal(),
OPAMP: OPAMP::steal(),
COMP: COMP::steal(),
}
}
}