stm32f3/stm32f303/dbgmcu/
apb1_fz.rs1#[doc = "Register `APB1_FZ` reader"]
2pub struct R(crate::R<APB1_FZ_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<APB1_FZ_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<APB1_FZ_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<APB1_FZ_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `APB1_FZ` writer"]
17pub struct W(crate::W<APB1_FZ_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<APB1_FZ_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<APB1_FZ_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<APB1_FZ_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `DBG_TIM2_STOP` reader - Debug Timer 2 stopped when Core is halted"]
38pub type DBG_TIM2_STOP_R = crate::BitReader<bool>;
39#[doc = "Field `DBG_TIM2_STOP` writer - Debug Timer 2 stopped when Core is halted"]
40pub type DBG_TIM2_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
41#[doc = "Field `DBG_TIM3_STOP` reader - Debug Timer 3 stopped when Core is halted"]
42pub type DBG_TIM3_STOP_R = crate::BitReader<bool>;
43#[doc = "Field `DBG_TIM3_STOP` writer - Debug Timer 3 stopped when Core is halted"]
44pub type DBG_TIM3_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
45#[doc = "Field `DBG_TIM4_STOP` reader - Debug Timer 4 stopped when Core is halted"]
46pub type DBG_TIM4_STOP_R = crate::BitReader<bool>;
47#[doc = "Field `DBG_TIM4_STOP` writer - Debug Timer 4 stopped when Core is halted"]
48pub type DBG_TIM4_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
49#[doc = "Field `DBG_TIM5_STOP` reader - Debug Timer 5 stopped when Core is halted"]
50pub type DBG_TIM5_STOP_R = crate::BitReader<bool>;
51#[doc = "Field `DBG_TIM5_STOP` writer - Debug Timer 5 stopped when Core is halted"]
52pub type DBG_TIM5_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
53#[doc = "Field `DBG_TIM6_STOP` reader - Debug Timer 6 stopped when Core is halted"]
54pub type DBG_TIM6_STOP_R = crate::BitReader<bool>;
55#[doc = "Field `DBG_TIM6_STOP` writer - Debug Timer 6 stopped when Core is halted"]
56pub type DBG_TIM6_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
57#[doc = "Field `DBG_TIM7_STOP` reader - Debug Timer 7 stopped when Core is halted"]
58pub type DBG_TIM7_STOP_R = crate::BitReader<bool>;
59#[doc = "Field `DBG_TIM7_STOP` writer - Debug Timer 7 stopped when Core is halted"]
60pub type DBG_TIM7_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
61#[doc = "Field `DBG_TIM12_STOP` reader - Debug Timer 12 stopped when Core is halted"]
62pub type DBG_TIM12_STOP_R = crate::BitReader<bool>;
63#[doc = "Field `DBG_TIM12_STOP` writer - Debug Timer 12 stopped when Core is halted"]
64pub type DBG_TIM12_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
65#[doc = "Field `DBG_TIM13_STOP` reader - Debug Timer 13 stopped when Core is halted"]
66pub type DBG_TIM13_STOP_R = crate::BitReader<bool>;
67#[doc = "Field `DBG_TIM13_STOP` writer - Debug Timer 13 stopped when Core is halted"]
68pub type DBG_TIM13_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
69#[doc = "Field `DBG_TIMER14_STOP` reader - Debug Timer 14 stopped when Core is halted"]
70pub type DBG_TIMER14_STOP_R = crate::BitReader<bool>;
71#[doc = "Field `DBG_TIMER14_STOP` writer - Debug Timer 14 stopped when Core is halted"]
72pub type DBG_TIMER14_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
73#[doc = "Field `DBG_TIM18_STOP` reader - Debug Timer 18 stopped when Core is halted"]
74pub type DBG_TIM18_STOP_R = crate::BitReader<bool>;
75#[doc = "Field `DBG_TIM18_STOP` writer - Debug Timer 18 stopped when Core is halted"]
76pub type DBG_TIM18_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
77#[doc = "Field `DBG_RTC_STOP` reader - Debug RTC stopped when Core is halted"]
78pub type DBG_RTC_STOP_R = crate::BitReader<bool>;
79#[doc = "Field `DBG_RTC_STOP` writer - Debug RTC stopped when Core is halted"]
80pub type DBG_RTC_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
81#[doc = "Field `DBG_WWDG_STOP` reader - Debug Window Wachdog stopped when Core is halted"]
82pub type DBG_WWDG_STOP_R = crate::BitReader<bool>;
83#[doc = "Field `DBG_WWDG_STOP` writer - Debug Window Wachdog stopped when Core is halted"]
84pub type DBG_WWDG_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
85#[doc = "Field `DBG_IWDG_STOP` reader - Debug Independent Wachdog stopped when Core is halted"]
86pub type DBG_IWDG_STOP_R = crate::BitReader<bool>;
87#[doc = "Field `DBG_IWDG_STOP` writer - Debug Independent Wachdog stopped when Core is halted"]
88pub type DBG_IWDG_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
89#[doc = "Field `I2C1_SMBUS_TIMEOUT` reader - SMBUS timeout mode stopped when Core is halted"]
90pub type I2C1_SMBUS_TIMEOUT_R = crate::BitReader<bool>;
91#[doc = "Field `I2C1_SMBUS_TIMEOUT` writer - SMBUS timeout mode stopped when Core is halted"]
92pub type I2C1_SMBUS_TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
93#[doc = "Field `I2C2_SMBUS_TIMEOUT` reader - SMBUS timeout mode stopped when Core is halted"]
94pub type I2C2_SMBUS_TIMEOUT_R = crate::BitReader<bool>;
95#[doc = "Field `I2C2_SMBUS_TIMEOUT` writer - SMBUS timeout mode stopped when Core is halted"]
96pub type I2C2_SMBUS_TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
97#[doc = "Field `DBG_CAN_STOP` reader - Debug CAN stopped when core is halted"]
98pub type DBG_CAN_STOP_R = crate::BitReader<bool>;
99#[doc = "Field `DBG_CAN_STOP` writer - Debug CAN stopped when core is halted"]
100pub type DBG_CAN_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1_FZ_SPEC, bool, O>;
101impl R {
102 #[doc = "Bit 0 - Debug Timer 2 stopped when Core is halted"]
103 #[inline(always)]
104 pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R {
105 DBG_TIM2_STOP_R::new((self.bits & 1) != 0)
106 }
107 #[doc = "Bit 1 - Debug Timer 3 stopped when Core is halted"]
108 #[inline(always)]
109 pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R {
110 DBG_TIM3_STOP_R::new(((self.bits >> 1) & 1) != 0)
111 }
112 #[doc = "Bit 2 - Debug Timer 4 stopped when Core is halted"]
113 #[inline(always)]
114 pub fn dbg_tim4_stop(&self) -> DBG_TIM4_STOP_R {
115 DBG_TIM4_STOP_R::new(((self.bits >> 2) & 1) != 0)
116 }
117 #[doc = "Bit 3 - Debug Timer 5 stopped when Core is halted"]
118 #[inline(always)]
119 pub fn dbg_tim5_stop(&self) -> DBG_TIM5_STOP_R {
120 DBG_TIM5_STOP_R::new(((self.bits >> 3) & 1) != 0)
121 }
122 #[doc = "Bit 4 - Debug Timer 6 stopped when Core is halted"]
123 #[inline(always)]
124 pub fn dbg_tim6_stop(&self) -> DBG_TIM6_STOP_R {
125 DBG_TIM6_STOP_R::new(((self.bits >> 4) & 1) != 0)
126 }
127 #[doc = "Bit 5 - Debug Timer 7 stopped when Core is halted"]
128 #[inline(always)]
129 pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R {
130 DBG_TIM7_STOP_R::new(((self.bits >> 5) & 1) != 0)
131 }
132 #[doc = "Bit 6 - Debug Timer 12 stopped when Core is halted"]
133 #[inline(always)]
134 pub fn dbg_tim12_stop(&self) -> DBG_TIM12_STOP_R {
135 DBG_TIM12_STOP_R::new(((self.bits >> 6) & 1) != 0)
136 }
137 #[doc = "Bit 7 - Debug Timer 13 stopped when Core is halted"]
138 #[inline(always)]
139 pub fn dbg_tim13_stop(&self) -> DBG_TIM13_STOP_R {
140 DBG_TIM13_STOP_R::new(((self.bits >> 7) & 1) != 0)
141 }
142 #[doc = "Bit 8 - Debug Timer 14 stopped when Core is halted"]
143 #[inline(always)]
144 pub fn dbg_timer14_stop(&self) -> DBG_TIMER14_STOP_R {
145 DBG_TIMER14_STOP_R::new(((self.bits >> 8) & 1) != 0)
146 }
147 #[doc = "Bit 9 - Debug Timer 18 stopped when Core is halted"]
148 #[inline(always)]
149 pub fn dbg_tim18_stop(&self) -> DBG_TIM18_STOP_R {
150 DBG_TIM18_STOP_R::new(((self.bits >> 9) & 1) != 0)
151 }
152 #[doc = "Bit 10 - Debug RTC stopped when Core is halted"]
153 #[inline(always)]
154 pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R {
155 DBG_RTC_STOP_R::new(((self.bits >> 10) & 1) != 0)
156 }
157 #[doc = "Bit 11 - Debug Window Wachdog stopped when Core is halted"]
158 #[inline(always)]
159 pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R {
160 DBG_WWDG_STOP_R::new(((self.bits >> 11) & 1) != 0)
161 }
162 #[doc = "Bit 12 - Debug Independent Wachdog stopped when Core is halted"]
163 #[inline(always)]
164 pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R {
165 DBG_IWDG_STOP_R::new(((self.bits >> 12) & 1) != 0)
166 }
167 #[doc = "Bit 21 - SMBUS timeout mode stopped when Core is halted"]
168 #[inline(always)]
169 pub fn i2c1_smbus_timeout(&self) -> I2C1_SMBUS_TIMEOUT_R {
170 I2C1_SMBUS_TIMEOUT_R::new(((self.bits >> 21) & 1) != 0)
171 }
172 #[doc = "Bit 22 - SMBUS timeout mode stopped when Core is halted"]
173 #[inline(always)]
174 pub fn i2c2_smbus_timeout(&self) -> I2C2_SMBUS_TIMEOUT_R {
175 I2C2_SMBUS_TIMEOUT_R::new(((self.bits >> 22) & 1) != 0)
176 }
177 #[doc = "Bit 25 - Debug CAN stopped when core is halted"]
178 #[inline(always)]
179 pub fn dbg_can_stop(&self) -> DBG_CAN_STOP_R {
180 DBG_CAN_STOP_R::new(((self.bits >> 25) & 1) != 0)
181 }
182}
183impl W {
184 #[doc = "Bit 0 - Debug Timer 2 stopped when Core is halted"]
185 #[inline(always)]
186 pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<0> {
187 DBG_TIM2_STOP_W::new(self)
188 }
189 #[doc = "Bit 1 - Debug Timer 3 stopped when Core is halted"]
190 #[inline(always)]
191 pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<1> {
192 DBG_TIM3_STOP_W::new(self)
193 }
194 #[doc = "Bit 2 - Debug Timer 4 stopped when Core is halted"]
195 #[inline(always)]
196 pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<2> {
197 DBG_TIM4_STOP_W::new(self)
198 }
199 #[doc = "Bit 3 - Debug Timer 5 stopped when Core is halted"]
200 #[inline(always)]
201 pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<3> {
202 DBG_TIM5_STOP_W::new(self)
203 }
204 #[doc = "Bit 4 - Debug Timer 6 stopped when Core is halted"]
205 #[inline(always)]
206 pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<4> {
207 DBG_TIM6_STOP_W::new(self)
208 }
209 #[doc = "Bit 5 - Debug Timer 7 stopped when Core is halted"]
210 #[inline(always)]
211 pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<5> {
212 DBG_TIM7_STOP_W::new(self)
213 }
214 #[doc = "Bit 6 - Debug Timer 12 stopped when Core is halted"]
215 #[inline(always)]
216 pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<6> {
217 DBG_TIM12_STOP_W::new(self)
218 }
219 #[doc = "Bit 7 - Debug Timer 13 stopped when Core is halted"]
220 #[inline(always)]
221 pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<7> {
222 DBG_TIM13_STOP_W::new(self)
223 }
224 #[doc = "Bit 8 - Debug Timer 14 stopped when Core is halted"]
225 #[inline(always)]
226 pub fn dbg_timer14_stop(&mut self) -> DBG_TIMER14_STOP_W<8> {
227 DBG_TIMER14_STOP_W::new(self)
228 }
229 #[doc = "Bit 9 - Debug Timer 18 stopped when Core is halted"]
230 #[inline(always)]
231 pub fn dbg_tim18_stop(&mut self) -> DBG_TIM18_STOP_W<9> {
232 DBG_TIM18_STOP_W::new(self)
233 }
234 #[doc = "Bit 10 - Debug RTC stopped when Core is halted"]
235 #[inline(always)]
236 pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<10> {
237 DBG_RTC_STOP_W::new(self)
238 }
239 #[doc = "Bit 11 - Debug Window Wachdog stopped when Core is halted"]
240 #[inline(always)]
241 pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<11> {
242 DBG_WWDG_STOP_W::new(self)
243 }
244 #[doc = "Bit 12 - Debug Independent Wachdog stopped when Core is halted"]
245 #[inline(always)]
246 pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<12> {
247 DBG_IWDG_STOP_W::new(self)
248 }
249 #[doc = "Bit 21 - SMBUS timeout mode stopped when Core is halted"]
250 #[inline(always)]
251 pub fn i2c1_smbus_timeout(&mut self) -> I2C1_SMBUS_TIMEOUT_W<21> {
252 I2C1_SMBUS_TIMEOUT_W::new(self)
253 }
254 #[doc = "Bit 22 - SMBUS timeout mode stopped when Core is halted"]
255 #[inline(always)]
256 pub fn i2c2_smbus_timeout(&mut self) -> I2C2_SMBUS_TIMEOUT_W<22> {
257 I2C2_SMBUS_TIMEOUT_W::new(self)
258 }
259 #[doc = "Bit 25 - Debug CAN stopped when core is halted"]
260 #[inline(always)]
261 pub fn dbg_can_stop(&mut self) -> DBG_CAN_STOP_W<25> {
262 DBG_CAN_STOP_W::new(self)
263 }
264 #[doc = "Writes raw bits to the register."]
265 #[inline(always)]
266 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
267 self.0.bits(bits);
268 self
269 }
270}
271#[doc = "APB Low Freeze Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apb1_fz](index.html) module"]
272pub struct APB1_FZ_SPEC;
273impl crate::RegisterSpec for APB1_FZ_SPEC {
274 type Ux = u32;
275}
276#[doc = "`read()` method returns [apb1_fz::R](R) reader structure"]
277impl crate::Readable for APB1_FZ_SPEC {
278 type Reader = R;
279}
280#[doc = "`write(|w| ..)` method takes [apb1_fz::W](W) writer structure"]
281impl crate::Writable for APB1_FZ_SPEC {
282 type Writer = W;
283}
284#[doc = "`reset()` method sets APB1_FZ to value 0"]
285impl crate::Resettable for APB1_FZ_SPEC {
286 #[inline(always)]
287 fn reset_value() -> Self::Ux {
288 0
289 }
290}