stm32f2/stm32f217/dbgmcu/
apb1_fz.rs

1///Register `APB1_FZ` reader
2pub type R = crate::R<APB1_FZrs>;
3///Register `APB1_FZ` writer
4pub type W = crate::W<APB1_FZrs>;
5///Field `DBG_TIM2_STOP` reader - DBG_TIM2_STOP
6pub type DBG_TIM2_STOP_R = crate::BitReader;
7///Field `DBG_TIM2_STOP` writer - DBG_TIM2_STOP
8pub type DBG_TIM2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `DBG_TIM3_STOP` reader - DBG_TIM3 _STOP
10pub type DBG_TIM3_STOP_R = crate::BitReader;
11///Field `DBG_TIM3_STOP` writer - DBG_TIM3 _STOP
12pub type DBG_TIM3_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `DBG_TIM4_STOP` reader - DBG_TIM4_STOP
14pub type DBG_TIM4_STOP_R = crate::BitReader;
15///Field `DBG_TIM4_STOP` writer - DBG_TIM4_STOP
16pub type DBG_TIM4_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `DBG_TIM5_STOP` reader - DBG_TIM5_STOP
18pub type DBG_TIM5_STOP_R = crate::BitReader;
19///Field `DBG_TIM5_STOP` writer - DBG_TIM5_STOP
20pub type DBG_TIM5_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `DBG_TIM6_STOP` reader - DBG_TIM6_STOP
22pub type DBG_TIM6_STOP_R = crate::BitReader;
23///Field `DBG_TIM6_STOP` writer - DBG_TIM6_STOP
24pub type DBG_TIM6_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `DBG_TIM7_STOP` reader - DBG_TIM7_STOP
26pub type DBG_TIM7_STOP_R = crate::BitReader;
27///Field `DBG_TIM7_STOP` writer - DBG_TIM7_STOP
28pub type DBG_TIM7_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `DBG_TIM12_STOP` reader - DBG_TIM12_STOP
30pub type DBG_TIM12_STOP_R = crate::BitReader;
31///Field `DBG_TIM12_STOP` writer - DBG_TIM12_STOP
32pub type DBG_TIM12_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `DBG_TIM13_STOP` reader - DBG_TIM13_STOP
34pub type DBG_TIM13_STOP_R = crate::BitReader;
35///Field `DBG_TIM13_STOP` writer - DBG_TIM13_STOP
36pub type DBG_TIM13_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `DBG_TIM14_STOP` reader - DBG_TIM14_STOP
38pub type DBG_TIM14_STOP_R = crate::BitReader;
39///Field `DBG_TIM14_STOP` writer - DBG_TIM14_STOP
40pub type DBG_TIM14_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `DBG_WWDG_STOP` reader - DBG_WWDG_STOP
42pub type DBG_WWDG_STOP_R = crate::BitReader;
43///Field `DBG_WWDG_STOP` writer - DBG_WWDG_STOP
44pub type DBG_WWDG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `DBG_IWDG_STOP` reader - DBG_IWDEG_STOP
46pub type DBG_IWDG_STOP_R = crate::BitReader;
47///Field `DBG_IWDG_STOP` writer - DBG_IWDEG_STOP
48pub type DBG_IWDG_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `DBG_J2C1_SMBUS_TIMEOUT` reader - DBG_J2C1_SMBUS_TIMEOUT
50pub type DBG_J2C1_SMBUS_TIMEOUT_R = crate::BitReader;
51///Field `DBG_J2C1_SMBUS_TIMEOUT` writer - DBG_J2C1_SMBUS_TIMEOUT
52pub type DBG_J2C1_SMBUS_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `DBG_J2C2_SMBUS_TIMEOUT` reader - DBG_J2C2_SMBUS_TIMEOUT
54pub type DBG_J2C2_SMBUS_TIMEOUT_R = crate::BitReader;
55///Field `DBG_J2C2_SMBUS_TIMEOUT` writer - DBG_J2C2_SMBUS_TIMEOUT
56pub type DBG_J2C2_SMBUS_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
57///Field `DBG_J2C3SMBUS_TIMEOUT` reader - DBG_J2C3SMBUS_TIMEOUT
58pub type DBG_J2C3SMBUS_TIMEOUT_R = crate::BitReader;
59///Field `DBG_J2C3SMBUS_TIMEOUT` writer - DBG_J2C3SMBUS_TIMEOUT
60pub type DBG_J2C3SMBUS_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
61///Field `DBG_CAN1_STOP` reader - DBG_CAN1_STOP
62pub type DBG_CAN1_STOP_R = crate::BitReader;
63///Field `DBG_CAN1_STOP` writer - DBG_CAN1_STOP
64pub type DBG_CAN1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
65///Field `DBG_CAN2_STOP` reader - DBG_CAN2_STOP
66pub type DBG_CAN2_STOP_R = crate::BitReader;
67///Field `DBG_CAN2_STOP` writer - DBG_CAN2_STOP
68pub type DBG_CAN2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
69impl R {
70    ///Bit 0 - DBG_TIM2_STOP
71    #[inline(always)]
72    pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R {
73        DBG_TIM2_STOP_R::new((self.bits & 1) != 0)
74    }
75    ///Bit 1 - DBG_TIM3 _STOP
76    #[inline(always)]
77    pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R {
78        DBG_TIM3_STOP_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    ///Bit 2 - DBG_TIM4_STOP
81    #[inline(always)]
82    pub fn dbg_tim4_stop(&self) -> DBG_TIM4_STOP_R {
83        DBG_TIM4_STOP_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    ///Bit 3 - DBG_TIM5_STOP
86    #[inline(always)]
87    pub fn dbg_tim5_stop(&self) -> DBG_TIM5_STOP_R {
88        DBG_TIM5_STOP_R::new(((self.bits >> 3) & 1) != 0)
89    }
90    ///Bit 4 - DBG_TIM6_STOP
91    #[inline(always)]
92    pub fn dbg_tim6_stop(&self) -> DBG_TIM6_STOP_R {
93        DBG_TIM6_STOP_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    ///Bit 5 - DBG_TIM7_STOP
96    #[inline(always)]
97    pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R {
98        DBG_TIM7_STOP_R::new(((self.bits >> 5) & 1) != 0)
99    }
100    ///Bit 6 - DBG_TIM12_STOP
101    #[inline(always)]
102    pub fn dbg_tim12_stop(&self) -> DBG_TIM12_STOP_R {
103        DBG_TIM12_STOP_R::new(((self.bits >> 6) & 1) != 0)
104    }
105    ///Bit 7 - DBG_TIM13_STOP
106    #[inline(always)]
107    pub fn dbg_tim13_stop(&self) -> DBG_TIM13_STOP_R {
108        DBG_TIM13_STOP_R::new(((self.bits >> 7) & 1) != 0)
109    }
110    ///Bit 8 - DBG_TIM14_STOP
111    #[inline(always)]
112    pub fn dbg_tim14_stop(&self) -> DBG_TIM14_STOP_R {
113        DBG_TIM14_STOP_R::new(((self.bits >> 8) & 1) != 0)
114    }
115    ///Bit 11 - DBG_WWDG_STOP
116    #[inline(always)]
117    pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R {
118        DBG_WWDG_STOP_R::new(((self.bits >> 11) & 1) != 0)
119    }
120    ///Bit 12 - DBG_IWDEG_STOP
121    #[inline(always)]
122    pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R {
123        DBG_IWDG_STOP_R::new(((self.bits >> 12) & 1) != 0)
124    }
125    ///Bit 21 - DBG_J2C1_SMBUS_TIMEOUT
126    #[inline(always)]
127    pub fn dbg_j2c1_smbus_timeout(&self) -> DBG_J2C1_SMBUS_TIMEOUT_R {
128        DBG_J2C1_SMBUS_TIMEOUT_R::new(((self.bits >> 21) & 1) != 0)
129    }
130    ///Bit 22 - DBG_J2C2_SMBUS_TIMEOUT
131    #[inline(always)]
132    pub fn dbg_j2c2_smbus_timeout(&self) -> DBG_J2C2_SMBUS_TIMEOUT_R {
133        DBG_J2C2_SMBUS_TIMEOUT_R::new(((self.bits >> 22) & 1) != 0)
134    }
135    ///Bit 23 - DBG_J2C3SMBUS_TIMEOUT
136    #[inline(always)]
137    pub fn dbg_j2c3smbus_timeout(&self) -> DBG_J2C3SMBUS_TIMEOUT_R {
138        DBG_J2C3SMBUS_TIMEOUT_R::new(((self.bits >> 23) & 1) != 0)
139    }
140    ///Bit 25 - DBG_CAN1_STOP
141    #[inline(always)]
142    pub fn dbg_can1_stop(&self) -> DBG_CAN1_STOP_R {
143        DBG_CAN1_STOP_R::new(((self.bits >> 25) & 1) != 0)
144    }
145    ///Bit 26 - DBG_CAN2_STOP
146    #[inline(always)]
147    pub fn dbg_can2_stop(&self) -> DBG_CAN2_STOP_R {
148        DBG_CAN2_STOP_R::new(((self.bits >> 26) & 1) != 0)
149    }
150}
151impl core::fmt::Debug for R {
152    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
153        f.debug_struct("APB1_FZ")
154            .field("dbg_tim2_stop", &self.dbg_tim2_stop())
155            .field("dbg_tim3_stop", &self.dbg_tim3_stop())
156            .field("dbg_tim4_stop", &self.dbg_tim4_stop())
157            .field("dbg_tim5_stop", &self.dbg_tim5_stop())
158            .field("dbg_tim6_stop", &self.dbg_tim6_stop())
159            .field("dbg_tim7_stop", &self.dbg_tim7_stop())
160            .field("dbg_tim12_stop", &self.dbg_tim12_stop())
161            .field("dbg_tim13_stop", &self.dbg_tim13_stop())
162            .field("dbg_tim14_stop", &self.dbg_tim14_stop())
163            .field("dbg_wwdg_stop", &self.dbg_wwdg_stop())
164            .field("dbg_iwdg_stop", &self.dbg_iwdg_stop())
165            .field("dbg_j2c1_smbus_timeout", &self.dbg_j2c1_smbus_timeout())
166            .field("dbg_j2c2_smbus_timeout", &self.dbg_j2c2_smbus_timeout())
167            .field("dbg_j2c3smbus_timeout", &self.dbg_j2c3smbus_timeout())
168            .field("dbg_can1_stop", &self.dbg_can1_stop())
169            .field("dbg_can2_stop", &self.dbg_can2_stop())
170            .finish()
171    }
172}
173impl W {
174    ///Bit 0 - DBG_TIM2_STOP
175    #[inline(always)]
176    pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<APB1_FZrs> {
177        DBG_TIM2_STOP_W::new(self, 0)
178    }
179    ///Bit 1 - DBG_TIM3 _STOP
180    #[inline(always)]
181    pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<APB1_FZrs> {
182        DBG_TIM3_STOP_W::new(self, 1)
183    }
184    ///Bit 2 - DBG_TIM4_STOP
185    #[inline(always)]
186    pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<APB1_FZrs> {
187        DBG_TIM4_STOP_W::new(self, 2)
188    }
189    ///Bit 3 - DBG_TIM5_STOP
190    #[inline(always)]
191    pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<APB1_FZrs> {
192        DBG_TIM5_STOP_W::new(self, 3)
193    }
194    ///Bit 4 - DBG_TIM6_STOP
195    #[inline(always)]
196    pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<APB1_FZrs> {
197        DBG_TIM6_STOP_W::new(self, 4)
198    }
199    ///Bit 5 - DBG_TIM7_STOP
200    #[inline(always)]
201    pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<APB1_FZrs> {
202        DBG_TIM7_STOP_W::new(self, 5)
203    }
204    ///Bit 6 - DBG_TIM12_STOP
205    #[inline(always)]
206    pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<APB1_FZrs> {
207        DBG_TIM12_STOP_W::new(self, 6)
208    }
209    ///Bit 7 - DBG_TIM13_STOP
210    #[inline(always)]
211    pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<APB1_FZrs> {
212        DBG_TIM13_STOP_W::new(self, 7)
213    }
214    ///Bit 8 - DBG_TIM14_STOP
215    #[inline(always)]
216    pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<APB1_FZrs> {
217        DBG_TIM14_STOP_W::new(self, 8)
218    }
219    ///Bit 11 - DBG_WWDG_STOP
220    #[inline(always)]
221    pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<APB1_FZrs> {
222        DBG_WWDG_STOP_W::new(self, 11)
223    }
224    ///Bit 12 - DBG_IWDEG_STOP
225    #[inline(always)]
226    pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<APB1_FZrs> {
227        DBG_IWDG_STOP_W::new(self, 12)
228    }
229    ///Bit 21 - DBG_J2C1_SMBUS_TIMEOUT
230    #[inline(always)]
231    pub fn dbg_j2c1_smbus_timeout(&mut self) -> DBG_J2C1_SMBUS_TIMEOUT_W<APB1_FZrs> {
232        DBG_J2C1_SMBUS_TIMEOUT_W::new(self, 21)
233    }
234    ///Bit 22 - DBG_J2C2_SMBUS_TIMEOUT
235    #[inline(always)]
236    pub fn dbg_j2c2_smbus_timeout(&mut self) -> DBG_J2C2_SMBUS_TIMEOUT_W<APB1_FZrs> {
237        DBG_J2C2_SMBUS_TIMEOUT_W::new(self, 22)
238    }
239    ///Bit 23 - DBG_J2C3SMBUS_TIMEOUT
240    #[inline(always)]
241    pub fn dbg_j2c3smbus_timeout(&mut self) -> DBG_J2C3SMBUS_TIMEOUT_W<APB1_FZrs> {
242        DBG_J2C3SMBUS_TIMEOUT_W::new(self, 23)
243    }
244    ///Bit 25 - DBG_CAN1_STOP
245    #[inline(always)]
246    pub fn dbg_can1_stop(&mut self) -> DBG_CAN1_STOP_W<APB1_FZrs> {
247        DBG_CAN1_STOP_W::new(self, 25)
248    }
249    ///Bit 26 - DBG_CAN2_STOP
250    #[inline(always)]
251    pub fn dbg_can2_stop(&mut self) -> DBG_CAN2_STOP_W<APB1_FZrs> {
252        DBG_CAN2_STOP_W::new(self, 26)
253    }
254}
255/**Debug MCU APB1 Freeze registe
256
257You can [`read`](crate::Reg::read) this register and get [`apb1_fz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1_fz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
258
259See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F217.html#DBGMCU:APB1_FZ)*/
260pub struct APB1_FZrs;
261impl crate::RegisterSpec for APB1_FZrs {
262    type Ux = u32;
263}
264///`read()` method returns [`apb1_fz::R`](R) reader structure
265impl crate::Readable for APB1_FZrs {}
266///`write(|w| ..)` method takes [`apb1_fz::W`](W) writer structure
267impl crate::Writable for APB1_FZrs {
268    type Safety = crate::Unsafe;
269}
270///`reset()` method sets APB1_FZ to value 0
271impl crate::Resettable for APB1_FZrs {}
stm32f2/stm32f217/dbgmcu/apb1_fz.rs

stm32f2/stm32f217/dbgmcu/
apb1_fz.rs
