stm32f2/stm32f215/rcc/
ahb3enr.rs

1///Register `AHB3ENR` reader
2pub type R = crate::R<AHB3ENRrs>;
3///Register `AHB3ENR` writer
4pub type W = crate::W<AHB3ENRrs>;
5/**Flexible static memory controller module clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum FSMCEN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<FSMCEN> for bool {
17    #[inline(always)]
18    fn from(variant: FSMCEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `FSMCEN` reader - Flexible static memory controller module clock enable
23pub type FSMCEN_R = crate::BitReader<FSMCEN>;
24impl FSMCEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> FSMCEN {
28        match self.bits {
29            false => FSMCEN::Disabled,
30            true => FSMCEN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == FSMCEN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == FSMCEN::Enabled
42    }
43}
44///Field `FSMCEN` writer - Flexible static memory controller module clock enable
45pub type FSMCEN_W<'a, REG> = crate::BitWriter<'a, REG, FSMCEN>;
46impl<'a, REG> FSMCEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(FSMCEN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(FSMCEN::Enabled)
59    }
60}
61impl R {
62    ///Bit 0 - Flexible static memory controller module clock enable
63    #[inline(always)]
64    pub fn fsmcen(&self) -> FSMCEN_R {
65        FSMCEN_R::new((self.bits & 1) != 0)
66    }
67}
68impl core::fmt::Debug for R {
69    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
70        f.debug_struct("AHB3ENR")
71            .field("fsmcen", &self.fsmcen())
72            .finish()
73    }
74}
75impl W {
76    ///Bit 0 - Flexible static memory controller module clock enable
77    #[inline(always)]
78    pub fn fsmcen(&mut self) -> FSMCEN_W<AHB3ENRrs> {
79        FSMCEN_W::new(self, 0)
80    }
81}
82/**AHB3 peripheral clock enable register
83
84You can [`read`](crate::Reg::read) this register and get [`ahb3enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb3enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
85
86See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#RCC:AHB3ENR)*/
87pub struct AHB3ENRrs;
88impl crate::RegisterSpec for AHB3ENRrs {
89    type Ux = u32;
90}
91///`read()` method returns [`ahb3enr::R`](R) reader structure
92impl crate::Readable for AHB3ENRrs {}
93///`write(|w| ..)` method takes [`ahb3enr::W`](W) writer structure
94impl crate::Writable for AHB3ENRrs {
95    type Safety = crate::Unsafe;
96}
97///`reset()` method sets AHB3ENR to value 0
98impl crate::Resettable for AHB3ENRrs {}
stm32f2/stm32f215/rcc/ahb3enr.rs

stm32f2/stm32f215/rcc/
ahb3enr.rs
