stm32f2/stm32f215/
mod.rs

1/*!Peripheral access API for STM32F215 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn WWDG();
21    fn PVD();
22    fn TAMP_STAMP();
23    fn RTC_WKUP();
24    fn FLASH();
25    fn RCC();
26    fn EXTI0();
27    fn EXTI1();
28    fn EXTI2();
29    fn EXTI3();
30    fn EXTI4();
31    fn DMA1_STREAM0();
32    fn DMA1_STREAM1();
33    fn DMA1_STREAM2();
34    fn DMA1_STREAM3();
35    fn DMA1_STREAM4();
36    fn DMA1_STREAM5();
37    fn DMA1_STREAM6();
38    fn ADC();
39    fn CAN1_TX();
40    fn CAN1_RX0();
41    fn CAN1_RX1();
42    fn CAN1_SCE();
43    fn EXTI9_5();
44    fn TIM1_BRK_TIM9();
45    fn TIM1_UP_TIM10();
46    fn TIM1_TRG_COM_TIM11();
47    fn TIM1_CC();
48    fn TIM2();
49    fn TIM3();
50    fn TIM4();
51    fn I2C1_EV();
52    fn I2C1_ER();
53    fn I2C2_EV();
54    fn I2C2_ER();
55    fn SPI1();
56    fn SPI2();
57    fn USART1();
58    fn USART2();
59    fn USART3();
60    fn EXTI15_10();
61    fn RTC_ALARM();
62    fn OTG_FS_WKUP();
63    fn TIM8_BRK_TIM12();
64    fn TIM8_UP_TIM13();
65    fn TIM8_TRG_COM_TIM14();
66    fn TIM8_CC();
67    fn DMA1_STREAM7();
68    fn FSMC();
69    fn SDIO();
70    fn TIM5();
71    fn SPI3();
72    fn UART4();
73    fn UART5();
74    fn TIM6_DAC();
75    fn TIM7();
76    fn DMA2_STREAM0();
77    fn DMA2_STREAM1();
78    fn DMA2_STREAM2();
79    fn DMA2_STREAM3();
80    fn DMA2_STREAM4();
81    fn ETH();
82    fn ETH_WKUP();
83    fn CAN2_TX();
84    fn CAN2_RX0();
85    fn CAN2_RX1();
86    fn CAN2_SCE();
87    fn OTG_FS();
88    fn DMA2_STREAM5();
89    fn DMA2_STREAM6();
90    fn DMA2_STREAM7();
91    fn USART6();
92    fn I2C3_EV();
93    fn I2C3_ER();
94    fn OTG_HS_EP1_OUT();
95    fn OTG_HS_EP1_IN();
96    fn OTG_HS_WKUP();
97    fn OTG_HS();
98    fn DCMI();
99    fn CRYP();
100    fn HASH_RNG();
101}
102#[doc(hidden)]
103#[repr(C)]
104pub union Vector {
105    _handler: unsafe extern "C" fn(),
106    _reserved: u32,
107}
108#[cfg(feature = "rt")]
109#[doc(hidden)]
110#[link_section = ".vector_table.interrupts"]
111#[no_mangle]
112pub static __INTERRUPTS: [Vector; 81] = [
113    Vector { _handler: WWDG },
114    Vector { _handler: PVD },
115    Vector {
116        _handler: TAMP_STAMP,
117    },
118    Vector { _handler: RTC_WKUP },
119    Vector { _handler: FLASH },
120    Vector { _handler: RCC },
121    Vector { _handler: EXTI0 },
122    Vector { _handler: EXTI1 },
123    Vector { _handler: EXTI2 },
124    Vector { _handler: EXTI3 },
125    Vector { _handler: EXTI4 },
126    Vector {
127        _handler: DMA1_STREAM0,
128    },
129    Vector {
130        _handler: DMA1_STREAM1,
131    },
132    Vector {
133        _handler: DMA1_STREAM2,
134    },
135    Vector {
136        _handler: DMA1_STREAM3,
137    },
138    Vector {
139        _handler: DMA1_STREAM4,
140    },
141    Vector {
142        _handler: DMA1_STREAM5,
143    },
144    Vector {
145        _handler: DMA1_STREAM6,
146    },
147    Vector { _handler: ADC },
148    Vector { _handler: CAN1_TX },
149    Vector { _handler: CAN1_RX0 },
150    Vector { _handler: CAN1_RX1 },
151    Vector { _handler: CAN1_SCE },
152    Vector { _handler: EXTI9_5 },
153    Vector {
154        _handler: TIM1_BRK_TIM9,
155    },
156    Vector {
157        _handler: TIM1_UP_TIM10,
158    },
159    Vector {
160        _handler: TIM1_TRG_COM_TIM11,
161    },
162    Vector { _handler: TIM1_CC },
163    Vector { _handler: TIM2 },
164    Vector { _handler: TIM3 },
165    Vector { _handler: TIM4 },
166    Vector { _handler: I2C1_EV },
167    Vector { _handler: I2C1_ER },
168    Vector { _handler: I2C2_EV },
169    Vector { _handler: I2C2_ER },
170    Vector { _handler: SPI1 },
171    Vector { _handler: SPI2 },
172    Vector { _handler: USART1 },
173    Vector { _handler: USART2 },
174    Vector { _handler: USART3 },
175    Vector {
176        _handler: EXTI15_10,
177    },
178    Vector {
179        _handler: RTC_ALARM,
180    },
181    Vector {
182        _handler: OTG_FS_WKUP,
183    },
184    Vector {
185        _handler: TIM8_BRK_TIM12,
186    },
187    Vector {
188        _handler: TIM8_UP_TIM13,
189    },
190    Vector {
191        _handler: TIM8_TRG_COM_TIM14,
192    },
193    Vector { _handler: TIM8_CC },
194    Vector {
195        _handler: DMA1_STREAM7,
196    },
197    Vector { _handler: FSMC },
198    Vector { _handler: SDIO },
199    Vector { _handler: TIM5 },
200    Vector { _handler: SPI3 },
201    Vector { _handler: UART4 },
202    Vector { _handler: UART5 },
203    Vector { _handler: TIM6_DAC },
204    Vector { _handler: TIM7 },
205    Vector {
206        _handler: DMA2_STREAM0,
207    },
208    Vector {
209        _handler: DMA2_STREAM1,
210    },
211    Vector {
212        _handler: DMA2_STREAM2,
213    },
214    Vector {
215        _handler: DMA2_STREAM3,
216    },
217    Vector {
218        _handler: DMA2_STREAM4,
219    },
220    Vector { _handler: ETH },
221    Vector { _handler: ETH_WKUP },
222    Vector { _handler: CAN2_TX },
223    Vector { _handler: CAN2_RX0 },
224    Vector { _handler: CAN2_RX1 },
225    Vector { _handler: CAN2_SCE },
226    Vector { _handler: OTG_FS },
227    Vector {
228        _handler: DMA2_STREAM5,
229    },
230    Vector {
231        _handler: DMA2_STREAM6,
232    },
233    Vector {
234        _handler: DMA2_STREAM7,
235    },
236    Vector { _handler: USART6 },
237    Vector { _handler: I2C3_EV },
238    Vector { _handler: I2C3_ER },
239    Vector {
240        _handler: OTG_HS_EP1_OUT,
241    },
242    Vector {
243        _handler: OTG_HS_EP1_IN,
244    },
245    Vector {
246        _handler: OTG_HS_WKUP,
247    },
248    Vector { _handler: OTG_HS },
249    Vector { _handler: DCMI },
250    Vector { _handler: CRYP },
251    Vector { _handler: HASH_RNG },
252];
253///Enumeration of all the interrupts.
254#[cfg_attr(feature = "defmt", derive(defmt::Format))]
255#[derive(Copy, Clone, Debug, PartialEq, Eq)]
256#[repr(u16)]
257pub enum Interrupt {
258    ///0 - Window Watchdog interrupt
259    WWDG = 0,
260    ///1 - PVD through EXTI line detection interrupt
261    PVD = 1,
262    ///2 - Tamper and TimeStamp interrupts through the EXTI line
263    TAMP_STAMP = 2,
264    ///3 - RTC Wakeup interrupt through the EXTI line
265    RTC_WKUP = 3,
266    ///4 - FlASH global interrupt
267    FLASH = 4,
268    ///5 - RCC global interrupt
269    RCC = 5,
270    ///6 - EXTI Line0 interrupt
271    EXTI0 = 6,
272    ///7 - EXTI Line1 interrupt
273    EXTI1 = 7,
274    ///8 - EXTI Line2 interrupt
275    EXTI2 = 8,
276    ///9 - EXTI Line3 interrupt
277    EXTI3 = 9,
278    ///10 - EXTI Line4 interrupt
279    EXTI4 = 10,
280    ///11 - DMA1 Stream0 global interrupt
281    DMA1_STREAM0 = 11,
282    ///12 - DMA1 Stream1 global interrupt
283    DMA1_STREAM1 = 12,
284    ///13 - DMA1 Stream2 global interrupt
285    DMA1_STREAM2 = 13,
286    ///14 - DMA1 Stream3 global interrupt
287    DMA1_STREAM3 = 14,
288    ///15 - DMA1 Stream4 global interrupt
289    DMA1_STREAM4 = 15,
290    ///16 - DMA1 Stream5 global interrupt
291    DMA1_STREAM5 = 16,
292    ///17 - DMA1 Stream6 global interrupt
293    DMA1_STREAM6 = 17,
294    ///18 - ADC3 global interrupts
295    ADC = 18,
296    ///19 - CAN1 TX interrupts
297    CAN1_TX = 19,
298    ///20 - CAN1 RX0 interrupts
299    CAN1_RX0 = 20,
300    ///21 - CAN1 RX1 interrupts
301    CAN1_RX1 = 21,
302    ///22 - CAN1 SCE interrupt
303    CAN1_SCE = 22,
304    ///23 - EXTI Line\[9:5\] interrupts
305    EXTI9_5 = 23,
306    ///24 - TIM1 Break interrupt and TIM9 global interrupt
307    TIM1_BRK_TIM9 = 24,
308    ///25 - TIM1 Update interrupt and TIM10 global interrupt
309    TIM1_UP_TIM10 = 25,
310    ///26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
311    TIM1_TRG_COM_TIM11 = 26,
312    ///27 - TIM1 Capture Compare interrupt
313    TIM1_CC = 27,
314    ///28 - TIM2 global interrupt
315    TIM2 = 28,
316    ///29 - TIM3 global interrupt
317    TIM3 = 29,
318    ///30 - TIM4 global interrupt
319    TIM4 = 30,
320    ///31 - I2C1 event interrupt
321    I2C1_EV = 31,
322    ///32 - I2C1 error interrupt
323    I2C1_ER = 32,
324    ///33 - I2C2 event interrupt
325    I2C2_EV = 33,
326    ///34 - I2C2 error interrupt
327    I2C2_ER = 34,
328    ///35 - SPI1 global interrupt
329    SPI1 = 35,
330    ///36 - SPI2 global interrupt
331    SPI2 = 36,
332    ///37 - USART1 global interrupt
333    USART1 = 37,
334    ///38 - USART2 global interrupt
335    USART2 = 38,
336    ///39 - USART3 global interrupt
337    USART3 = 39,
338    ///40 - EXTI Line\[15:10\] interrupts
339    EXTI15_10 = 40,
340    ///41 - RTC Alarms (A and B) through EXTI line interrupt
341    RTC_ALARM = 41,
342    ///42 - USB On-The-Go FS Wakeup through EXTI line interrupt
343    OTG_FS_WKUP = 42,
344    ///43 - TIM8 Break interrupt and TIM12 global interrupt
345    TIM8_BRK_TIM12 = 43,
346    ///44 - TIM8 Update interrupt and TIM13 global interrupt
347    TIM8_UP_TIM13 = 44,
348    ///45 - TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
349    TIM8_TRG_COM_TIM14 = 45,
350    ///46 - TIM8 Capture Compare interrupt
351    TIM8_CC = 46,
352    ///47 - DMA1 Stream7 global interrupt
353    DMA1_STREAM7 = 47,
354    ///48 - FSMC global interrupt
355    FSMC = 48,
356    ///49 - SDIO global interrupt
357    SDIO = 49,
358    ///50 - TIM5 global interrupt
359    TIM5 = 50,
360    ///51 - SPI3 global interrupt
361    SPI3 = 51,
362    ///52 - UART4 global interrupt
363    UART4 = 52,
364    ///53 - UART5 global interrupt
365    UART5 = 53,
366    ///54 - TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
367    TIM6_DAC = 54,
368    ///55 - TIM7 global interrupt
369    TIM7 = 55,
370    ///56 - DMA2 Stream0 global interrupt
371    DMA2_STREAM0 = 56,
372    ///57 - DMA2 Stream1 global interrupt
373    DMA2_STREAM1 = 57,
374    ///58 - DMA2 Stream2 global interrupt
375    DMA2_STREAM2 = 58,
376    ///59 - DMA2 Stream3 global interrupt
377    DMA2_STREAM3 = 59,
378    ///60 - DMA2 Stream4 global interrupt
379    DMA2_STREAM4 = 60,
380    ///61 - Ethernet global interrupt
381    ETH = 61,
382    ///62 - Ethernet Wakeup through EXTI line interrupt
383    ETH_WKUP = 62,
384    ///63 - CAN2 TX interrupts
385    CAN2_TX = 63,
386    ///64 - CAN2 RX0 interrupts
387    CAN2_RX0 = 64,
388    ///65 - CAN2 RX1 interrupts
389    CAN2_RX1 = 65,
390    ///66 - CAN2 SCE interrupt
391    CAN2_SCE = 66,
392    ///67 - USB On The Go FS global interrupt
393    OTG_FS = 67,
394    ///68 - DMA2 Stream5 global interrupt
395    DMA2_STREAM5 = 68,
396    ///69 - DMA2 Stream6 global interrupt
397    DMA2_STREAM6 = 69,
398    ///70 - DMA2 Stream7 global interrupt
399    DMA2_STREAM7 = 70,
400    ///71 - USART6 global interrupt
401    USART6 = 71,
402    ///72 - I2C3 event interrupt
403    I2C3_EV = 72,
404    ///73 - I2C3 error interrupt
405    I2C3_ER = 73,
406    ///74 - USB On The Go HS End Point 1 Out global interrupt
407    OTG_HS_EP1_OUT = 74,
408    ///75 - USB On The Go HS End Point 1 In global interrupt
409    OTG_HS_EP1_IN = 75,
410    ///76 - USB On The Go HS Wakeup through EXTI interrupt
411    OTG_HS_WKUP = 76,
412    ///77 - USB On The Go HS global interrupt
413    OTG_HS = 77,
414    ///78 - DCMI global interrupt
415    DCMI = 78,
416    ///79 - CRYP crypto global interrupt
417    CRYP = 79,
418    ///80 - Hash and Rng global interrupt
419    HASH_RNG = 80,
420}
421unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
422    #[inline(always)]
423    fn number(self) -> u16 {
424        self as u16
425    }
426}
427///Random number generator
428///
429///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#RNG)
430pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
431impl core::fmt::Debug for RNG {
432    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
433        f.debug_struct("RNG").finish()
434    }
435}
436///Random number generator
437pub mod rng;
438///cyclic redundancy check calculation unit
439///
440///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#CRC)
441pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
442impl core::fmt::Debug for CRC {
443    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
444        f.debug_struct("CRC").finish()
445    }
446}
447///cyclic redundancy check calculation unit
448pub mod crc;
449///Digital camera interface
450///
451///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#DCMI)
452pub type DCMI = crate::Periph<dcmi::RegisterBlock, 0x5005_0000>;
453impl core::fmt::Debug for DCMI {
454    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
455        f.debug_struct("DCMI").finish()
456    }
457}
458///Digital camera interface
459pub mod dcmi;
460///Flexible static memory controller
461///
462///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#FSMC)
463pub type FSMC = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
464impl core::fmt::Debug for FSMC {
465    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
466        f.debug_struct("FSMC").finish()
467    }
468}
469///Flexible static memory controller
470pub mod fsmc;
471///Debug support
472///
473///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#DBGMCU)
474pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
475impl core::fmt::Debug for DBGMCU {
476    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
477        f.debug_struct("DBGMCU").finish()
478    }
479}
480///Debug support
481pub mod dbgmcu;
482///DMA controller
483///
484///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#DMA2)
485pub type DMA2 = crate::Periph<dma2::RegisterBlock, 0x4002_6400>;
486impl core::fmt::Debug for DMA2 {
487    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
488        f.debug_struct("DMA2").finish()
489    }
490}
491///DMA controller
492pub mod dma2;
493///DMA controller
494///
495///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#DMA2)
496pub type DMA1 = crate::Periph<dma2::RegisterBlock, 0x4002_6000>;
497impl core::fmt::Debug for DMA1 {
498    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
499        f.debug_struct("DMA1").finish()
500    }
501}
502///DMA controller
503pub use self::dma2 as dma1;
504///Reset and clock control
505///
506///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#RCC)
507pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_3800>;
508impl core::fmt::Debug for RCC {
509    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
510        f.debug_struct("RCC").finish()
511    }
512}
513///Reset and clock control
514pub mod rcc;
515///General-purpose I/Os
516///
517///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#GPIOI)
518pub type GPIOI = crate::Periph<gpioi::RegisterBlock, 0x4002_2000>;
519impl core::fmt::Debug for GPIOI {
520    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
521        f.debug_struct("GPIOI").finish()
522    }
523}
524///General-purpose I/Os
525pub mod gpioi;
526///General-purpose I/Os
527///
528///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#GPIOI)
529pub type GPIOH = crate::Periph<gpioi::RegisterBlock, 0x4002_1c00>;
530impl core::fmt::Debug for GPIOH {
531    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
532        f.debug_struct("GPIOH").finish()
533    }
534}
535///General-purpose I/Os
536pub use self::gpioi as gpioh;
537///General-purpose I/Os
538///
539///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#GPIOI)
540pub type GPIOG = crate::Periph<gpioi::RegisterBlock, 0x4002_1800>;
541impl core::fmt::Debug for GPIOG {
542    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
543        f.debug_struct("GPIOG").finish()
544    }
545}
546///General-purpose I/Os
547pub use self::gpioi as gpiog;
548///General-purpose I/Os
549///
550///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#GPIOI)
551pub type GPIOF = crate::Periph<gpioi::RegisterBlock, 0x4002_1400>;
552impl core::fmt::Debug for GPIOF {
553    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
554        f.debug_struct("GPIOF").finish()
555    }
556}
557///General-purpose I/Os
558pub use self::gpioi as gpiof;
559///General-purpose I/Os
560///
561///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#GPIOI)
562pub type GPIOE = crate::Periph<gpioi::RegisterBlock, 0x4002_1000>;
563impl core::fmt::Debug for GPIOE {
564    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
565        f.debug_struct("GPIOE").finish()
566    }
567}
568///General-purpose I/Os
569pub use self::gpioi as gpioe;
570///General-purpose I/Os
571///
572///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#GPIOI)
573pub type GPIOD = crate::Periph<gpioi::RegisterBlock, 0x4002_0c00>;
574impl core::fmt::Debug for GPIOD {
575    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
576        f.debug_struct("GPIOD").finish()
577    }
578}
579///General-purpose I/Os
580pub use self::gpioi as gpiod;
581///General-purpose I/Os
582///
583///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#GPIOI)
584pub type GPIOC = crate::Periph<gpioi::RegisterBlock, 0x4002_0800>;
585impl core::fmt::Debug for GPIOC {
586    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
587        f.debug_struct("GPIOC").finish()
588    }
589}
590///General-purpose I/Os
591pub use self::gpioi as gpioc;
592///General-purpose I/Os
593///
594///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#GPIOB)
595pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4002_0400>;
596impl core::fmt::Debug for GPIOB {
597    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
598        f.debug_struct("GPIOB").finish()
599    }
600}
601///General-purpose I/Os
602pub mod gpiob;
603///General-purpose I/Os
604///
605///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#GPIOA)
606pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4002_0000>;
607impl core::fmt::Debug for GPIOA {
608    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
609        f.debug_struct("GPIOA").finish()
610    }
611}
612///General-purpose I/Os
613pub mod gpioa;
614///System configuration controller
615///
616///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#SYSCFG)
617pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_3800>;
618impl core::fmt::Debug for SYSCFG {
619    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
620        f.debug_struct("SYSCFG").finish()
621    }
622}
623///System configuration controller
624pub mod syscfg;
625///Serial peripheral interface
626///
627///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#SPI1)
628pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
629impl core::fmt::Debug for SPI1 {
630    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
631        f.debug_struct("SPI1").finish()
632    }
633}
634///Serial peripheral interface
635pub mod spi1;
636///Serial peripheral interface
637///
638///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#SPI1)
639pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
640impl core::fmt::Debug for SPI3 {
641    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
642        f.debug_struct("SPI3").finish()
643    }
644}
645///Serial peripheral interface
646pub use self::spi1 as spi3;
647///Serial peripheral interface
648///
649///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#SPI1)
650pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
651impl core::fmt::Debug for SPI2 {
652    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
653        f.debug_struct("SPI2").finish()
654    }
655}
656///Serial peripheral interface
657pub use self::spi1 as spi2;
658///Secure digital input/output interface
659///
660///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#SDIO)
661pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_2c00>;
662impl core::fmt::Debug for SDIO {
663    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
664        f.debug_struct("SDIO").finish()
665    }
666}
667///Secure digital input/output interface
668pub mod sdio;
669///Analog-to-digital converter
670///
671///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#ADC1)
672pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2000>;
673impl core::fmt::Debug for ADC1 {
674    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
675        f.debug_struct("ADC1").finish()
676    }
677}
678///Analog-to-digital converter
679pub mod adc1;
680///Analog-to-digital converter
681///
682///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#ADC1)
683pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x4001_2100>;
684impl core::fmt::Debug for ADC2 {
685    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
686        f.debug_struct("ADC2").finish()
687    }
688}
689///Analog-to-digital converter
690pub use self::adc1 as adc2;
691///Analog-to-digital converter
692///
693///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#ADC1)
694pub type ADC3 = crate::Periph<adc1::RegisterBlock, 0x4001_2200>;
695impl core::fmt::Debug for ADC3 {
696    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
697        f.debug_struct("ADC3").finish()
698    }
699}
700///Analog-to-digital converter
701pub use self::adc1 as adc3;
702///Universal synchronous asynchronous receiver transmitter
703///
704///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#USART1)
705pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_1000>;
706impl core::fmt::Debug for USART1 {
707    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
708        f.debug_struct("USART1").finish()
709    }
710}
711///Universal synchronous asynchronous receiver transmitter
712pub mod usart1;
713///Universal synchronous asynchronous receiver transmitter
714///
715///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#USART1)
716pub type USART6 = crate::Periph<usart1::RegisterBlock, 0x4001_1400>;
717impl core::fmt::Debug for USART6 {
718    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
719        f.debug_struct("USART6").finish()
720    }
721}
722///Universal synchronous asynchronous receiver transmitter
723pub use self::usart1 as usart6;
724///Universal synchronous asynchronous receiver transmitter
725///
726///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#USART1)
727pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
728impl core::fmt::Debug for USART2 {
729    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
730        f.debug_struct("USART2").finish()
731    }
732}
733///Universal synchronous asynchronous receiver transmitter
734pub use self::usart1 as usart2;
735///Universal synchronous asynchronous receiver transmitter
736///
737///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#USART1)
738pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
739impl core::fmt::Debug for USART3 {
740    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
741        f.debug_struct("USART3").finish()
742    }
743}
744///Universal synchronous asynchronous receiver transmitter
745pub use self::usart1 as usart3;
746///Digital-to-analog converter
747///
748///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#DAC)
749pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
750impl core::fmt::Debug for DAC {
751    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
752        f.debug_struct("DAC").finish()
753    }
754}
755///Digital-to-analog converter
756pub mod dac;
757///Power control
758///
759///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#PWR)
760pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
761impl core::fmt::Debug for PWR {
762    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
763        f.debug_struct("PWR").finish()
764    }
765}
766///Power control
767pub mod pwr;
768///Controller area network
769///
770///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#CAN2)
771pub type CAN2 = crate::Periph<can2::RegisterBlock, 0x4000_6800>;
772impl core::fmt::Debug for CAN2 {
773    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
774        f.debug_struct("CAN2").finish()
775    }
776}
777///Controller area network
778pub mod can2;
779///Controller area network
780///
781///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#CAN2)
782pub type CAN1 = crate::Periph<can2::RegisterBlock, 0x4000_6400>;
783impl core::fmt::Debug for CAN1 {
784    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
785        f.debug_struct("CAN1").finish()
786    }
787}
788///Controller area network
789pub use self::can2 as can1;
790///Inter-integrated circuit
791///
792///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#I2C1)
793pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
794impl core::fmt::Debug for I2C1 {
795    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
796        f.debug_struct("I2C1").finish()
797    }
798}
799///Inter-integrated circuit
800pub mod i2c1;
801///Inter-integrated circuit
802///
803///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#I2C1)
804pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
805impl core::fmt::Debug for I2C3 {
806    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
807        f.debug_struct("I2C3").finish()
808    }
809}
810///Inter-integrated circuit
811pub use self::i2c1 as i2c3;
812///Inter-integrated circuit
813///
814///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#I2C1)
815pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
816impl core::fmt::Debug for I2C2 {
817    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
818        f.debug_struct("I2C2").finish()
819    }
820}
821///Inter-integrated circuit
822pub use self::i2c1 as i2c2;
823///Independent watchdog
824///
825///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#IWDG)
826pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
827impl core::fmt::Debug for IWDG {
828    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
829        f.debug_struct("IWDG").finish()
830    }
831}
832///Independent watchdog
833pub mod iwdg;
834///Window watchdog
835///
836///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#WWDG)
837pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
838impl core::fmt::Debug for WWDG {
839    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
840        f.debug_struct("WWDG").finish()
841    }
842}
843///Window watchdog
844pub mod wwdg;
845///Real-time clock
846///
847///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#RTC)
848pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
849impl core::fmt::Debug for RTC {
850    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
851        f.debug_struct("RTC").finish()
852    }
853}
854///Real-time clock
855pub mod rtc;
856///Universal synchronous asynchronous receiver transmitter
857///
858///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#UART4)
859pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
860impl core::fmt::Debug for UART4 {
861    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
862        f.debug_struct("UART4").finish()
863    }
864}
865///Universal synchronous asynchronous receiver transmitter
866pub mod uart4;
867///Universal synchronous asynchronous receiver transmitter
868///
869///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#UART4)
870pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
871impl core::fmt::Debug for UART5 {
872    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
873        f.debug_struct("UART5").finish()
874    }
875}
876///Universal synchronous asynchronous receiver transmitter
877pub use self::uart4 as uart5;
878///Common ADC registers
879///
880///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#ADC_Common)
881pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4001_2300>;
882impl core::fmt::Debug for ADC_COMMON {
883    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
884        f.debug_struct("ADC_COMMON").finish()
885    }
886}
887///Common ADC registers
888pub mod adc_common;
889///Advanced-timers
890///
891///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM1)
892pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_0000>;
893impl core::fmt::Debug for TIM1 {
894    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
895        f.debug_struct("TIM1").finish()
896    }
897}
898///Advanced-timers
899pub mod tim1;
900///Advanced-timers
901///
902///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM1)
903pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_0400>;
904impl core::fmt::Debug for TIM8 {
905    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
906        f.debug_struct("TIM8").finish()
907    }
908}
909///Advanced-timers
910pub use self::tim1 as tim8;
911///General-purpose-timers
912///
913///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM2)
914pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
915impl core::fmt::Debug for TIM2 {
916    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
917        f.debug_struct("TIM2").finish()
918    }
919}
920///General-purpose-timers
921pub mod tim2;
922///General-purpose-timers
923///
924///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM3)
925pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
926impl core::fmt::Debug for TIM3 {
927    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
928        f.debug_struct("TIM3").finish()
929    }
930}
931///General-purpose-timers
932pub mod tim3;
933///General-purpose-timers
934///
935///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM3)
936pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
937impl core::fmt::Debug for TIM4 {
938    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
939        f.debug_struct("TIM4").finish()
940    }
941}
942///General-purpose-timers
943pub use self::tim3 as tim4;
944///General-purpose-timers
945///
946///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM5)
947pub type TIM5 = crate::Periph<tim5::RegisterBlock, 0x4000_0c00>;
948impl core::fmt::Debug for TIM5 {
949    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
950        f.debug_struct("TIM5").finish()
951    }
952}
953///General-purpose-timers
954pub mod tim5;
955///General-purpose-timers
956///
957///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM9)
958pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4000>;
959impl core::fmt::Debug for TIM9 {
960    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
961        f.debug_struct("TIM9").finish()
962    }
963}
964///General-purpose-timers
965pub mod tim9;
966///General-purpose-timers
967///
968///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM9)
969pub type TIM12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
970impl core::fmt::Debug for TIM12 {
971    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
972        f.debug_struct("TIM12").finish()
973    }
974}
975///General-purpose-timers
976pub use self::tim9 as tim12;
977///General-purpose-timers
978///
979///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM10)
980pub type TIM10 = crate::Periph<tim10::RegisterBlock, 0x4001_4400>;
981impl core::fmt::Debug for TIM10 {
982    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
983        f.debug_struct("TIM10").finish()
984    }
985}
986///General-purpose-timers
987pub mod tim10;
988///General-purpose-timers
989///
990///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM10)
991pub type TIM11 = crate::Periph<tim10::RegisterBlock, 0x4001_4800>;
992impl core::fmt::Debug for TIM11 {
993    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
994        f.debug_struct("TIM11").finish()
995    }
996}
997///General-purpose-timers
998pub use self::tim10 as tim11;
999///General-purpose-timers
1000///
1001///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM10)
1002pub type TIM13 = crate::Periph<tim10::RegisterBlock, 0x4000_1c00>;
1003impl core::fmt::Debug for TIM13 {
1004    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1005        f.debug_struct("TIM13").finish()
1006    }
1007}
1008///General-purpose-timers
1009pub use self::tim10 as tim13;
1010///General-purpose-timers
1011///
1012///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM10)
1013pub type TIM14 = crate::Periph<tim10::RegisterBlock, 0x4000_2000>;
1014impl core::fmt::Debug for TIM14 {
1015    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1016        f.debug_struct("TIM14").finish()
1017    }
1018}
1019///General-purpose-timers
1020pub use self::tim10 as tim14;
1021///Basic-timers
1022///
1023///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM6)
1024pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
1025impl core::fmt::Debug for TIM6 {
1026    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1027        f.debug_struct("TIM6").finish()
1028    }
1029}
1030///Basic-timers
1031pub mod tim6;
1032///Basic-timers
1033///
1034///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#TIM6)
1035pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
1036impl core::fmt::Debug for TIM7 {
1037    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1038        f.debug_struct("TIM7").finish()
1039    }
1040}
1041///Basic-timers
1042pub use self::tim6 as tim7;
1043///Ethernet: media access control (MAC)
1044///
1045///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#Ethernet_MAC)
1046pub type ETHERNET_MAC = crate::Periph<ethernet_mac::RegisterBlock, 0x4002_8000>;
1047impl core::fmt::Debug for ETHERNET_MAC {
1048    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1049        f.debug_struct("ETHERNET_MAC").finish()
1050    }
1051}
1052///Ethernet: media access control (MAC)
1053pub mod ethernet_mac;
1054///Ethernet: MAC management counters
1055///
1056///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#Ethernet_MMC)
1057pub type ETHERNET_MMC = crate::Periph<ethernet_mmc::RegisterBlock, 0x4002_8100>;
1058impl core::fmt::Debug for ETHERNET_MMC {
1059    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1060        f.debug_struct("ETHERNET_MMC").finish()
1061    }
1062}
1063///Ethernet: MAC management counters
1064pub mod ethernet_mmc;
1065///Ethernet: Precision time protocol
1066///
1067///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#Ethernet_PTP)
1068pub type ETHERNET_PTP = crate::Periph<ethernet_ptp::RegisterBlock, 0x4002_8700>;
1069impl core::fmt::Debug for ETHERNET_PTP {
1070    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1071        f.debug_struct("ETHERNET_PTP").finish()
1072    }
1073}
1074///Ethernet: Precision time protocol
1075pub mod ethernet_ptp;
1076///Ethernet: DMA controller operation
1077///
1078///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#Ethernet_DMA)
1079pub type ETHERNET_DMA = crate::Periph<ethernet_dma::RegisterBlock, 0x4002_9000>;
1080impl core::fmt::Debug for ETHERNET_DMA {
1081    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1082        f.debug_struct("ETHERNET_DMA").finish()
1083    }
1084}
1085///Ethernet: DMA controller operation
1086pub mod ethernet_dma;
1087///USB on the go full speed
1088///
1089///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#OTG_FS_GLOBAL)
1090pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
1091impl core::fmt::Debug for OTG_FS_GLOBAL {
1092    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1093        f.debug_struct("OTG_FS_GLOBAL").finish()
1094    }
1095}
1096///USB on the go full speed
1097pub mod otg_fs_global;
1098///USB on the go full speed
1099///
1100///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#OTG_FS_HOST)
1101pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
1102impl core::fmt::Debug for OTG_FS_HOST {
1103    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1104        f.debug_struct("OTG_FS_HOST").finish()
1105    }
1106}
1107///USB on the go full speed
1108pub mod otg_fs_host;
1109///USB on the go full speed
1110///
1111///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#OTG_FS_DEVICE)
1112pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
1113impl core::fmt::Debug for OTG_FS_DEVICE {
1114    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1115        f.debug_struct("OTG_FS_DEVICE").finish()
1116    }
1117}
1118///USB on the go full speed
1119pub mod otg_fs_device;
1120///USB on the go full speed
1121///
1122///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#OTG_FS_PWRCLK)
1123pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
1124impl core::fmt::Debug for OTG_FS_PWRCLK {
1125    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1126        f.debug_struct("OTG_FS_PWRCLK").finish()
1127    }
1128}
1129///USB on the go full speed
1130pub mod otg_fs_pwrclk;
1131///External interrupt/event controller
1132///
1133///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#EXTI)
1134pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_3c00>;
1135impl core::fmt::Debug for EXTI {
1136    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1137        f.debug_struct("EXTI").finish()
1138    }
1139}
1140///External interrupt/event controller
1141pub mod exti;
1142///FLASH
1143///
1144///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#FLASH)
1145pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_3c00>;
1146impl core::fmt::Debug for FLASH {
1147    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1148        f.debug_struct("FLASH").finish()
1149    }
1150}
1151///FLASH
1152pub mod flash;
1153///Hash processor
1154///
1155///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#HASH)
1156pub type HASH = crate::Periph<hash::RegisterBlock, 0x5006_0400>;
1157impl core::fmt::Debug for HASH {
1158    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1159        f.debug_struct("HASH").finish()
1160    }
1161}
1162///Hash processor
1163pub mod hash;
1164///Cryptographic processor
1165///
1166///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#CRYP)
1167pub type CRYP = crate::Periph<cryp::RegisterBlock, 0x5006_0000>;
1168impl core::fmt::Debug for CRYP {
1169    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1170        f.debug_struct("CRYP").finish()
1171    }
1172}
1173///Cryptographic processor
1174pub mod cryp;
1175///USB on the go high speed
1176///
1177///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#OTG_HS_GLOBAL)
1178pub type OTG_HS_GLOBAL = crate::Periph<otg_hs_global::RegisterBlock, 0x4004_0000>;
1179impl core::fmt::Debug for OTG_HS_GLOBAL {
1180    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1181        f.debug_struct("OTG_HS_GLOBAL").finish()
1182    }
1183}
1184///USB on the go high speed
1185pub mod otg_hs_global;
1186///USB on the go high speed
1187///
1188///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#OTG_HS_HOST)
1189pub type OTG_HS_HOST = crate::Periph<otg_hs_host::RegisterBlock, 0x4004_0400>;
1190impl core::fmt::Debug for OTG_HS_HOST {
1191    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1192        f.debug_struct("OTG_HS_HOST").finish()
1193    }
1194}
1195///USB on the go high speed
1196pub mod otg_hs_host;
1197///USB on the go high speed
1198///
1199///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#OTG_HS_DEVICE)
1200pub type OTG_HS_DEVICE = crate::Periph<otg_hs_device::RegisterBlock, 0x4004_0800>;
1201impl core::fmt::Debug for OTG_HS_DEVICE {
1202    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1203        f.debug_struct("OTG_HS_DEVICE").finish()
1204    }
1205}
1206///USB on the go high speed
1207pub mod otg_hs_device;
1208///USB on the go high speed
1209///
1210///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#OTG_HS_PWRCLK)
1211pub type OTG_HS_PWRCLK = crate::Periph<otg_hs_pwrclk::RegisterBlock, 0x4004_0e00>;
1212impl core::fmt::Debug for OTG_HS_PWRCLK {
1213    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1214        f.debug_struct("OTG_HS_PWRCLK").finish()
1215    }
1216}
1217///USB on the go high speed
1218pub mod otg_hs_pwrclk;
1219///System control block ACTLR
1220///
1221///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#SCB_ACTRL)
1222pub type SCB_ACTRL = crate::Periph<scb_actrl::RegisterBlock, 0xe000_e008>;
1223impl core::fmt::Debug for SCB_ACTRL {
1224    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1225        f.debug_struct("SCB_ACTRL").finish()
1226    }
1227}
1228///System control block ACTLR
1229pub mod scb_actrl;
1230///Nested vectored interrupt controller
1231///
1232///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#NVIC_STIR)
1233pub type NVIC_STIR = crate::Periph<nvic_stir::RegisterBlock, 0xe000_ef00>;
1234impl core::fmt::Debug for NVIC_STIR {
1235    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1236        f.debug_struct("NVIC_STIR").finish()
1237    }
1238}
1239///Nested vectored interrupt controller
1240pub mod nvic_stir;
1241///SysTick timer
1242///
1243///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F215.html#STK)
1244pub type STK = crate::Periph<stk::RegisterBlock, 0xe000_e010>;
1245impl core::fmt::Debug for STK {
1246    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1247        f.debug_struct("STK").finish()
1248    }
1249}
1250///SysTick timer
1251pub mod stk;
1252#[no_mangle]
1253static mut DEVICE_PERIPHERALS: bool = false;
1254/// All the peripherals.
1255#[allow(non_snake_case)]
1256pub struct Peripherals {
1257    ///RNG
1258    pub RNG: RNG,
1259    ///CRC
1260    pub CRC: CRC,
1261    ///DCMI
1262    pub DCMI: DCMI,
1263    ///FSMC
1264    pub FSMC: FSMC,
1265    ///DBGMCU
1266    pub DBGMCU: DBGMCU,
1267    ///DMA2
1268    pub DMA2: DMA2,
1269    ///DMA1
1270    pub DMA1: DMA1,
1271    ///RCC
1272    pub RCC: RCC,
1273    ///GPIOI
1274    pub GPIOI: GPIOI,
1275    ///GPIOH
1276    pub GPIOH: GPIOH,
1277    ///GPIOG
1278    pub GPIOG: GPIOG,
1279    ///GPIOF
1280    pub GPIOF: GPIOF,
1281    ///GPIOE
1282    pub GPIOE: GPIOE,
1283    ///GPIOD
1284    pub GPIOD: GPIOD,
1285    ///GPIOC
1286    pub GPIOC: GPIOC,
1287    ///GPIOB
1288    pub GPIOB: GPIOB,
1289    ///GPIOA
1290    pub GPIOA: GPIOA,
1291    ///SYSCFG
1292    pub SYSCFG: SYSCFG,
1293    ///SPI1
1294    pub SPI1: SPI1,
1295    ///SPI3
1296    pub SPI3: SPI3,
1297    ///SPI2
1298    pub SPI2: SPI2,
1299    ///SDIO
1300    pub SDIO: SDIO,
1301    ///ADC1
1302    pub ADC1: ADC1,
1303    ///ADC2
1304    pub ADC2: ADC2,
1305    ///ADC3
1306    pub ADC3: ADC3,
1307    ///USART1
1308    pub USART1: USART1,
1309    ///USART6
1310    pub USART6: USART6,
1311    ///USART2
1312    pub USART2: USART2,
1313    ///USART3
1314    pub USART3: USART3,
1315    ///DAC
1316    pub DAC: DAC,
1317    ///PWR
1318    pub PWR: PWR,
1319    ///CAN2
1320    pub CAN2: CAN2,
1321    ///CAN1
1322    pub CAN1: CAN1,
1323    ///I2C1
1324    pub I2C1: I2C1,
1325    ///I2C3
1326    pub I2C3: I2C3,
1327    ///I2C2
1328    pub I2C2: I2C2,
1329    ///IWDG
1330    pub IWDG: IWDG,
1331    ///WWDG
1332    pub WWDG: WWDG,
1333    ///RTC
1334    pub RTC: RTC,
1335    ///UART4
1336    pub UART4: UART4,
1337    ///UART5
1338    pub UART5: UART5,
1339    ///ADC_Common
1340    pub ADC_COMMON: ADC_COMMON,
1341    ///TIM1
1342    pub TIM1: TIM1,
1343    ///TIM8
1344    pub TIM8: TIM8,
1345    ///TIM2
1346    pub TIM2: TIM2,
1347    ///TIM3
1348    pub TIM3: TIM3,
1349    ///TIM4
1350    pub TIM4: TIM4,
1351    ///TIM5
1352    pub TIM5: TIM5,
1353    ///TIM9
1354    pub TIM9: TIM9,
1355    ///TIM12
1356    pub TIM12: TIM12,
1357    ///TIM10
1358    pub TIM10: TIM10,
1359    ///TIM11
1360    pub TIM11: TIM11,
1361    ///TIM13
1362    pub TIM13: TIM13,
1363    ///TIM14
1364    pub TIM14: TIM14,
1365    ///TIM6
1366    pub TIM6: TIM6,
1367    ///TIM7
1368    pub TIM7: TIM7,
1369    ///Ethernet_MAC
1370    pub ETHERNET_MAC: ETHERNET_MAC,
1371    ///Ethernet_MMC
1372    pub ETHERNET_MMC: ETHERNET_MMC,
1373    ///Ethernet_PTP
1374    pub ETHERNET_PTP: ETHERNET_PTP,
1375    ///Ethernet_DMA
1376    pub ETHERNET_DMA: ETHERNET_DMA,
1377    ///OTG_FS_GLOBAL
1378    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
1379    ///OTG_FS_HOST
1380    pub OTG_FS_HOST: OTG_FS_HOST,
1381    ///OTG_FS_DEVICE
1382    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
1383    ///OTG_FS_PWRCLK
1384    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
1385    ///EXTI
1386    pub EXTI: EXTI,
1387    ///FLASH
1388    pub FLASH: FLASH,
1389    ///HASH
1390    pub HASH: HASH,
1391    ///CRYP
1392    pub CRYP: CRYP,
1393    ///OTG_HS_GLOBAL
1394    pub OTG_HS_GLOBAL: OTG_HS_GLOBAL,
1395    ///OTG_HS_HOST
1396    pub OTG_HS_HOST: OTG_HS_HOST,
1397    ///OTG_HS_DEVICE
1398    pub OTG_HS_DEVICE: OTG_HS_DEVICE,
1399    ///OTG_HS_PWRCLK
1400    pub OTG_HS_PWRCLK: OTG_HS_PWRCLK,
1401    ///SCB_ACTRL
1402    pub SCB_ACTRL: SCB_ACTRL,
1403    ///NVIC_STIR
1404    pub NVIC_STIR: NVIC_STIR,
1405    ///STK
1406    pub STK: STK,
1407}
1408impl Peripherals {
1409    /// Returns all the peripherals *once*.
1410    #[cfg(feature = "critical-section")]
1411    #[inline]
1412    pub fn take() -> Option<Self> {
1413        critical_section::with(|_| {
1414            if unsafe { DEVICE_PERIPHERALS } {
1415                return None;
1416            }
1417            Some(unsafe { Peripherals::steal() })
1418        })
1419    }
1420    /// Unchecked version of `Peripherals::take`.
1421    ///
1422    /// # Safety
1423    ///
1424    /// Each of the returned peripherals must be used at most once.
1425    #[inline]
1426    pub unsafe fn steal() -> Self {
1427        DEVICE_PERIPHERALS = true;
1428        Peripherals {
1429            RNG: RNG::steal(),
1430            CRC: CRC::steal(),
1431            DCMI: DCMI::steal(),
1432            FSMC: FSMC::steal(),
1433            DBGMCU: DBGMCU::steal(),
1434            DMA2: DMA2::steal(),
1435            DMA1: DMA1::steal(),
1436            RCC: RCC::steal(),
1437            GPIOI: GPIOI::steal(),
1438            GPIOH: GPIOH::steal(),
1439            GPIOG: GPIOG::steal(),
1440            GPIOF: GPIOF::steal(),
1441            GPIOE: GPIOE::steal(),
1442            GPIOD: GPIOD::steal(),
1443            GPIOC: GPIOC::steal(),
1444            GPIOB: GPIOB::steal(),
1445            GPIOA: GPIOA::steal(),
1446            SYSCFG: SYSCFG::steal(),
1447            SPI1: SPI1::steal(),
1448            SPI3: SPI3::steal(),
1449            SPI2: SPI2::steal(),
1450            SDIO: SDIO::steal(),
1451            ADC1: ADC1::steal(),
1452            ADC2: ADC2::steal(),
1453            ADC3: ADC3::steal(),
1454            USART1: USART1::steal(),
1455            USART6: USART6::steal(),
1456            USART2: USART2::steal(),
1457            USART3: USART3::steal(),
1458            DAC: DAC::steal(),
1459            PWR: PWR::steal(),
1460            CAN2: CAN2::steal(),
1461            CAN1: CAN1::steal(),
1462            I2C1: I2C1::steal(),
1463            I2C3: I2C3::steal(),
1464            I2C2: I2C2::steal(),
1465            IWDG: IWDG::steal(),
1466            WWDG: WWDG::steal(),
1467            RTC: RTC::steal(),
1468            UART4: UART4::steal(),
1469            UART5: UART5::steal(),
1470            ADC_COMMON: ADC_COMMON::steal(),
1471            TIM1: TIM1::steal(),
1472            TIM8: TIM8::steal(),
1473            TIM2: TIM2::steal(),
1474            TIM3: TIM3::steal(),
1475            TIM4: TIM4::steal(),
1476            TIM5: TIM5::steal(),
1477            TIM9: TIM9::steal(),
1478            TIM12: TIM12::steal(),
1479            TIM10: TIM10::steal(),
1480            TIM11: TIM11::steal(),
1481            TIM13: TIM13::steal(),
1482            TIM14: TIM14::steal(),
1483            TIM6: TIM6::steal(),
1484            TIM7: TIM7::steal(),
1485            ETHERNET_MAC: ETHERNET_MAC::steal(),
1486            ETHERNET_MMC: ETHERNET_MMC::steal(),
1487            ETHERNET_PTP: ETHERNET_PTP::steal(),
1488            ETHERNET_DMA: ETHERNET_DMA::steal(),
1489            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
1490            OTG_FS_HOST: OTG_FS_HOST::steal(),
1491            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
1492            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
1493            EXTI: EXTI::steal(),
1494            FLASH: FLASH::steal(),
1495            HASH: HASH::steal(),
1496            CRYP: CRYP::steal(),
1497            OTG_HS_GLOBAL: OTG_HS_GLOBAL::steal(),
1498            OTG_HS_HOST: OTG_HS_HOST::steal(),
1499            OTG_HS_DEVICE: OTG_HS_DEVICE::steal(),
1500            OTG_HS_PWRCLK: OTG_HS_PWRCLK::steal(),
1501            SCB_ACTRL: SCB_ACTRL::steal(),
1502            NVIC_STIR: NVIC_STIR::steal(),
1503            STK: STK::steal(),
1504        }
1505    }
1506}
stm32f2/stm32f215/mod.rs

stm32f2/stm32f215/
mod.rs
