stm32f2 0.16.0

Device support crates for STM32F2 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304

///Register `DMASR` reader
pub type R = crate::R<DMASRrs>;
///Register `DMASR` writer
pub type W = crate::W<DMASRrs>;
///Field `TS` reader - Transmit status
pub type TS_R = crate::BitReader;
///Field `TS` writer - Transmit status
pub type TS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TPSS` reader - Transmit process stopped status
pub type TPSS_R = crate::BitReader;
///Field `TPSS` writer - Transmit process stopped status
pub type TPSS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TBUS` reader - Transmit buffer unavailable status
pub type TBUS_R = crate::BitReader;
///Field `TBUS` writer - Transmit buffer unavailable status
pub type TBUS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TJTS` reader - Transmit jabber timeout status
pub type TJTS_R = crate::BitReader;
///Field `TJTS` writer - Transmit jabber timeout status
pub type TJTS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ROS` reader - Receive overflow status
pub type ROS_R = crate::BitReader;
///Field `ROS` writer - Receive overflow status
pub type ROS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TUS` reader - Transmit underflow status
pub type TUS_R = crate::BitReader;
///Field `TUS` writer - Transmit underflow status
pub type TUS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RS` reader - Receive status
pub type RS_R = crate::BitReader;
///Field `RS` writer - Receive status
pub type RS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RBUS` reader - Receive buffer unavailable status
pub type RBUS_R = crate::BitReader;
///Field `RBUS` writer - Receive buffer unavailable status
pub type RBUS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RPSS` reader - Receive process stopped status
pub type RPSS_R = crate::BitReader;
///Field `RPSS` writer - Receive process stopped status
pub type RPSS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `PWTS` reader - Receive watchdog timeout status
pub type PWTS_R = crate::BitReader;
///Field `PWTS` writer - Receive watchdog timeout status
pub type PWTS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ETS` reader - Early transmit status
pub type ETS_R = crate::BitReader;
///Field `ETS` writer - Early transmit status
pub type ETS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `FBES` reader - Fatal bus error status
pub type FBES_R = crate::BitReader;
///Field `FBES` writer - Fatal bus error status
pub type FBES_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `ERS` reader - Early receive status
pub type ERS_R = crate::BitReader;
///Field `ERS` writer - Early receive status
pub type ERS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `AIS` reader - Abnormal interrupt summary
pub type AIS_R = crate::BitReader;
///Field `AIS` writer - Abnormal interrupt summary
pub type AIS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `NIS` reader - Normal interrupt summary
pub type NIS_R = crate::BitReader;
///Field `NIS` writer - Normal interrupt summary
pub type NIS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `RPS` reader - Receive process state
pub type RPS_R = crate::FieldReader;
///Field `TPS` reader - Transmit process state
pub type TPS_R = crate::FieldReader;
///Field `EBS` reader - Error bits status
pub type EBS_R = crate::FieldReader;
///Field `MMCS` reader - MMC status
pub type MMCS_R = crate::BitReader;
///Field `PMTS` reader - PMT status
pub type PMTS_R = crate::BitReader;
///Field `TSTS` reader - Time stamp trigger status
pub type TSTS_R = crate::BitReader;
impl R {
    ///Bit 0 - Transmit status
    #[inline(always)]
    pub fn ts(&self) -> TS_R {
        TS_R::new((self.bits & 1) != 0)
    }
    ///Bit 1 - Transmit process stopped status
    #[inline(always)]
    pub fn tpss(&self) -> TPSS_R {
        TPSS_R::new(((self.bits >> 1) & 1) != 0)
    }
    ///Bit 2 - Transmit buffer unavailable status
    #[inline(always)]
    pub fn tbus(&self) -> TBUS_R {
        TBUS_R::new(((self.bits >> 2) & 1) != 0)
    }
    ///Bit 3 - Transmit jabber timeout status
    #[inline(always)]
    pub fn tjts(&self) -> TJTS_R {
        TJTS_R::new(((self.bits >> 3) & 1) != 0)
    }
    ///Bit 4 - Receive overflow status
    #[inline(always)]
    pub fn ros(&self) -> ROS_R {
        ROS_R::new(((self.bits >> 4) & 1) != 0)
    }
    ///Bit 5 - Transmit underflow status
    #[inline(always)]
    pub fn tus(&self) -> TUS_R {
        TUS_R::new(((self.bits >> 5) & 1) != 0)
    }
    ///Bit 6 - Receive status
    #[inline(always)]
    pub fn rs(&self) -> RS_R {
        RS_R::new(((self.bits >> 6) & 1) != 0)
    }
    ///Bit 7 - Receive buffer unavailable status
    #[inline(always)]
    pub fn rbus(&self) -> RBUS_R {
        RBUS_R::new(((self.bits >> 7) & 1) != 0)
    }
    ///Bit 8 - Receive process stopped status
    #[inline(always)]
    pub fn rpss(&self) -> RPSS_R {
        RPSS_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - Receive watchdog timeout status
    #[inline(always)]
    pub fn pwts(&self) -> PWTS_R {
        PWTS_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - Early transmit status
    #[inline(always)]
    pub fn ets(&self) -> ETS_R {
        ETS_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bit 13 - Fatal bus error status
    #[inline(always)]
    pub fn fbes(&self) -> FBES_R {
        FBES_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - Early receive status
    #[inline(always)]
    pub fn ers(&self) -> ERS_R {
        ERS_R::new(((self.bits >> 14) & 1) != 0)
    }
    ///Bit 15 - Abnormal interrupt summary
    #[inline(always)]
    pub fn ais(&self) -> AIS_R {
        AIS_R::new(((self.bits >> 15) & 1) != 0)
    }
    ///Bit 16 - Normal interrupt summary
    #[inline(always)]
    pub fn nis(&self) -> NIS_R {
        NIS_R::new(((self.bits >> 16) & 1) != 0)
    }
    ///Bits 17:19 - Receive process state
    #[inline(always)]
    pub fn rps(&self) -> RPS_R {
        RPS_R::new(((self.bits >> 17) & 7) as u8)
    }
    ///Bits 20:22 - Transmit process state
    #[inline(always)]
    pub fn tps(&self) -> TPS_R {
        TPS_R::new(((self.bits >> 20) & 7) as u8)
    }
    ///Bits 23:25 - Error bits status
    #[inline(always)]
    pub fn ebs(&self) -> EBS_R {
        EBS_R::new(((self.bits >> 23) & 7) as u8)
    }
    ///Bit 27 - MMC status
    #[inline(always)]
    pub fn mmcs(&self) -> MMCS_R {
        MMCS_R::new(((self.bits >> 27) & 1) != 0)
    }
    ///Bit 28 - PMT status
    #[inline(always)]
    pub fn pmts(&self) -> PMTS_R {
        PMTS_R::new(((self.bits >> 28) & 1) != 0)
    }
    ///Bit 29 - Time stamp trigger status
    #[inline(always)]
    pub fn tsts(&self) -> TSTS_R {
        TSTS_R::new(((self.bits >> 29) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMASR")
            .field("ts", &self.ts())
            .field("tpss", &self.tpss())
            .field("tbus", &self.tbus())
            .field("tjts", &self.tjts())
            .field("ros", &self.ros())
            .field("tus", &self.tus())
            .field("rs", &self.rs())
            .field("rbus", &self.rbus())
            .field("rpss", &self.rpss())
            .field("pwts", &self.pwts())
            .field("ets", &self.ets())
            .field("fbes", &self.fbes())
            .field("ers", &self.ers())
            .field("ais", &self.ais())
            .field("nis", &self.nis())
            .field("rps", &self.rps())
            .field("tps", &self.tps())
            .field("ebs", &self.ebs())
            .field("mmcs", &self.mmcs())
            .field("pmts", &self.pmts())
            .field("tsts", &self.tsts())
            .finish()
    }
}
impl W {
    ///Bit 0 - Transmit status
    #[inline(always)]
    pub fn ts(&mut self) -> TS_W<DMASRrs> {
        TS_W::new(self, 0)
    }
    ///Bit 1 - Transmit process stopped status
    #[inline(always)]
    pub fn tpss(&mut self) -> TPSS_W<DMASRrs> {
        TPSS_W::new(self, 1)
    }
    ///Bit 2 - Transmit buffer unavailable status
    #[inline(always)]
    pub fn tbus(&mut self) -> TBUS_W<DMASRrs> {
        TBUS_W::new(self, 2)
    }
    ///Bit 3 - Transmit jabber timeout status
    #[inline(always)]
    pub fn tjts(&mut self) -> TJTS_W<DMASRrs> {
        TJTS_W::new(self, 3)
    }
    ///Bit 4 - Receive overflow status
    #[inline(always)]
    pub fn ros(&mut self) -> ROS_W<DMASRrs> {
        ROS_W::new(self, 4)
    }
    ///Bit 5 - Transmit underflow status
    #[inline(always)]
    pub fn tus(&mut self) -> TUS_W<DMASRrs> {
        TUS_W::new(self, 5)
    }
    ///Bit 6 - Receive status
    #[inline(always)]
    pub fn rs(&mut self) -> RS_W<DMASRrs> {
        RS_W::new(self, 6)
    }
    ///Bit 7 - Receive buffer unavailable status
    #[inline(always)]
    pub fn rbus(&mut self) -> RBUS_W<DMASRrs> {
        RBUS_W::new(self, 7)
    }
    ///Bit 8 - Receive process stopped status
    #[inline(always)]
    pub fn rpss(&mut self) -> RPSS_W<DMASRrs> {
        RPSS_W::new(self, 8)
    }
    ///Bit 9 - Receive watchdog timeout status
    #[inline(always)]
    pub fn pwts(&mut self) -> PWTS_W<DMASRrs> {
        PWTS_W::new(self, 9)
    }
    ///Bit 10 - Early transmit status
    #[inline(always)]
    pub fn ets(&mut self) -> ETS_W<DMASRrs> {
        ETS_W::new(self, 10)
    }
    ///Bit 13 - Fatal bus error status
    #[inline(always)]
    pub fn fbes(&mut self) -> FBES_W<DMASRrs> {
        FBES_W::new(self, 13)
    }
    ///Bit 14 - Early receive status
    #[inline(always)]
    pub fn ers(&mut self) -> ERS_W<DMASRrs> {
        ERS_W::new(self, 14)
    }
    ///Bit 15 - Abnormal interrupt summary
    #[inline(always)]
    pub fn ais(&mut self) -> AIS_W<DMASRrs> {
        AIS_W::new(self, 15)
    }
    ///Bit 16 - Normal interrupt summary
    #[inline(always)]
    pub fn nis(&mut self) -> NIS_W<DMASRrs> {
        NIS_W::new(self, 16)
    }
}
/**Ethernet DMA status register

You can [`read`](crate::Reg::read) this register and get [`dmasr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F217.html#Ethernet_DMA:DMASR)*/
pub struct DMASRrs;
impl crate::RegisterSpec for DMASRrs {
    type Ux = u32;
}
///`read()` method returns [`dmasr::R`](R) reader structure
impl crate::Readable for DMASRrs {}
///`write(|w| ..)` method takes [`dmasr::W`](W) writer structure
impl crate::Writable for DMASRrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets DMASR to value 0
impl crate::Resettable for DMASRrs {}