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#[doc = "Reader of register CR2"] pub type R = crate::R<u32, super::CR2>; #[doc = "Writer for register CR2"] pub type W = crate::W<u32, super::CR2>; #[doc = "Register CR2 `reset()`'s with value 0"] impl crate::ResetValue for super::CR2 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `SWSTART`"] pub type SWSTART_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SWSTART`"] pub struct SWSTART_W<'a> { w: &'a mut W, } impl<'a> SWSTART_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); self.w } } #[doc = "Reader of field `EXTEN`"] pub type EXTEN_R = crate::R<u8, u8>; #[doc = "Write proxy for field `EXTEN`"] pub struct EXTEN_W<'a> { w: &'a mut W, } impl<'a> EXTEN_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28); self.w } } #[doc = "Reader of field `EXTSEL`"] pub type EXTSEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `EXTSEL`"] pub struct EXTSEL_W<'a> { w: &'a mut W, } impl<'a> EXTSEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24); self.w } } #[doc = "Reader of field `JSWSTART`"] pub type JSWSTART_R = crate::R<bool, bool>; #[doc = "Write proxy for field `JSWSTART`"] pub struct JSWSTART_W<'a> { w: &'a mut W, } impl<'a> JSWSTART_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); self.w } } #[doc = "Reader of field `JEXTEN`"] pub type JEXTEN_R = crate::R<u8, u8>; #[doc = "Write proxy for field `JEXTEN`"] pub struct JEXTEN_W<'a> { w: &'a mut W, } impl<'a> JEXTEN_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20); self.w } } #[doc = "Reader of field `JEXTSEL`"] pub type JEXTSEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `JEXTSEL`"] pub struct JEXTSEL_W<'a> { w: &'a mut W, } impl<'a> JEXTSEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16); self.w } } #[doc = "Reader of field `ALIGN`"] pub type ALIGN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ALIGN`"] pub struct ALIGN_W<'a> { w: &'a mut W, } impl<'a> ALIGN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); self.w } } #[doc = "Reader of field `EOCS`"] pub type EOCS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `EOCS`"] pub struct EOCS_W<'a> { w: &'a mut W, } impl<'a> EOCS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); self.w } } #[doc = "Reader of field `DDS`"] pub type DDS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DDS`"] pub struct DDS_W<'a> { w: &'a mut W, } impl<'a> DDS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); self.w } } #[doc = "Reader of field `DMA`"] pub type DMA_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DMA`"] pub struct DMA_W<'a> { w: &'a mut W, } impl<'a> DMA_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Reader of field `CONT`"] pub type CONT_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CONT`"] pub struct CONT_W<'a> { w: &'a mut W, } impl<'a> CONT_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `ADON`"] pub type ADON_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ADON`"] pub struct ADON_W<'a> { w: &'a mut W, } impl<'a> ADON_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } impl R { #[doc = "Bit 30 - Start conversion of regular channels"] #[inline(always)] pub fn swstart(&self) -> SWSTART_R { SWSTART_R::new(((self.bits >> 30) & 0x01) != 0) } #[doc = "Bits 28:29 - External trigger enable for regular channels"] #[inline(always)] pub fn exten(&self) -> EXTEN_R { EXTEN_R::new(((self.bits >> 28) & 0x03) as u8) } #[doc = "Bits 24:27 - External event select for regular group"] #[inline(always)] pub fn extsel(&self) -> EXTSEL_R { EXTSEL_R::new(((self.bits >> 24) & 0x0f) as u8) } #[doc = "Bit 22 - Start conversion of injected channels"] #[inline(always)] pub fn jswstart(&self) -> JSWSTART_R { JSWSTART_R::new(((self.bits >> 22) & 0x01) != 0) } #[doc = "Bits 20:21 - External trigger enable for injected channels"] #[inline(always)] pub fn jexten(&self) -> JEXTEN_R { JEXTEN_R::new(((self.bits >> 20) & 0x03) as u8) } #[doc = "Bits 16:19 - External event select for injected group"] #[inline(always)] pub fn jextsel(&self) -> JEXTSEL_R { JEXTSEL_R::new(((self.bits >> 16) & 0x0f) as u8) } #[doc = "Bit 11 - Data alignment"] #[inline(always)] pub fn align(&self) -> ALIGN_R { ALIGN_R::new(((self.bits >> 11) & 0x01) != 0) } #[doc = "Bit 10 - End of conversion selection"] #[inline(always)] pub fn eocs(&self) -> EOCS_R { EOCS_R::new(((self.bits >> 10) & 0x01) != 0) } #[doc = "Bit 9 - DMA disable selection (for single ADC mode)"] #[inline(always)] pub fn dds(&self) -> DDS_R { DDS_R::new(((self.bits >> 9) & 0x01) != 0) } #[doc = "Bit 8 - Direct memory access mode (for single ADC mode)"] #[inline(always)] pub fn dma(&self) -> DMA_R { DMA_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 1 - Continuous conversion"] #[inline(always)] pub fn cont(&self) -> CONT_R { CONT_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 0 - A/D Converter ON / OFF"] #[inline(always)] pub fn adon(&self) -> ADON_R { ADON_R::new((self.bits & 0x01) != 0) } } impl W { #[doc = "Bit 30 - Start conversion of regular channels"] #[inline(always)] pub fn swstart(&mut self) -> SWSTART_W { SWSTART_W { w: self } } #[doc = "Bits 28:29 - External trigger enable for regular channels"] #[inline(always)] pub fn exten(&mut self) -> EXTEN_W { EXTEN_W { w: self } } #[doc = "Bits 24:27 - External event select for regular group"] #[inline(always)] pub fn extsel(&mut self) -> EXTSEL_W { EXTSEL_W { w: self } } #[doc = "Bit 22 - Start conversion of injected channels"] #[inline(always)] pub fn jswstart(&mut self) -> JSWSTART_W { JSWSTART_W { w: self } } #[doc = "Bits 20:21 - External trigger enable for injected channels"] #[inline(always)] pub fn jexten(&mut self) -> JEXTEN_W { JEXTEN_W { w: self } } #[doc = "Bits 16:19 - External event select for injected group"] #[inline(always)] pub fn jextsel(&mut self) -> JEXTSEL_W { JEXTSEL_W { w: self } } #[doc = "Bit 11 - Data alignment"] #[inline(always)] pub fn align(&mut self) -> ALIGN_W { ALIGN_W { w: self } } #[doc = "Bit 10 - End of conversion selection"] #[inline(always)] pub fn eocs(&mut self) -> EOCS_W { EOCS_W { w: self } } #[doc = "Bit 9 - DMA disable selection (for single ADC mode)"] #[inline(always)] pub fn dds(&mut self) -> DDS_W { DDS_W { w: self } } #[doc = "Bit 8 - Direct memory access mode (for single ADC mode)"] #[inline(always)] pub fn dma(&mut self) -> DMA_W { DMA_W { w: self } } #[doc = "Bit 1 - Continuous conversion"] #[inline(always)] pub fn cont(&mut self) -> CONT_W { CONT_W { w: self } } #[doc = "Bit 0 - A/D Converter ON / OFF"] #[inline(always)] pub fn adon(&mut self) -> ADON_W { ADON_W { w: self } } }