stm32f1xx_hal/
watchdog.rs

1//! Watchdog peripherals
2
3use crate::{
4    hal_02::watchdog::{Watchdog, WatchdogEnable},
5    pac::{DBGMCU as DBG, IWDG},
6    time::MilliSeconds,
7};
8use fugit::ExtU32;
9
10/// Wraps the Independent Watchdog (IWDG) peripheral
11pub struct IndependentWatchdog {
12    iwdg: IWDG,
13}
14
15const LSI_KHZ: u32 = 40;
16const MAX_PR: u8 = 8;
17const MAX_RL: u16 = 0xFFF;
18const KR_ACCESS: u16 = 0x5555;
19const KR_RELOAD: u16 = 0xAAAA;
20const KR_START: u16 = 0xCCCC;
21
22impl IndependentWatchdog {
23    /// Wrap and start the watchdog
24    pub fn new(iwdg: IWDG) -> Self {
25        IndependentWatchdog { iwdg }
26    }
27
28    /// Debug independent watchdog stopped when core is halted
29    pub fn stop_on_debug(&self, dbg: &DBG, stop: bool) {
30        dbg.cr().modify(|_, w| w.dbg_iwdg_stop().bit(stop));
31    }
32
33    fn setup(&self, timeout_ms: u32) {
34        let mut pr = 0;
35        while pr < MAX_PR && Self::timeout_period(pr, MAX_RL) < timeout_ms {
36            pr += 1;
37        }
38
39        let max_period = Self::timeout_period(pr, MAX_RL);
40        let max_rl = u32::from(MAX_RL);
41        let rl = (timeout_ms * max_rl / max_period).min(max_rl) as u16;
42
43        self.access_registers(|iwdg| {
44            iwdg.pr().modify(|_, w| unsafe { w.pr().bits(pr) });
45            iwdg.rlr().modify(|_, w| w.rl().set(rl));
46        });
47    }
48
49    fn is_pr_updating(&self) -> bool {
50        self.iwdg.sr().read().pvu().bit()
51    }
52
53    /// Returns the interval in ms
54    pub fn interval(&self) -> MilliSeconds {
55        while self.is_pr_updating() {}
56
57        let pr = self.iwdg.pr().read().pr().bits();
58        let rl = self.iwdg.rlr().read().rl().bits();
59        let ms = Self::timeout_period(pr, rl);
60        ms.millis()
61    }
62
63    /// pr: Prescaler divider bits, rl: reload value
64    ///
65    /// Returns ms
66    fn timeout_period(pr: u8, rl: u16) -> u32 {
67        let divider: u32 = match pr {
68            0b000 => 4,
69            0b001 => 8,
70            0b010 => 16,
71            0b011 => 32,
72            0b100 => 64,
73            0b101 => 128,
74            0b110 => 256,
75            0b111 => 256,
76            _ => panic!("Invalid IWDG prescaler divider"),
77        };
78        (u32::from(rl) + 1) * divider / LSI_KHZ
79    }
80
81    fn access_registers<A, F: FnMut(&IWDG) -> A>(&self, mut f: F) -> A {
82        // Unprotect write access to registers
83        self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_ACCESS) });
84        let a = f(&self.iwdg);
85
86        // Protect again
87        self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_RELOAD) });
88        a
89    }
90
91    pub fn start(&mut self, period: MilliSeconds) {
92        self.setup(period.ticks());
93
94        self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_START) });
95    }
96
97    pub fn feed(&mut self) {
98        self.iwdg.kr().write(|w| unsafe { w.key().bits(KR_RELOAD) });
99    }
100}
101
102impl WatchdogEnable for IndependentWatchdog {
103    type Time = MilliSeconds;
104
105    fn start<T: Into<Self::Time>>(&mut self, period: T) {
106        self.start(period.into());
107    }
108}
109
110impl Watchdog for IndependentWatchdog {
111    fn feed(&mut self) {
112        self.feed();
113    }
114}
stm32f1xx_hal/watchdog.rs

stm32f1xx_hal/
watchdog.rs
