1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::SMCR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct ETPR {
47 bits: bool,
48}
49impl ETPR {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bit(&self) -> bool {
53 self.bits
54 }
55 #[doc = r" Returns `true` if the bit is clear (0)"]
56 #[inline]
57 pub fn bit_is_clear(&self) -> bool {
58 !self.bit()
59 }
60 #[doc = r" Returns `true` if the bit is set (1)"]
61 #[inline]
62 pub fn bit_is_set(&self) -> bool {
63 self.bit()
64 }
65}
66#[doc = r" Value of the field"]
67pub struct ECER {
68 bits: bool,
69}
70impl ECER {
71 #[doc = r" Value of the field as raw bits"]
72 #[inline]
73 pub fn bit(&self) -> bool {
74 self.bits
75 }
76 #[doc = r" Returns `true` if the bit is clear (0)"]
77 #[inline]
78 pub fn bit_is_clear(&self) -> bool {
79 !self.bit()
80 }
81 #[doc = r" Returns `true` if the bit is set (1)"]
82 #[inline]
83 pub fn bit_is_set(&self) -> bool {
84 self.bit()
85 }
86}
87#[doc = r" Value of the field"]
88pub struct ETPSR {
89 bits: u8,
90}
91impl ETPSR {
92 #[doc = r" Value of the field as raw bits"]
93 #[inline]
94 pub fn bits(&self) -> u8 {
95 self.bits
96 }
97}
98#[doc = r" Value of the field"]
99pub struct ETFR {
100 bits: u8,
101}
102impl ETFR {
103 #[doc = r" Value of the field as raw bits"]
104 #[inline]
105 pub fn bits(&self) -> u8 {
106 self.bits
107 }
108}
109#[doc = r" Value of the field"]
110pub struct MSMR {
111 bits: bool,
112}
113impl MSMR {
114 #[doc = r" Value of the field as raw bits"]
115 #[inline]
116 pub fn bit(&self) -> bool {
117 self.bits
118 }
119 #[doc = r" Returns `true` if the bit is clear (0)"]
120 #[inline]
121 pub fn bit_is_clear(&self) -> bool {
122 !self.bit()
123 }
124 #[doc = r" Returns `true` if the bit is set (1)"]
125 #[inline]
126 pub fn bit_is_set(&self) -> bool {
127 self.bit()
128 }
129}
130#[doc = "Possible values of the field `TS`"]
131#[derive(Clone, Copy, Debug, PartialEq)]
132pub enum TSR {
133 #[doc = "Internal Trigger 0 (ITR0)"]
134 ITR0,
135 #[doc = "Internal Trigger 1 (ITR1)"]
136 ITR1,
137 #[doc = "Internal Trigger 2 (ITR2)"]
138 ITR2,
139 #[doc = "Internal Trigger 3 (ITR3)"]
140 ITR3,
141 #[doc = "TI1 Edge Detector"]
142 TI1F_ED,
143 #[doc = "Filtered Timer Input 1"]
144 TI1FP1,
145 #[doc = "Filtered Timer Input 2"]
146 TI2FP2,
147 #[doc = "External Trigger input"]
148 ETRF,
149}
150impl TSR {
151 #[doc = r" Value of the field as raw bits"]
152 #[inline]
153 pub fn bits(&self) -> u8 {
154 match *self {
155 TSR::ITR0 => 0,
156 TSR::ITR1 => 1,
157 TSR::ITR2 => 2,
158 TSR::ITR3 => 3,
159 TSR::TI1F_ED => 4,
160 TSR::TI1FP1 => 5,
161 TSR::TI2FP2 => 6,
162 TSR::ETRF => 7,
163 }
164 }
165 #[allow(missing_docs)]
166 #[doc(hidden)]
167 #[inline]
168 pub fn _from(value: u8) -> TSR {
169 match value {
170 0 => TSR::ITR0,
171 1 => TSR::ITR1,
172 2 => TSR::ITR2,
173 3 => TSR::ITR3,
174 4 => TSR::TI1F_ED,
175 5 => TSR::TI1FP1,
176 6 => TSR::TI2FP2,
177 7 => TSR::ETRF,
178 _ => unreachable!(),
179 }
180 }
181 #[doc = "Checks if the value of the field is `ITR0`"]
182 #[inline]
183 pub fn is_itr0(&self) -> bool {
184 *self == TSR::ITR0
185 }
186 #[doc = "Checks if the value of the field is `ITR1`"]
187 #[inline]
188 pub fn is_itr1(&self) -> bool {
189 *self == TSR::ITR1
190 }
191 #[doc = "Checks if the value of the field is `ITR2`"]
192 #[inline]
193 pub fn is_itr2(&self) -> bool {
194 *self == TSR::ITR2
195 }
196 #[doc = "Checks if the value of the field is `ITR3`"]
197 #[inline]
198 pub fn is_itr3(&self) -> bool {
199 *self == TSR::ITR3
200 }
201 #[doc = "Checks if the value of the field is `TI1F_ED`"]
202 #[inline]
203 pub fn is_ti1f_ed(&self) -> bool {
204 *self == TSR::TI1F_ED
205 }
206 #[doc = "Checks if the value of the field is `TI1FP1`"]
207 #[inline]
208 pub fn is_ti1fp1(&self) -> bool {
209 *self == TSR::TI1FP1
210 }
211 #[doc = "Checks if the value of the field is `TI2FP2`"]
212 #[inline]
213 pub fn is_ti2fp2(&self) -> bool {
214 *self == TSR::TI2FP2
215 }
216 #[doc = "Checks if the value of the field is `ETRF`"]
217 #[inline]
218 pub fn is_etrf(&self) -> bool {
219 *self == TSR::ETRF
220 }
221}
222#[doc = "Possible values of the field `SMS`"]
223#[derive(Clone, Copy, Debug, PartialEq)]
224pub enum SMSR {
225 #[doc = "Counter disabled"]
226 DISABLED,
227 #[doc = "Encoder mode, count up/down on TI2FP1"]
228 ENCODERTI2,
229 #[doc = "Encoder mode, count up/down on TI1FP2"]
230 ENCODERTI1,
231 #[doc = "Encoder mode, count up/down on both TI1FP1 and TI2FP2"]
232 ENCODERTI1TI2,
233 #[doc = "Rising edge of the selected trigger input (TRGI) reinitializes the counter"]
234 RESET,
235 #[doc = " The counter clock is enabled when the trigger input (TRGI) is high"]
236 GATED,
237 #[doc = "The counter starts at a rising edge of the trigger TRGI "]
238 TRIGGER,
239 #[doc = " Rising edges of the selected trigger (TRGI) clock the counter"]
240 EXTERNAL,
241}
242impl SMSR {
243 #[doc = r" Value of the field as raw bits"]
244 #[inline]
245 pub fn bits(&self) -> u8 {
246 match *self {
247 SMSR::DISABLED => 0,
248 SMSR::ENCODERTI2 => 1,
249 SMSR::ENCODERTI1 => 2,
250 SMSR::ENCODERTI1TI2 => 3,
251 SMSR::RESET => 4,
252 SMSR::GATED => 5,
253 SMSR::TRIGGER => 6,
254 SMSR::EXTERNAL => 7,
255 }
256 }
257 #[allow(missing_docs)]
258 #[doc(hidden)]
259 #[inline]
260 pub fn _from(value: u8) -> SMSR {
261 match value {
262 0 => SMSR::DISABLED,
263 1 => SMSR::ENCODERTI2,
264 2 => SMSR::ENCODERTI1,
265 3 => SMSR::ENCODERTI1TI2,
266 4 => SMSR::RESET,
267 5 => SMSR::GATED,
268 6 => SMSR::TRIGGER,
269 7 => SMSR::EXTERNAL,
270 _ => unreachable!(),
271 }
272 }
273 #[doc = "Checks if the value of the field is `DISABLED`"]
274 #[inline]
275 pub fn is_disabled(&self) -> bool {
276 *self == SMSR::DISABLED
277 }
278 #[doc = "Checks if the value of the field is `ENCODERTI2`"]
279 #[inline]
280 pub fn is_encoder_ti2(&self) -> bool {
281 *self == SMSR::ENCODERTI2
282 }
283 #[doc = "Checks if the value of the field is `ENCODERTI1`"]
284 #[inline]
285 pub fn is_encoder_ti1(&self) -> bool {
286 *self == SMSR::ENCODERTI1
287 }
288 #[doc = "Checks if the value of the field is `ENCODERTI1TI2`"]
289 #[inline]
290 pub fn is_encoder_ti1ti2(&self) -> bool {
291 *self == SMSR::ENCODERTI1TI2
292 }
293 #[doc = "Checks if the value of the field is `RESET`"]
294 #[inline]
295 pub fn is_reset(&self) -> bool {
296 *self == SMSR::RESET
297 }
298 #[doc = "Checks if the value of the field is `GATED`"]
299 #[inline]
300 pub fn is_gated(&self) -> bool {
301 *self == SMSR::GATED
302 }
303 #[doc = "Checks if the value of the field is `TRIGGER`"]
304 #[inline]
305 pub fn is_trigger(&self) -> bool {
306 *self == SMSR::TRIGGER
307 }
308 #[doc = "Checks if the value of the field is `EXTERNAL`"]
309 #[inline]
310 pub fn is_external(&self) -> bool {
311 *self == SMSR::EXTERNAL
312 }
313}
314#[doc = r" Proxy"]
315pub struct _ETPW<'a> {
316 w: &'a mut W,
317}
318impl<'a> _ETPW<'a> {
319 #[doc = r" Sets the field bit"]
320 pub fn set_bit(self) -> &'a mut W {
321 self.bit(true)
322 }
323 #[doc = r" Clears the field bit"]
324 pub fn clear_bit(self) -> &'a mut W {
325 self.bit(false)
326 }
327 #[doc = r" Writes raw bits to the field"]
328 #[inline]
329 pub fn bit(self, value: bool) -> &'a mut W {
330 const MASK: bool = true;
331 const OFFSET: u8 = 15;
332 self.w.bits &= !((MASK as u32) << OFFSET);
333 self.w.bits |= ((value & MASK) as u32) << OFFSET;
334 self.w
335 }
336}
337#[doc = r" Proxy"]
338pub struct _ECEW<'a> {
339 w: &'a mut W,
340}
341impl<'a> _ECEW<'a> {
342 #[doc = r" Sets the field bit"]
343 pub fn set_bit(self) -> &'a mut W {
344 self.bit(true)
345 }
346 #[doc = r" Clears the field bit"]
347 pub fn clear_bit(self) -> &'a mut W {
348 self.bit(false)
349 }
350 #[doc = r" Writes raw bits to the field"]
351 #[inline]
352 pub fn bit(self, value: bool) -> &'a mut W {
353 const MASK: bool = true;
354 const OFFSET: u8 = 14;
355 self.w.bits &= !((MASK as u32) << OFFSET);
356 self.w.bits |= ((value & MASK) as u32) << OFFSET;
357 self.w
358 }
359}
360#[doc = r" Proxy"]
361pub struct _ETPSW<'a> {
362 w: &'a mut W,
363}
364impl<'a> _ETPSW<'a> {
365 #[doc = r" Writes raw bits to the field"]
366 #[inline]
367 pub unsafe fn bits(self, value: u8) -> &'a mut W {
368 const MASK: u8 = 3;
369 const OFFSET: u8 = 12;
370 self.w.bits &= !((MASK as u32) << OFFSET);
371 self.w.bits |= ((value & MASK) as u32) << OFFSET;
372 self.w
373 }
374}
375#[doc = r" Proxy"]
376pub struct _ETFW<'a> {
377 w: &'a mut W,
378}
379impl<'a> _ETFW<'a> {
380 #[doc = r" Writes raw bits to the field"]
381 #[inline]
382 pub unsafe fn bits(self, value: u8) -> &'a mut W {
383 const MASK: u8 = 15;
384 const OFFSET: u8 = 8;
385 self.w.bits &= !((MASK as u32) << OFFSET);
386 self.w.bits |= ((value & MASK) as u32) << OFFSET;
387 self.w
388 }
389}
390#[doc = r" Proxy"]
391pub struct _MSMW<'a> {
392 w: &'a mut W,
393}
394impl<'a> _MSMW<'a> {
395 #[doc = r" Sets the field bit"]
396 pub fn set_bit(self) -> &'a mut W {
397 self.bit(true)
398 }
399 #[doc = r" Clears the field bit"]
400 pub fn clear_bit(self) -> &'a mut W {
401 self.bit(false)
402 }
403 #[doc = r" Writes raw bits to the field"]
404 #[inline]
405 pub fn bit(self, value: bool) -> &'a mut W {
406 const MASK: bool = true;
407 const OFFSET: u8 = 7;
408 self.w.bits &= !((MASK as u32) << OFFSET);
409 self.w.bits |= ((value & MASK) as u32) << OFFSET;
410 self.w
411 }
412}
413#[doc = "Values that can be written to the field `TS`"]
414pub enum TSW {
415 #[doc = "Internal Trigger 0 (ITR0)"]
416 ITR0,
417 #[doc = "Internal Trigger 1 (ITR1)"]
418 ITR1,
419 #[doc = "Internal Trigger 2 (ITR2)"]
420 ITR2,
421 #[doc = "Internal Trigger 3 (ITR3)"]
422 ITR3,
423 #[doc = "TI1 Edge Detector"]
424 TI1F_ED,
425 #[doc = "Filtered Timer Input 1"]
426 TI1FP1,
427 #[doc = "Filtered Timer Input 2"]
428 TI2FP2,
429 #[doc = "External Trigger input"]
430 ETRF,
431}
432impl TSW {
433 #[allow(missing_docs)]
434 #[doc(hidden)]
435 #[inline]
436 pub fn _bits(&self) -> u8 {
437 match *self {
438 TSW::ITR0 => 0,
439 TSW::ITR1 => 1,
440 TSW::ITR2 => 2,
441 TSW::ITR3 => 3,
442 TSW::TI1F_ED => 4,
443 TSW::TI1FP1 => 5,
444 TSW::TI2FP2 => 6,
445 TSW::ETRF => 7,
446 }
447 }
448}
449#[doc = r" Proxy"]
450pub struct _TSW<'a> {
451 w: &'a mut W,
452}
453impl<'a> _TSW<'a> {
454 #[doc = r" Writes `variant` to the field"]
455 #[inline]
456 pub fn variant(self, variant: TSW) -> &'a mut W {
457 {
458 self.bits(variant._bits())
459 }
460 }
461 #[doc = "Internal Trigger 0 (ITR0)"]
462 #[inline]
463 pub fn itr0(self) -> &'a mut W {
464 self.variant(TSW::ITR0)
465 }
466 #[doc = "Internal Trigger 1 (ITR1)"]
467 #[inline]
468 pub fn itr1(self) -> &'a mut W {
469 self.variant(TSW::ITR1)
470 }
471 #[doc = "Internal Trigger 2 (ITR2)"]
472 #[inline]
473 pub fn itr2(self) -> &'a mut W {
474 self.variant(TSW::ITR2)
475 }
476 #[doc = "Internal Trigger 3 (ITR3)"]
477 #[inline]
478 pub fn itr3(self) -> &'a mut W {
479 self.variant(TSW::ITR3)
480 }
481 #[doc = "TI1 Edge Detector"]
482 #[inline]
483 pub fn ti1f_ed(self) -> &'a mut W {
484 self.variant(TSW::TI1F_ED)
485 }
486 #[doc = "Filtered Timer Input 1"]
487 #[inline]
488 pub fn ti1fp1(self) -> &'a mut W {
489 self.variant(TSW::TI1FP1)
490 }
491 #[doc = "Filtered Timer Input 2"]
492 #[inline]
493 pub fn ti2fp2(self) -> &'a mut W {
494 self.variant(TSW::TI2FP2)
495 }
496 #[doc = "External Trigger input"]
497 #[inline]
498 pub fn etrf(self) -> &'a mut W {
499 self.variant(TSW::ETRF)
500 }
501 #[doc = r" Writes raw bits to the field"]
502 #[inline]
503 pub fn bits(self, value: u8) -> &'a mut W {
504 const MASK: u8 = 7;
505 const OFFSET: u8 = 4;
506 self.w.bits &= !((MASK as u32) << OFFSET);
507 self.w.bits |= ((value & MASK) as u32) << OFFSET;
508 self.w
509 }
510}
511#[doc = "Values that can be written to the field `SMS`"]
512pub enum SMSW {
513 #[doc = "Counter disabled"]
514 DISABLED,
515 #[doc = "Encoder mode, count up/down on TI2FP1"]
516 ENCODERTI2,
517 #[doc = "Encoder mode, count up/down on TI1FP2"]
518 ENCODERTI1,
519 #[doc = "Encoder mode, count up/down on both TI1FP1 and TI2FP2"]
520 ENCODERTI1TI2,
521 #[doc = "Rising edge of the selected trigger input (TRGI) reinitializes the counter"]
522 RESET,
523 #[doc = " The counter clock is enabled when the trigger input (TRGI) is high"]
524 GATED,
525 #[doc = "The counter starts at a rising edge of the trigger TRGI "]
526 TRIGGER,
527 #[doc = " Rising edges of the selected trigger (TRGI) clock the counter"]
528 EXTERNAL,
529}
530impl SMSW {
531 #[allow(missing_docs)]
532 #[doc(hidden)]
533 #[inline]
534 pub fn _bits(&self) -> u8 {
535 match *self {
536 SMSW::DISABLED => 0,
537 SMSW::ENCODERTI2 => 1,
538 SMSW::ENCODERTI1 => 2,
539 SMSW::ENCODERTI1TI2 => 3,
540 SMSW::RESET => 4,
541 SMSW::GATED => 5,
542 SMSW::TRIGGER => 6,
543 SMSW::EXTERNAL => 7,
544 }
545 }
546}
547#[doc = r" Proxy"]
548pub struct _SMSW<'a> {
549 w: &'a mut W,
550}
551impl<'a> _SMSW<'a> {
552 #[doc = r" Writes `variant` to the field"]
553 #[inline]
554 pub fn variant(self, variant: SMSW) -> &'a mut W {
555 {
556 self.bits(variant._bits())
557 }
558 }
559 #[doc = "Counter disabled"]
560 #[inline]
561 pub fn disabled(self) -> &'a mut W {
562 self.variant(SMSW::DISABLED)
563 }
564 #[doc = "Encoder mode, count up/down on TI2FP1"]
565 #[inline]
566 pub fn encoder_ti2(self) -> &'a mut W {
567 self.variant(SMSW::ENCODERTI2)
568 }
569 #[doc = "Encoder mode, count up/down on TI1FP2"]
570 #[inline]
571 pub fn encoder_ti1(self) -> &'a mut W {
572 self.variant(SMSW::ENCODERTI1)
573 }
574 #[doc = "Encoder mode, count up/down on both TI1FP1 and TI2FP2"]
575 #[inline]
576 pub fn encoder_ti1ti2(self) -> &'a mut W {
577 self.variant(SMSW::ENCODERTI1TI2)
578 }
579 #[doc = "Rising edge of the selected trigger input (TRGI) reinitializes the counter"]
580 #[inline]
581 pub fn reset(self) -> &'a mut W {
582 self.variant(SMSW::RESET)
583 }
584 #[doc = "The counter clock is enabled when the trigger input (TRGI) is high"]
585 #[inline]
586 pub fn gated(self) -> &'a mut W {
587 self.variant(SMSW::GATED)
588 }
589 #[doc = "The counter starts at a rising edge of the trigger TRGI"]
590 #[inline]
591 pub fn trigger(self) -> &'a mut W {
592 self.variant(SMSW::TRIGGER)
593 }
594 #[doc = "Rising edges of the selected trigger (TRGI) clock the counter"]
595 #[inline]
596 pub fn external(self) -> &'a mut W {
597 self.variant(SMSW::EXTERNAL)
598 }
599 #[doc = r" Writes raw bits to the field"]
600 #[inline]
601 pub fn bits(self, value: u8) -> &'a mut W {
602 const MASK: u8 = 7;
603 const OFFSET: u8 = 0;
604 self.w.bits &= !((MASK as u32) << OFFSET);
605 self.w.bits |= ((value & MASK) as u32) << OFFSET;
606 self.w
607 }
608}
609impl R {
610 #[doc = r" Value of the register as raw bits"]
611 #[inline]
612 pub fn bits(&self) -> u32 {
613 self.bits
614 }
615 #[doc = "Bit 15 - External trigger polarity"]
616 #[inline]
617 pub fn etp(&self) -> ETPR {
618 let bits = {
619 const MASK: bool = true;
620 const OFFSET: u8 = 15;
621 ((self.bits >> OFFSET) & MASK as u32) != 0
622 };
623 ETPR { bits }
624 }
625 #[doc = "Bit 14 - External clock enable"]
626 #[inline]
627 pub fn ece(&self) -> ECER {
628 let bits = {
629 const MASK: bool = true;
630 const OFFSET: u8 = 14;
631 ((self.bits >> OFFSET) & MASK as u32) != 0
632 };
633 ECER { bits }
634 }
635 #[doc = "Bits 12:13 - External trigger prescaler"]
636 #[inline]
637 pub fn etps(&self) -> ETPSR {
638 let bits = {
639 const MASK: u8 = 3;
640 const OFFSET: u8 = 12;
641 ((self.bits >> OFFSET) & MASK as u32) as u8
642 };
643 ETPSR { bits }
644 }
645 #[doc = "Bits 8:11 - External trigger filter"]
646 #[inline]
647 pub fn etf(&self) -> ETFR {
648 let bits = {
649 const MASK: u8 = 15;
650 const OFFSET: u8 = 8;
651 ((self.bits >> OFFSET) & MASK as u32) as u8
652 };
653 ETFR { bits }
654 }
655 #[doc = "Bit 7 - Master/Slave mode"]
656 #[inline]
657 pub fn msm(&self) -> MSMR {
658 let bits = {
659 const MASK: bool = true;
660 const OFFSET: u8 = 7;
661 ((self.bits >> OFFSET) & MASK as u32) != 0
662 };
663 MSMR { bits }
664 }
665 #[doc = "Bits 4:6 - Trigger selection"]
666 #[inline]
667 pub fn ts(&self) -> TSR {
668 TSR::_from({
669 const MASK: u8 = 7;
670 const OFFSET: u8 = 4;
671 ((self.bits >> OFFSET) & MASK as u32) as u8
672 })
673 }
674 #[doc = "Bits 0:2 - Slave mode selection"]
675 #[inline]
676 pub fn sms(&self) -> SMSR {
677 SMSR::_from({
678 const MASK: u8 = 7;
679 const OFFSET: u8 = 0;
680 ((self.bits >> OFFSET) & MASK as u32) as u8
681 })
682 }
683}
684impl W {
685 #[doc = r" Reset value of the register"]
686 #[inline]
687 pub fn reset_value() -> W {
688 W { bits: 0 }
689 }
690 #[doc = r" Writes raw bits to the register"]
691 #[inline]
692 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
693 self.bits = bits;
694 self
695 }
696 #[doc = "Bit 15 - External trigger polarity"]
697 #[inline]
698 pub fn etp(&mut self) -> _ETPW {
699 _ETPW { w: self }
700 }
701 #[doc = "Bit 14 - External clock enable"]
702 #[inline]
703 pub fn ece(&mut self) -> _ECEW {
704 _ECEW { w: self }
705 }
706 #[doc = "Bits 12:13 - External trigger prescaler"]
707 #[inline]
708 pub fn etps(&mut self) -> _ETPSW {
709 _ETPSW { w: self }
710 }
711 #[doc = "Bits 8:11 - External trigger filter"]
712 #[inline]
713 pub fn etf(&mut self) -> _ETFW {
714 _ETFW { w: self }
715 }
716 #[doc = "Bit 7 - Master/Slave mode"]
717 #[inline]
718 pub fn msm(&mut self) -> _MSMW {
719 _MSMW { w: self }
720 }
721 #[doc = "Bits 4:6 - Trigger selection"]
722 #[inline]
723 pub fn ts(&mut self) -> _TSW {
724 _TSW { w: self }
725 }
726 #[doc = "Bits 0:2 - Slave mode selection"]
727 #[inline]
728 pub fn sms(&mut self) -> _SMSW {
729 _SMSW { w: self }
730 }
731}