1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CR1 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `CKD`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum CKDR {
48 #[doc = "Clock is not divided"]
49 NODIV,
50 #[doc = "Clock is divided by 2"]
51 DIV2,
52 #[doc = "Clock is divided by 4"]
53 DIV4,
54 #[doc = r" Reserved"]
55 _Reserved(u8),
56}
57impl CKDR {
58 #[doc = r" Value of the field as raw bits"]
59 #[inline]
60 pub fn bits(&self) -> u8 {
61 match *self {
62 CKDR::NODIV => 0,
63 CKDR::DIV2 => 1,
64 CKDR::DIV4 => 2,
65 CKDR::_Reserved(bits) => bits,
66 }
67 }
68 #[allow(missing_docs)]
69 #[doc(hidden)]
70 #[inline]
71 pub fn _from(value: u8) -> CKDR {
72 match value {
73 0 => CKDR::NODIV,
74 1 => CKDR::DIV2,
75 2 => CKDR::DIV4,
76 i => CKDR::_Reserved(i),
77 }
78 }
79 #[doc = "Checks if the value of the field is `NODIV`"]
80 #[inline]
81 pub fn is_no_div(&self) -> bool {
82 *self == CKDR::NODIV
83 }
84 #[doc = "Checks if the value of the field is `DIV2`"]
85 #[inline]
86 pub fn is_div2(&self) -> bool {
87 *self == CKDR::DIV2
88 }
89 #[doc = "Checks if the value of the field is `DIV4`"]
90 #[inline]
91 pub fn is_div4(&self) -> bool {
92 *self == CKDR::DIV4
93 }
94}
95#[doc = r" Value of the field"]
96pub struct ARPER {
97 bits: bool,
98}
99impl ARPER {
100 #[doc = r" Value of the field as raw bits"]
101 #[inline]
102 pub fn bit(&self) -> bool {
103 self.bits
104 }
105 #[doc = r" Returns `true` if the bit is clear (0)"]
106 #[inline]
107 pub fn bit_is_clear(&self) -> bool {
108 !self.bit()
109 }
110 #[doc = r" Returns `true` if the bit is set (1)"]
111 #[inline]
112 pub fn bit_is_set(&self) -> bool {
113 self.bit()
114 }
115}
116#[doc = r" Value of the field"]
117pub struct CMSR {
118 bits: u8,
119}
120impl CMSR {
121 #[doc = r" Value of the field as raw bits"]
122 #[inline]
123 pub fn bits(&self) -> u8 {
124 self.bits
125 }
126}
127#[doc = "Possible values of the field `DIR`"]
128#[derive(Clone, Copy, Debug, PartialEq)]
129pub enum DIRR {
130 #[doc = "Up"]
131 UP,
132 #[doc = "Down"]
133 DOWN,
134}
135impl DIRR {
136 #[doc = r" Returns `true` if the bit is clear (0)"]
137 #[inline]
138 pub fn bit_is_clear(&self) -> bool {
139 !self.bit()
140 }
141 #[doc = r" Returns `true` if the bit is set (1)"]
142 #[inline]
143 pub fn bit_is_set(&self) -> bool {
144 self.bit()
145 }
146 #[doc = r" Value of the field as raw bits"]
147 #[inline]
148 pub fn bit(&self) -> bool {
149 match *self {
150 DIRR::UP => false,
151 DIRR::DOWN => true,
152 }
153 }
154 #[allow(missing_docs)]
155 #[doc(hidden)]
156 #[inline]
157 pub fn _from(value: bool) -> DIRR {
158 match value {
159 false => DIRR::UP,
160 true => DIRR::DOWN,
161 }
162 }
163 #[doc = "Checks if the value of the field is `UP`"]
164 #[inline]
165 pub fn is_up(&self) -> bool {
166 *self == DIRR::UP
167 }
168 #[doc = "Checks if the value of the field is `DOWN`"]
169 #[inline]
170 pub fn is_down(&self) -> bool {
171 *self == DIRR::DOWN
172 }
173}
174#[doc = "Possible values of the field `OPM`"]
175#[derive(Clone, Copy, Debug, PartialEq)]
176pub enum OPMR {
177 #[doc = "Counter is not stopped at update event"]
178 CONTINUOUS,
179 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
180 ONEPULSE,
181}
182impl OPMR {
183 #[doc = r" Returns `true` if the bit is clear (0)"]
184 #[inline]
185 pub fn bit_is_clear(&self) -> bool {
186 !self.bit()
187 }
188 #[doc = r" Returns `true` if the bit is set (1)"]
189 #[inline]
190 pub fn bit_is_set(&self) -> bool {
191 self.bit()
192 }
193 #[doc = r" Value of the field as raw bits"]
194 #[inline]
195 pub fn bit(&self) -> bool {
196 match *self {
197 OPMR::CONTINUOUS => false,
198 OPMR::ONEPULSE => true,
199 }
200 }
201 #[allow(missing_docs)]
202 #[doc(hidden)]
203 #[inline]
204 pub fn _from(value: bool) -> OPMR {
205 match value {
206 false => OPMR::CONTINUOUS,
207 true => OPMR::ONEPULSE,
208 }
209 }
210 #[doc = "Checks if the value of the field is `CONTINUOUS`"]
211 #[inline]
212 pub fn is_continuous(&self) -> bool {
213 *self == OPMR::CONTINUOUS
214 }
215 #[doc = "Checks if the value of the field is `ONEPULSE`"]
216 #[inline]
217 pub fn is_one_pulse(&self) -> bool {
218 *self == OPMR::ONEPULSE
219 }
220}
221#[doc = r" Value of the field"]
222pub struct URSR {
223 bits: bool,
224}
225impl URSR {
226 #[doc = r" Value of the field as raw bits"]
227 #[inline]
228 pub fn bit(&self) -> bool {
229 self.bits
230 }
231 #[doc = r" Returns `true` if the bit is clear (0)"]
232 #[inline]
233 pub fn bit_is_clear(&self) -> bool {
234 !self.bit()
235 }
236 #[doc = r" Returns `true` if the bit is set (1)"]
237 #[inline]
238 pub fn bit_is_set(&self) -> bool {
239 self.bit()
240 }
241}
242#[doc = r" Value of the field"]
243pub struct UDISR {
244 bits: bool,
245}
246impl UDISR {
247 #[doc = r" Value of the field as raw bits"]
248 #[inline]
249 pub fn bit(&self) -> bool {
250 self.bits
251 }
252 #[doc = r" Returns `true` if the bit is clear (0)"]
253 #[inline]
254 pub fn bit_is_clear(&self) -> bool {
255 !self.bit()
256 }
257 #[doc = r" Returns `true` if the bit is set (1)"]
258 #[inline]
259 pub fn bit_is_set(&self) -> bool {
260 self.bit()
261 }
262}
263#[doc = "Possible values of the field `CEN`"]
264#[derive(Clone, Copy, Debug, PartialEq)]
265pub enum CENR {
266 #[doc = "Counter disabled"]
267 DISABLED,
268 #[doc = "Counter enabled"]
269 ENABLED,
270}
271impl CENR {
272 #[doc = r" Returns `true` if the bit is clear (0)"]
273 #[inline]
274 pub fn bit_is_clear(&self) -> bool {
275 !self.bit()
276 }
277 #[doc = r" Returns `true` if the bit is set (1)"]
278 #[inline]
279 pub fn bit_is_set(&self) -> bool {
280 self.bit()
281 }
282 #[doc = r" Value of the field as raw bits"]
283 #[inline]
284 pub fn bit(&self) -> bool {
285 match *self {
286 CENR::DISABLED => false,
287 CENR::ENABLED => true,
288 }
289 }
290 #[allow(missing_docs)]
291 #[doc(hidden)]
292 #[inline]
293 pub fn _from(value: bool) -> CENR {
294 match value {
295 false => CENR::DISABLED,
296 true => CENR::ENABLED,
297 }
298 }
299 #[doc = "Checks if the value of the field is `DISABLED`"]
300 #[inline]
301 pub fn is_disabled(&self) -> bool {
302 *self == CENR::DISABLED
303 }
304 #[doc = "Checks if the value of the field is `ENABLED`"]
305 #[inline]
306 pub fn is_enabled(&self) -> bool {
307 *self == CENR::ENABLED
308 }
309}
310#[doc = "Values that can be written to the field `CKD`"]
311pub enum CKDW {
312 #[doc = "Clock is not divided"]
313 NODIV,
314 #[doc = "Clock is divided by 2"]
315 DIV2,
316 #[doc = "Clock is divided by 4"]
317 DIV4,
318}
319impl CKDW {
320 #[allow(missing_docs)]
321 #[doc(hidden)]
322 #[inline]
323 pub fn _bits(&self) -> u8 {
324 match *self {
325 CKDW::NODIV => 0,
326 CKDW::DIV2 => 1,
327 CKDW::DIV4 => 2,
328 }
329 }
330}
331#[doc = r" Proxy"]
332pub struct _CKDW<'a> {
333 w: &'a mut W,
334}
335impl<'a> _CKDW<'a> {
336 #[doc = r" Writes `variant` to the field"]
337 #[inline]
338 pub fn variant(self, variant: CKDW) -> &'a mut W {
339 unsafe { self.bits(variant._bits()) }
340 }
341 #[doc = "Clock is not divided"]
342 #[inline]
343 pub fn no_div(self) -> &'a mut W {
344 self.variant(CKDW::NODIV)
345 }
346 #[doc = "Clock is divided by 2"]
347 #[inline]
348 pub fn div2(self) -> &'a mut W {
349 self.variant(CKDW::DIV2)
350 }
351 #[doc = "Clock is divided by 4"]
352 #[inline]
353 pub fn div4(self) -> &'a mut W {
354 self.variant(CKDW::DIV4)
355 }
356 #[doc = r" Writes raw bits to the field"]
357 #[inline]
358 pub unsafe fn bits(self, value: u8) -> &'a mut W {
359 const MASK: u8 = 3;
360 const OFFSET: u8 = 8;
361 self.w.bits &= !((MASK as u32) << OFFSET);
362 self.w.bits |= ((value & MASK) as u32) << OFFSET;
363 self.w
364 }
365}
366#[doc = r" Proxy"]
367pub struct _ARPEW<'a> {
368 w: &'a mut W,
369}
370impl<'a> _ARPEW<'a> {
371 #[doc = r" Sets the field bit"]
372 pub fn set_bit(self) -> &'a mut W {
373 self.bit(true)
374 }
375 #[doc = r" Clears the field bit"]
376 pub fn clear_bit(self) -> &'a mut W {
377 self.bit(false)
378 }
379 #[doc = r" Writes raw bits to the field"]
380 #[inline]
381 pub fn bit(self, value: bool) -> &'a mut W {
382 const MASK: bool = true;
383 const OFFSET: u8 = 7;
384 self.w.bits &= !((MASK as u32) << OFFSET);
385 self.w.bits |= ((value & MASK) as u32) << OFFSET;
386 self.w
387 }
388}
389#[doc = r" Proxy"]
390pub struct _CMSW<'a> {
391 w: &'a mut W,
392}
393impl<'a> _CMSW<'a> {
394 #[doc = r" Writes raw bits to the field"]
395 #[inline]
396 pub unsafe fn bits(self, value: u8) -> &'a mut W {
397 const MASK: u8 = 3;
398 const OFFSET: u8 = 5;
399 self.w.bits &= !((MASK as u32) << OFFSET);
400 self.w.bits |= ((value & MASK) as u32) << OFFSET;
401 self.w
402 }
403}
404#[doc = "Values that can be written to the field `DIR`"]
405pub enum DIRW {
406 #[doc = "Up"]
407 UP,
408 #[doc = "Down"]
409 DOWN,
410}
411impl DIRW {
412 #[allow(missing_docs)]
413 #[doc(hidden)]
414 #[inline]
415 pub fn _bits(&self) -> bool {
416 match *self {
417 DIRW::UP => false,
418 DIRW::DOWN => true,
419 }
420 }
421}
422#[doc = r" Proxy"]
423pub struct _DIRW<'a> {
424 w: &'a mut W,
425}
426impl<'a> _DIRW<'a> {
427 #[doc = r" Writes `variant` to the field"]
428 #[inline]
429 pub fn variant(self, variant: DIRW) -> &'a mut W {
430 {
431 self.bit(variant._bits())
432 }
433 }
434 #[doc = "Up"]
435 #[inline]
436 pub fn up(self) -> &'a mut W {
437 self.variant(DIRW::UP)
438 }
439 #[doc = "Down"]
440 #[inline]
441 pub fn down(self) -> &'a mut W {
442 self.variant(DIRW::DOWN)
443 }
444 #[doc = r" Sets the field bit"]
445 pub fn set_bit(self) -> &'a mut W {
446 self.bit(true)
447 }
448 #[doc = r" Clears the field bit"]
449 pub fn clear_bit(self) -> &'a mut W {
450 self.bit(false)
451 }
452 #[doc = r" Writes raw bits to the field"]
453 #[inline]
454 pub fn bit(self, value: bool) -> &'a mut W {
455 const MASK: bool = true;
456 const OFFSET: u8 = 4;
457 self.w.bits &= !((MASK as u32) << OFFSET);
458 self.w.bits |= ((value & MASK) as u32) << OFFSET;
459 self.w
460 }
461}
462#[doc = "Values that can be written to the field `OPM`"]
463pub enum OPMW {
464 #[doc = "Counter is not stopped at update event"]
465 CONTINUOUS,
466 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
467 ONEPULSE,
468}
469impl OPMW {
470 #[allow(missing_docs)]
471 #[doc(hidden)]
472 #[inline]
473 pub fn _bits(&self) -> bool {
474 match *self {
475 OPMW::CONTINUOUS => false,
476 OPMW::ONEPULSE => true,
477 }
478 }
479}
480#[doc = r" Proxy"]
481pub struct _OPMW<'a> {
482 w: &'a mut W,
483}
484impl<'a> _OPMW<'a> {
485 #[doc = r" Writes `variant` to the field"]
486 #[inline]
487 pub fn variant(self, variant: OPMW) -> &'a mut W {
488 {
489 self.bit(variant._bits())
490 }
491 }
492 #[doc = "Counter is not stopped at update event"]
493 #[inline]
494 pub fn continuous(self) -> &'a mut W {
495 self.variant(OPMW::CONTINUOUS)
496 }
497 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
498 #[inline]
499 pub fn one_pulse(self) -> &'a mut W {
500 self.variant(OPMW::ONEPULSE)
501 }
502 #[doc = r" Sets the field bit"]
503 pub fn set_bit(self) -> &'a mut W {
504 self.bit(true)
505 }
506 #[doc = r" Clears the field bit"]
507 pub fn clear_bit(self) -> &'a mut W {
508 self.bit(false)
509 }
510 #[doc = r" Writes raw bits to the field"]
511 #[inline]
512 pub fn bit(self, value: bool) -> &'a mut W {
513 const MASK: bool = true;
514 const OFFSET: u8 = 3;
515 self.w.bits &= !((MASK as u32) << OFFSET);
516 self.w.bits |= ((value & MASK) as u32) << OFFSET;
517 self.w
518 }
519}
520#[doc = r" Proxy"]
521pub struct _URSW<'a> {
522 w: &'a mut W,
523}
524impl<'a> _URSW<'a> {
525 #[doc = r" Sets the field bit"]
526 pub fn set_bit(self) -> &'a mut W {
527 self.bit(true)
528 }
529 #[doc = r" Clears the field bit"]
530 pub fn clear_bit(self) -> &'a mut W {
531 self.bit(false)
532 }
533 #[doc = r" Writes raw bits to the field"]
534 #[inline]
535 pub fn bit(self, value: bool) -> &'a mut W {
536 const MASK: bool = true;
537 const OFFSET: u8 = 2;
538 self.w.bits &= !((MASK as u32) << OFFSET);
539 self.w.bits |= ((value & MASK) as u32) << OFFSET;
540 self.w
541 }
542}
543#[doc = r" Proxy"]
544pub struct _UDISW<'a> {
545 w: &'a mut W,
546}
547impl<'a> _UDISW<'a> {
548 #[doc = r" Sets the field bit"]
549 pub fn set_bit(self) -> &'a mut W {
550 self.bit(true)
551 }
552 #[doc = r" Clears the field bit"]
553 pub fn clear_bit(self) -> &'a mut W {
554 self.bit(false)
555 }
556 #[doc = r" Writes raw bits to the field"]
557 #[inline]
558 pub fn bit(self, value: bool) -> &'a mut W {
559 const MASK: bool = true;
560 const OFFSET: u8 = 1;
561 self.w.bits &= !((MASK as u32) << OFFSET);
562 self.w.bits |= ((value & MASK) as u32) << OFFSET;
563 self.w
564 }
565}
566#[doc = "Values that can be written to the field `CEN`"]
567pub enum CENW {
568 #[doc = "Counter disabled"]
569 DISABLED,
570 #[doc = "Counter enabled"]
571 ENABLED,
572}
573impl CENW {
574 #[allow(missing_docs)]
575 #[doc(hidden)]
576 #[inline]
577 pub fn _bits(&self) -> bool {
578 match *self {
579 CENW::DISABLED => false,
580 CENW::ENABLED => true,
581 }
582 }
583}
584#[doc = r" Proxy"]
585pub struct _CENW<'a> {
586 w: &'a mut W,
587}
588impl<'a> _CENW<'a> {
589 #[doc = r" Writes `variant` to the field"]
590 #[inline]
591 pub fn variant(self, variant: CENW) -> &'a mut W {
592 {
593 self.bit(variant._bits())
594 }
595 }
596 #[doc = "Counter disabled"]
597 #[inline]
598 pub fn disabled(self) -> &'a mut W {
599 self.variant(CENW::DISABLED)
600 }
601 #[doc = "Counter enabled"]
602 #[inline]
603 pub fn enabled(self) -> &'a mut W {
604 self.variant(CENW::ENABLED)
605 }
606 #[doc = r" Sets the field bit"]
607 pub fn set_bit(self) -> &'a mut W {
608 self.bit(true)
609 }
610 #[doc = r" Clears the field bit"]
611 pub fn clear_bit(self) -> &'a mut W {
612 self.bit(false)
613 }
614 #[doc = r" Writes raw bits to the field"]
615 #[inline]
616 pub fn bit(self, value: bool) -> &'a mut W {
617 const MASK: bool = true;
618 const OFFSET: u8 = 0;
619 self.w.bits &= !((MASK as u32) << OFFSET);
620 self.w.bits |= ((value & MASK) as u32) << OFFSET;
621 self.w
622 }
623}
624impl R {
625 #[doc = r" Value of the register as raw bits"]
626 #[inline]
627 pub fn bits(&self) -> u32 {
628 self.bits
629 }
630 #[doc = "Bits 8:9 - Division ratio between the timer clock (CK_INT) frequency and sampling clock"]
631 #[inline]
632 pub fn ckd(&self) -> CKDR {
633 CKDR::_from({
634 const MASK: u8 = 3;
635 const OFFSET: u8 = 8;
636 ((self.bits >> OFFSET) & MASK as u32) as u8
637 })
638 }
639 #[doc = "Bit 7 - Auto-reload preload enable"]
640 #[inline]
641 pub fn arpe(&self) -> ARPER {
642 let bits = {
643 const MASK: bool = true;
644 const OFFSET: u8 = 7;
645 ((self.bits >> OFFSET) & MASK as u32) != 0
646 };
647 ARPER { bits }
648 }
649 #[doc = "Bits 5:6 - Center-aligned mode selection"]
650 #[inline]
651 pub fn cms(&self) -> CMSR {
652 let bits = {
653 const MASK: u8 = 3;
654 const OFFSET: u8 = 5;
655 ((self.bits >> OFFSET) & MASK as u32) as u8
656 };
657 CMSR { bits }
658 }
659 #[doc = "Bit 4 - Direction"]
660 #[inline]
661 pub fn dir(&self) -> DIRR {
662 DIRR::_from({
663 const MASK: bool = true;
664 const OFFSET: u8 = 4;
665 ((self.bits >> OFFSET) & MASK as u32) != 0
666 })
667 }
668 #[doc = "Bit 3 - One-pulse mode"]
669 #[inline]
670 pub fn opm(&self) -> OPMR {
671 OPMR::_from({
672 const MASK: bool = true;
673 const OFFSET: u8 = 3;
674 ((self.bits >> OFFSET) & MASK as u32) != 0
675 })
676 }
677 #[doc = "Bit 2 - Update request source"]
678 #[inline]
679 pub fn urs(&self) -> URSR {
680 let bits = {
681 const MASK: bool = true;
682 const OFFSET: u8 = 2;
683 ((self.bits >> OFFSET) & MASK as u32) != 0
684 };
685 URSR { bits }
686 }
687 #[doc = "Bit 1 - Update disable"]
688 #[inline]
689 pub fn udis(&self) -> UDISR {
690 let bits = {
691 const MASK: bool = true;
692 const OFFSET: u8 = 1;
693 ((self.bits >> OFFSET) & MASK as u32) != 0
694 };
695 UDISR { bits }
696 }
697 #[doc = "Bit 0 - Counter enable"]
698 #[inline]
699 pub fn cen(&self) -> CENR {
700 CENR::_from({
701 const MASK: bool = true;
702 const OFFSET: u8 = 0;
703 ((self.bits >> OFFSET) & MASK as u32) != 0
704 })
705 }
706}
707impl W {
708 #[doc = r" Reset value of the register"]
709 #[inline]
710 pub fn reset_value() -> W {
711 W { bits: 0 }
712 }
713 #[doc = r" Writes raw bits to the register"]
714 #[inline]
715 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
716 self.bits = bits;
717 self
718 }
719 #[doc = "Bits 8:9 - Division ratio between the timer clock (CK_INT) frequency and sampling clock"]
720 #[inline]
721 pub fn ckd(&mut self) -> _CKDW {
722 _CKDW { w: self }
723 }
724 #[doc = "Bit 7 - Auto-reload preload enable"]
725 #[inline]
726 pub fn arpe(&mut self) -> _ARPEW {
727 _ARPEW { w: self }
728 }
729 #[doc = "Bits 5:6 - Center-aligned mode selection"]
730 #[inline]
731 pub fn cms(&mut self) -> _CMSW {
732 _CMSW { w: self }
733 }
734 #[doc = "Bit 4 - Direction"]
735 #[inline]
736 pub fn dir(&mut self) -> _DIRW {
737 _DIRW { w: self }
738 }
739 #[doc = "Bit 3 - One-pulse mode"]
740 #[inline]
741 pub fn opm(&mut self) -> _OPMW {
742 _OPMW { w: self }
743 }
744 #[doc = "Bit 2 - Update request source"]
745 #[inline]
746 pub fn urs(&mut self) -> _URSW {
747 _URSW { w: self }
748 }
749 #[doc = "Bit 1 - Update disable"]
750 #[inline]
751 pub fn udis(&mut self) -> _UDISW {
752 _UDISW { w: self }
753 }
754 #[doc = "Bit 0 - Counter enable"]
755 #[inline]
756 pub fn cen(&mut self) -> _CENW {
757 _CENW { w: self }
758 }
759}