#![doc = "Peripheral access API for STM32F103 microcontrollers (generated using svd2rust v0.37.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 4;
#[allow(unused_imports)]
use generic::*;
#[doc = r"Common register and bit access and modify traits"]
pub mod generic;
#[cfg(feature = "rt")]
extern "C" {
fn WWDG();
fn PVD();
fn TAMPER();
fn RTC();
fn FLASH();
fn RCC();
fn EXTI0();
fn EXTI1();
fn EXTI2();
fn EXTI3();
fn EXTI4();
fn DMA1_Channel1();
fn DMA1_Channel2();
fn DMA1_Channel3();
fn DMA1_Channel4();
fn DMA1_Channel5();
fn DMA1_Channel6();
fn DMA1_Channel7();
fn ADC1_2();
fn USB_HP_CAN_TX();
fn USB_LP_CAN_RX0();
fn CAN_RX1();
fn CAN_SCE();
fn EXTI9_5();
fn TIM1_BRK();
fn TIM1_UP();
fn TIM1_TRG_COM();
fn TIM1_CC();
fn TIM2();
fn TIM3();
fn TIM4();
fn I2C1_EV();
fn I2C1_ER();
fn I2C2_EV();
fn I2C2_ER();
fn SPI1();
fn SPI2();
fn USART1();
fn USART2();
fn USART3();
fn EXTI15_10();
fn RTCAlarm();
fn TIM8_BRK();
fn TIM8_UP();
fn TIM8_TRG_COM();
fn TIM8_CC();
fn ADC3();
fn FSMC();
fn SDIO();
fn TIM5();
fn SPI3();
fn UART4();
fn UART5();
fn TIM6();
fn TIM7();
fn DMA2_Channel1();
fn DMA2_Channel2();
fn DMA2_Channel3();
fn DMA2_Channel4_5();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 60] = [
Vector { _handler: WWDG },
Vector { _handler: PVD },
Vector { _handler: TAMPER },
Vector { _handler: RTC },
Vector { _handler: FLASH },
Vector { _handler: RCC },
Vector { _handler: EXTI0 },
Vector { _handler: EXTI1 },
Vector { _handler: EXTI2 },
Vector { _handler: EXTI3 },
Vector { _handler: EXTI4 },
Vector {
_handler: DMA1_Channel1,
},
Vector {
_handler: DMA1_Channel2,
},
Vector {
_handler: DMA1_Channel3,
},
Vector {
_handler: DMA1_Channel4,
},
Vector {
_handler: DMA1_Channel5,
},
Vector {
_handler: DMA1_Channel6,
},
Vector {
_handler: DMA1_Channel7,
},
Vector { _handler: ADC1_2 },
Vector {
_handler: USB_HP_CAN_TX,
},
Vector {
_handler: USB_LP_CAN_RX0,
},
Vector { _handler: CAN_RX1 },
Vector { _handler: CAN_SCE },
Vector { _handler: EXTI9_5 },
Vector { _handler: TIM1_BRK },
Vector { _handler: TIM1_UP },
Vector {
_handler: TIM1_TRG_COM,
},
Vector { _handler: TIM1_CC },
Vector { _handler: TIM2 },
Vector { _handler: TIM3 },
Vector { _handler: TIM4 },
Vector { _handler: I2C1_EV },
Vector { _handler: I2C1_ER },
Vector { _handler: I2C2_EV },
Vector { _handler: I2C2_ER },
Vector { _handler: SPI1 },
Vector { _handler: SPI2 },
Vector { _handler: USART1 },
Vector { _handler: USART2 },
Vector { _handler: USART3 },
Vector {
_handler: EXTI15_10,
},
Vector { _handler: RTCAlarm },
Vector { _reserved: 0 },
Vector { _handler: TIM8_BRK },
Vector { _handler: TIM8_UP },
Vector {
_handler: TIM8_TRG_COM,
},
Vector { _handler: TIM8_CC },
Vector { _handler: ADC3 },
Vector { _handler: FSMC },
Vector { _handler: SDIO },
Vector { _handler: TIM5 },
Vector { _handler: SPI3 },
Vector { _handler: UART4 },
Vector { _handler: UART5 },
Vector { _handler: TIM6 },
Vector { _handler: TIM7 },
Vector {
_handler: DMA2_Channel1,
},
Vector {
_handler: DMA2_Channel2,
},
Vector {
_handler: DMA2_Channel3,
},
Vector {
_handler: DMA2_Channel4_5,
},
];
#[doc = r"Enumeration of all the interrupts."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
#[doc = "0 - Window Watchdog interrupt"]
WWDG = 0,
#[doc = "1 - PVD through EXTI line detection interrupt"]
PVD = 1,
#[doc = "2 - Tamper interrupt"]
TAMPER = 2,
#[doc = "3 - RTC global interrupt"]
RTC = 3,
#[doc = "4 - Flash global interrupt"]
FLASH = 4,
#[doc = "5 - RCC global interrupt"]
RCC = 5,
#[doc = "6 - EXTI Line0 interrupt"]
EXTI0 = 6,
#[doc = "7 - EXTI Line1 interrupt"]
EXTI1 = 7,
#[doc = "8 - EXTI Line2 interrupt"]
EXTI2 = 8,
#[doc = "9 - EXTI Line3 interrupt"]
EXTI3 = 9,
#[doc = "10 - EXTI Line4 interrupt"]
EXTI4 = 10,
#[doc = "11 - DMA1 Channel1 global interrupt"]
DMA1_Channel1 = 11,
#[doc = "12 - DMA1 Channel2 global interrupt"]
DMA1_Channel2 = 12,
#[doc = "13 - DMA1 Channel3 global interrupt"]
DMA1_Channel3 = 13,
#[doc = "14 - DMA1 Channel4 global interrupt"]
DMA1_Channel4 = 14,
#[doc = "15 - DMA1 Channel5 global interrupt"]
DMA1_Channel5 = 15,
#[doc = "16 - DMA1 Channel6 global interrupt"]
DMA1_Channel6 = 16,
#[doc = "17 - DMA1 Channel7 global interrupt"]
DMA1_Channel7 = 17,
#[doc = "18 - ADC1 and ADC2 global interrupt"]
ADC1_2 = 18,
#[doc = "19 - USB High Priority or CAN TX interrupts"]
USB_HP_CAN_TX = 19,
#[doc = "20 - USB Low Priority or CAN RX0 interrupts"]
USB_LP_CAN_RX0 = 20,
#[doc = "21 - CAN RX1 interrupt"]
CAN_RX1 = 21,
#[doc = "22 - CAN SCE interrupt"]
CAN_SCE = 22,
#[doc = "23 - EXTI Line\\[9:5\\] interrupts"]
EXTI9_5 = 23,
#[doc = "24 - TIM1 Break interrupt"]
TIM1_BRK = 24,
#[doc = "25 - TIM1 Update interrupt"]
TIM1_UP = 25,
#[doc = "26 - TIM1 Trigger and Commutation interrupts"]
TIM1_TRG_COM = 26,
#[doc = "27 - TIM1 Capture Compare interrupt"]
TIM1_CC = 27,
#[doc = "28 - TIM2 global interrupt"]
TIM2 = 28,
#[doc = "29 - TIM3 global interrupt"]
TIM3 = 29,
#[doc = "30 - TIM4 global interrupt"]
TIM4 = 30,
#[doc = "31 - I2C1 event interrupt"]
I2C1_EV = 31,
#[doc = "32 - I2C1 error interrupt"]
I2C1_ER = 32,
#[doc = "33 - I2C2 event interrupt"]
I2C2_EV = 33,
#[doc = "34 - I2C2 error interrupt"]
I2C2_ER = 34,
#[doc = "35 - SPI1 global interrupt"]
SPI1 = 35,
#[doc = "36 - SPI2 global interrupt"]
SPI2 = 36,
#[doc = "37 - USART1 global interrupt"]
USART1 = 37,
#[doc = "38 - USART2 global interrupt"]
USART2 = 38,
#[doc = "39 - USART3 global interrupt"]
USART3 = 39,
#[doc = "40 - EXTI Line\\[15:10\\] interrupts"]
EXTI15_10 = 40,
#[doc = "41 - RTC Alarms through EXTI line interrupt"]
RTCAlarm = 41,
#[doc = "43 - TIM8 Break interrupt"]
TIM8_BRK = 43,
#[doc = "44 - TIM8 Update interrupt"]
TIM8_UP = 44,
#[doc = "45 - TIM8 Trigger and Commutation interrupts"]
TIM8_TRG_COM = 45,
#[doc = "46 - TIM8 Capture Compare interrupt"]
TIM8_CC = 46,
#[doc = "47 - ADC3 global interrupt"]
ADC3 = 47,
#[doc = "48 - FSMC global interrupt"]
FSMC = 48,
#[doc = "49 - SDIO global interrupt"]
SDIO = 49,
#[doc = "50 - TIM5 global interrupt"]
TIM5 = 50,
#[doc = "51 - SPI3 global interrupt"]
SPI3 = 51,
#[doc = "52 - UART4 global interrupt"]
UART4 = 52,
#[doc = "53 - UART5 global interrupt"]
UART5 = 53,
#[doc = "54 - TIM6 global interrupt"]
TIM6 = 54,
#[doc = "55 - TIM7 global interrupt"]
TIM7 = 55,
#[doc = "56 - DMA2 Channel1 global interrupt"]
DMA2_Channel1 = 56,
#[doc = "57 - DMA2 Channel2 global interrupt"]
DMA2_Channel2 = 57,
#[doc = "58 - DMA2 Channel3 global interrupt"]
DMA2_Channel3 = 58,
#[doc = "59 - DMA2 Channel4 and DMA2 Channel5 global interrupt"]
DMA2_Channel4_5 = 59,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
#[inline(always)]
fn number(self) -> u16 {
self as u16
}
}
#[doc = "Flexible static memory controller"]
pub type Fsmc = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
impl core::fmt::Debug for Fsmc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Fsmc").finish()
}
}
#[doc = "Flexible static memory controller"]
pub mod fsmc;
#[doc = "Power control"]
pub type Pwr = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
impl core::fmt::Debug for Pwr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pwr").finish()
}
}
#[doc = "Power control"]
pub mod pwr;
#[doc = "Reset and clock control"]
pub type Rcc = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
impl core::fmt::Debug for Rcc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Rcc").finish()
}
}
#[doc = "Reset and clock control"]
pub mod rcc;
#[doc = "General purpose I/O"]
pub type Gpioa = crate::Periph<gpioa::RegisterBlock, 0x4001_0800>;
impl core::fmt::Debug for Gpioa {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpioa").finish()
}
}
#[doc = "General purpose I/O"]
pub mod gpioa;
#[doc = "General purpose I/O"]
pub type Gpiob = crate::Periph<gpioa::RegisterBlock, 0x4001_0c00>;
impl core::fmt::Debug for Gpiob {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpiob").finish()
}
}
#[doc = "General purpose I/O"]
pub use self::gpioa as gpiob;
#[doc = "General purpose I/O"]
pub type Gpioc = crate::Periph<gpioa::RegisterBlock, 0x4001_1000>;
impl core::fmt::Debug for Gpioc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpioc").finish()
}
}
#[doc = "General purpose I/O"]
pub use self::gpioa as gpioc;
#[doc = "General purpose I/O"]
pub type Gpiod = crate::Periph<gpioa::RegisterBlock, 0x4001_1400>;
impl core::fmt::Debug for Gpiod {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpiod").finish()
}
}
#[doc = "General purpose I/O"]
pub use self::gpioa as gpiod;
#[doc = "General purpose I/O"]
pub type Gpioe = crate::Periph<gpioa::RegisterBlock, 0x4001_1800>;
impl core::fmt::Debug for Gpioe {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpioe").finish()
}
}
#[doc = "General purpose I/O"]
pub use self::gpioa as gpioe;
#[doc = "General purpose I/O"]
pub type Gpiof = crate::Periph<gpioa::RegisterBlock, 0x4001_1c00>;
impl core::fmt::Debug for Gpiof {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpiof").finish()
}
}
#[doc = "General purpose I/O"]
pub use self::gpioa as gpiof;
#[doc = "General purpose I/O"]
pub type Gpiog = crate::Periph<gpioa::RegisterBlock, 0x4001_2000>;
impl core::fmt::Debug for Gpiog {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpiog").finish()
}
}
#[doc = "General purpose I/O"]
pub use self::gpioa as gpiog;
#[doc = "Alternate function I/O"]
pub type Afio = crate::Periph<afio::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for Afio {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Afio").finish()
}
}
#[doc = "Alternate function I/O"]
pub mod afio;
#[doc = "EXTI"]
pub type Exti = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
impl core::fmt::Debug for Exti {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Exti").finish()
}
}
#[doc = "EXTI"]
pub mod exti;
#[doc = "DMA controller"]
pub type Dma1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for Dma1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dma1").finish()
}
}
#[doc = "DMA controller"]
pub mod dma1;
#[doc = "DMA controller"]
pub type Dma2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
impl core::fmt::Debug for Dma2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dma2").finish()
}
}
#[doc = "DMA controller"]
pub use self::dma1 as dma2;
#[doc = "Secure digital input/output interface"]
pub type Sdio = crate::Periph<sdio::RegisterBlock, 0x4001_8000>;
impl core::fmt::Debug for Sdio {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sdio").finish()
}
}
#[doc = "Secure digital input/output interface"]
pub mod sdio;
#[doc = "Real time clock"]
pub type Rtc = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
impl core::fmt::Debug for Rtc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Rtc").finish()
}
}
#[doc = "Real time clock"]
pub mod rtc;
#[doc = "Backup registers"]
pub type Bkp = crate::Periph<bkp::RegisterBlock, 0x4000_6c00>;
impl core::fmt::Debug for Bkp {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Bkp").finish()
}
}
#[doc = "Backup registers"]
pub mod bkp;
#[doc = "Independent watchdog"]
pub type Iwdg = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for Iwdg {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Iwdg").finish()
}
}
#[doc = "Independent watchdog"]
pub mod iwdg;
#[doc = "Window watchdog"]
pub type Wwdg = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
impl core::fmt::Debug for Wwdg {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Wwdg").finish()
}
}
#[doc = "Window watchdog"]
pub mod wwdg;
#[doc = "Advanced timer"]
pub type Tim1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
impl core::fmt::Debug for Tim1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim1").finish()
}
}
#[doc = "Advanced timer"]
pub mod tim1;
#[doc = "Advanced timer"]
pub type Tim8 = crate::Periph<tim1::RegisterBlock, 0x4001_3400>;
impl core::fmt::Debug for Tim8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim8").finish()
}
}
#[doc = "Advanced timer"]
pub use self::tim1 as tim8;
#[doc = "General purpose timer"]
pub type Tim2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for Tim2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim2").finish()
}
}
#[doc = "General purpose timer"]
pub mod tim2;
#[doc = "General purpose timer"]
pub type Tim3 = crate::Periph<tim2::RegisterBlock, 0x4000_0400>;
impl core::fmt::Debug for Tim3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim3").finish()
}
}
#[doc = "General purpose timer"]
pub use self::tim2 as tim3;
#[doc = "General purpose timer"]
pub type Tim4 = crate::Periph<tim2::RegisterBlock, 0x4000_0800>;
impl core::fmt::Debug for Tim4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim4").finish()
}
}
#[doc = "General purpose timer"]
pub use self::tim2 as tim4;
#[doc = "General purpose timer"]
pub type Tim5 = crate::Periph<tim2::RegisterBlock, 0x4000_0c00>;
impl core::fmt::Debug for Tim5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim5").finish()
}
}
#[doc = "General purpose timer"]
pub use self::tim2 as tim5;
#[doc = "General purpose timer"]
pub type Tim9 = crate::Periph<tim9::RegisterBlock, 0x4001_4c00>;
impl core::fmt::Debug for Tim9 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim9").finish()
}
}
#[doc = "General purpose timer"]
pub mod tim9;
#[doc = "General purpose timer"]
pub type Tim12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
impl core::fmt::Debug for Tim12 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim12").finish()
}
}
#[doc = "General purpose timer"]
pub use self::tim9 as tim12;
#[doc = "General purpose timer"]
pub type Tim10 = crate::Periph<tim10::RegisterBlock, 0x4001_5000>;
impl core::fmt::Debug for Tim10 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim10").finish()
}
}
#[doc = "General purpose timer"]
pub mod tim10;
#[doc = "General purpose timer"]
pub type Tim11 = crate::Periph<tim10::RegisterBlock, 0x4001_5400>;
impl core::fmt::Debug for Tim11 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim11").finish()
}
}
#[doc = "General purpose timer"]
pub use self::tim10 as tim11;
#[doc = "General purpose timer"]
pub type Tim13 = crate::Periph<tim10::RegisterBlock, 0x4000_1c00>;
impl core::fmt::Debug for Tim13 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim13").finish()
}
}
#[doc = "General purpose timer"]
pub use self::tim10 as tim13;
#[doc = "General purpose timer"]
pub type Tim14 = crate::Periph<tim10::RegisterBlock, 0x4000_2000>;
impl core::fmt::Debug for Tim14 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim14").finish()
}
}
#[doc = "General purpose timer"]
pub use self::tim10 as tim14;
#[doc = "Basic timer"]
pub type Tim6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for Tim6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim6").finish()
}
}
#[doc = "Basic timer"]
pub mod tim6;
#[doc = "Basic timer"]
pub type Tim7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
impl core::fmt::Debug for Tim7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Tim7").finish()
}
}
#[doc = "Basic timer"]
pub use self::tim6 as tim7;
#[doc = "Inter integrated circuit"]
pub type I2c1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
impl core::fmt::Debug for I2c1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2c1").finish()
}
}
#[doc = "Inter integrated circuit"]
pub mod i2c1;
#[doc = "Inter integrated circuit"]
pub type I2c2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
impl core::fmt::Debug for I2c2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2c2").finish()
}
}
#[doc = "Inter integrated circuit"]
pub use self::i2c1 as i2c2;
#[doc = "Serial peripheral interface"]
pub type Spi1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for Spi1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Spi1").finish()
}
}
#[doc = "Serial peripheral interface"]
pub mod spi1;
#[doc = "Serial peripheral interface"]
pub type Spi2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
impl core::fmt::Debug for Spi2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Spi2").finish()
}
}
#[doc = "Serial peripheral interface"]
pub use self::spi1 as spi2;
#[doc = "Serial peripheral interface"]
pub type Spi3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
impl core::fmt::Debug for Spi3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Spi3").finish()
}
}
#[doc = "Serial peripheral interface"]
pub use self::spi1 as spi3;
#[doc = "Universal synchronous asynchronous receiver transmitter"]
pub type Usart1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
impl core::fmt::Debug for Usart1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usart1").finish()
}
}
#[doc = "Universal synchronous asynchronous receiver transmitter"]
pub mod usart1;
#[doc = "Universal synchronous asynchronous receiver transmitter"]
pub type Usart2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
impl core::fmt::Debug for Usart2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usart2").finish()
}
}
#[doc = "Universal synchronous asynchronous receiver transmitter"]
pub use self::usart1 as usart2;
#[doc = "Universal synchronous asynchronous receiver transmitter"]
pub type Usart3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
impl core::fmt::Debug for Usart3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usart3").finish()
}
}
#[doc = "Universal synchronous asynchronous receiver transmitter"]
pub use self::usart1 as usart3;
#[doc = "Analog to digital converter"]
pub type Adc1 = crate::Periph<adc1::RegisterBlock, 0x4001_2400>;
impl core::fmt::Debug for Adc1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Adc1").finish()
}
}
#[doc = "Analog to digital converter"]
pub mod adc1;
#[doc = "Analog to digital converter"]
pub type Adc2 = crate::Periph<adc2::RegisterBlock, 0x4001_2800>;
impl core::fmt::Debug for Adc2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Adc2").finish()
}
}
#[doc = "Analog to digital converter"]
pub mod adc2;
#[doc = "Analog to digital converter"]
pub type Adc3 = crate::Periph<adc2::RegisterBlock, 0x4001_3c00>;
impl core::fmt::Debug for Adc3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Adc3").finish()
}
}
#[doc = "Analog to digital converter"]
pub use self::adc2 as adc3;
#[doc = "Controller area network"]
pub type Can1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
impl core::fmt::Debug for Can1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Can1").finish()
}
}
#[doc = "Controller area network"]
pub mod can1;
#[doc = "Controller area network"]
pub type Can2 = crate::Periph<can1::RegisterBlock, 0x4000_6800>;
impl core::fmt::Debug for Can2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Can2").finish()
}
}
#[doc = "Controller area network"]
pub use self::can1 as can2;
#[doc = "Digital to analog converter"]
pub type Dac = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
impl core::fmt::Debug for Dac {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dac").finish()
}
}
#[doc = "Digital to analog converter"]
pub mod dac;
#[doc = "Debug support"]
pub type Dbg = crate::Periph<dbg::RegisterBlock, 0xe004_2000>;
impl core::fmt::Debug for Dbg {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dbg").finish()
}
}
#[doc = "Debug support"]
pub mod dbg;
#[doc = "Universal asynchronous receiver transmitter"]
pub type Uart4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
impl core::fmt::Debug for Uart4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Uart4").finish()
}
}
#[doc = "Universal asynchronous receiver transmitter"]
pub mod uart4;
#[doc = "Universal asynchronous receiver transmitter"]
pub type Uart5 = crate::Periph<uart5::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for Uart5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Uart5").finish()
}
}
#[doc = "Universal asynchronous receiver transmitter"]
pub mod uart5;
#[doc = "CRC calculation unit"]
pub type Crc = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
impl core::fmt::Debug for Crc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Crc").finish()
}
}
#[doc = "CRC calculation unit"]
pub mod crc;
#[doc = "FLASH"]
pub type Flash = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
impl core::fmt::Debug for Flash {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Flash").finish()
}
}
#[doc = "FLASH"]
pub mod flash;
#[doc = "Universal serial bus full-speed device interface"]
pub type Usb = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
impl core::fmt::Debug for Usb {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usb").finish()
}
}
#[doc = "Universal serial bus full-speed device interface"]
pub mod usb;
#[doc = "USB on the go full speed"]
pub type OtgFsDevice = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
impl core::fmt::Debug for OtgFsDevice {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OtgFsDevice").finish()
}
}
#[doc = "USB on the go full speed"]
pub mod otg_fs_device;
#[doc = "USB on the go full speed"]
pub type OtgFsGlobal = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
impl core::fmt::Debug for OtgFsGlobal {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OtgFsGlobal").finish()
}
}
#[doc = "USB on the go full speed"]
pub mod otg_fs_global;
#[doc = "USB on the go full speed"]
pub type OtgFsHost = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
impl core::fmt::Debug for OtgFsHost {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OtgFsHost").finish()
}
}
#[doc = "USB on the go full speed"]
pub mod otg_fs_host;
#[doc = "USB on the go full speed"]
pub type OtgFsPwrclk = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
impl core::fmt::Debug for OtgFsPwrclk {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OtgFsPwrclk").finish()
}
}
#[doc = "USB on the go full speed"]
pub mod otg_fs_pwrclk;
#[doc = "Ethernet: MAC management counters"]
pub type EthernetMmc = crate::Periph<ethernet_mmc::RegisterBlock, 0x4002_8100>;
impl core::fmt::Debug for EthernetMmc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EthernetMmc").finish()
}
}
#[doc = "Ethernet: MAC management counters"]
pub mod ethernet_mmc;
#[doc = "Ethernet: media access control"]
pub type EthernetMac = crate::Periph<ethernet_mac::RegisterBlock, 0x4002_8000>;
impl core::fmt::Debug for EthernetMac {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EthernetMac").finish()
}
}
#[doc = "Ethernet: media access control"]
pub mod ethernet_mac;
#[doc = "Ethernet: Precision time protocol"]
pub type EthernetPtp = crate::Periph<ethernet_ptp::RegisterBlock, 0x4002_8700>;
impl core::fmt::Debug for EthernetPtp {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EthernetPtp").finish()
}
}
#[doc = "Ethernet: Precision time protocol"]
pub mod ethernet_ptp;
#[doc = "Ethernet: DMA controller operation"]
pub type EthernetDma = crate::Periph<ethernet_dma::RegisterBlock, 0x4002_9000>;
impl core::fmt::Debug for EthernetDma {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EthernetDma").finish()
}
}
#[doc = "Ethernet: DMA controller operation"]
pub mod ethernet_dma;
#[doc = "System control block ACTLR"]
pub type ScbActrl = crate::Periph<scb_actrl::RegisterBlock, 0xe000_e008>;
impl core::fmt::Debug for ScbActrl {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ScbActrl").finish()
}
}
#[doc = "System control block ACTLR"]
pub mod scb_actrl;
#[doc = "Nested vectored interrupt controller"]
pub type NvicStir = crate::Periph<nvic_stir::RegisterBlock, 0xe000_ef00>;
impl core::fmt::Debug for NvicStir {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("NvicStir").finish()
}
}
#[doc = "Nested vectored interrupt controller"]
pub mod nvic_stir;
#[doc = "SysTick timer"]
pub type Stk = crate::Periph<stk::RegisterBlock, 0xe000_e010>;
impl core::fmt::Debug for Stk {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Stk").finish()
}
}
#[doc = "SysTick timer"]
pub mod stk;
#[unsafe(no_mangle)]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
#[doc = "FSMC"]
pub fsmc: Fsmc,
#[doc = "PWR"]
pub pwr: Pwr,
#[doc = "RCC"]
pub rcc: Rcc,
#[doc = "GPIOA"]
pub gpioa: Gpioa,
#[doc = "GPIOB"]
pub gpiob: Gpiob,
#[doc = "GPIOC"]
pub gpioc: Gpioc,
#[doc = "GPIOD"]
pub gpiod: Gpiod,
#[doc = "GPIOE"]
pub gpioe: Gpioe,
#[doc = "GPIOF"]
pub gpiof: Gpiof,
#[doc = "GPIOG"]
pub gpiog: Gpiog,
#[doc = "AFIO"]
pub afio: Afio,
#[doc = "EXTI"]
pub exti: Exti,
#[doc = "DMA1"]
pub dma1: Dma1,
#[doc = "DMA2"]
pub dma2: Dma2,
#[doc = "SDIO"]
pub sdio: Sdio,
#[doc = "RTC"]
pub rtc: Rtc,
#[doc = "BKP"]
pub bkp: Bkp,
#[doc = "IWDG"]
pub iwdg: Iwdg,
#[doc = "WWDG"]
pub wwdg: Wwdg,
#[doc = "TIM1"]
pub tim1: Tim1,
#[doc = "TIM8"]
pub tim8: Tim8,
#[doc = "TIM2"]
pub tim2: Tim2,
#[doc = "TIM3"]
pub tim3: Tim3,
#[doc = "TIM4"]
pub tim4: Tim4,
#[doc = "TIM5"]
pub tim5: Tim5,
#[doc = "TIM9"]
pub tim9: Tim9,
#[doc = "TIM12"]
pub tim12: Tim12,
#[doc = "TIM10"]
pub tim10: Tim10,
#[doc = "TIM11"]
pub tim11: Tim11,
#[doc = "TIM13"]
pub tim13: Tim13,
#[doc = "TIM14"]
pub tim14: Tim14,
#[doc = "TIM6"]
pub tim6: Tim6,
#[doc = "TIM7"]
pub tim7: Tim7,
#[doc = "I2C1"]
pub i2c1: I2c1,
#[doc = "I2C2"]
pub i2c2: I2c2,
#[doc = "SPI1"]
pub spi1: Spi1,
#[doc = "SPI2"]
pub spi2: Spi2,
#[doc = "SPI3"]
pub spi3: Spi3,
#[doc = "USART1"]
pub usart1: Usart1,
#[doc = "USART2"]
pub usart2: Usart2,
#[doc = "USART3"]
pub usart3: Usart3,
#[doc = "ADC1"]
pub adc1: Adc1,
#[doc = "ADC2"]
pub adc2: Adc2,
#[doc = "ADC3"]
pub adc3: Adc3,
#[doc = "CAN1"]
pub can1: Can1,
#[doc = "CAN2"]
pub can2: Can2,
#[doc = "DAC"]
pub dac: Dac,
#[doc = "DBG"]
pub dbg: Dbg,
#[doc = "UART4"]
pub uart4: Uart4,
#[doc = "UART5"]
pub uart5: Uart5,
#[doc = "CRC"]
pub crc: Crc,
#[doc = "FLASH"]
pub flash: Flash,
#[doc = "USB"]
pub usb: Usb,
#[doc = "OTG_FS_DEVICE"]
pub otg_fs_device: OtgFsDevice,
#[doc = "OTG_FS_GLOBAL"]
pub otg_fs_global: OtgFsGlobal,
#[doc = "OTG_FS_HOST"]
pub otg_fs_host: OtgFsHost,
#[doc = "OTG_FS_PWRCLK"]
pub otg_fs_pwrclk: OtgFsPwrclk,
#[doc = "ETHERNET_MMC"]
pub ethernet_mmc: EthernetMmc,
#[doc = "ETHERNET_MAC"]
pub ethernet_mac: EthernetMac,
#[doc = "ETHERNET_PTP"]
pub ethernet_ptp: EthernetPtp,
#[doc = "ETHERNET_DMA"]
pub ethernet_dma: EthernetDma,
#[doc = "SCB_ACTRL"]
pub scb_actrl: ScbActrl,
#[doc = "NVIC_STIR"]
pub nvic_stir: NvicStir,
#[doc = "STK"]
pub stk: Stk,
}
impl Peripherals {
#[doc = r" Returns all the peripherals *once*."]
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[doc = r" Unchecked version of `Peripherals::take`."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Each of the returned peripherals must be used at most once."]
#[inline]
pub unsafe fn steal() -> Self {
unsafe {
DEVICE_PERIPHERALS = true;
Peripherals {
fsmc: Fsmc::steal(),
pwr: Pwr::steal(),
rcc: Rcc::steal(),
gpioa: Gpioa::steal(),
gpiob: Gpiob::steal(),
gpioc: Gpioc::steal(),
gpiod: Gpiod::steal(),
gpioe: Gpioe::steal(),
gpiof: Gpiof::steal(),
gpiog: Gpiog::steal(),
afio: Afio::steal(),
exti: Exti::steal(),
dma1: Dma1::steal(),
dma2: Dma2::steal(),
sdio: Sdio::steal(),
rtc: Rtc::steal(),
bkp: Bkp::steal(),
iwdg: Iwdg::steal(),
wwdg: Wwdg::steal(),
tim1: Tim1::steal(),
tim8: Tim8::steal(),
tim2: Tim2::steal(),
tim3: Tim3::steal(),
tim4: Tim4::steal(),
tim5: Tim5::steal(),
tim9: Tim9::steal(),
tim12: Tim12::steal(),
tim10: Tim10::steal(),
tim11: Tim11::steal(),
tim13: Tim13::steal(),
tim14: Tim14::steal(),
tim6: Tim6::steal(),
tim7: Tim7::steal(),
i2c1: I2c1::steal(),
i2c2: I2c2::steal(),
spi1: Spi1::steal(),
spi2: Spi2::steal(),
spi3: Spi3::steal(),
usart1: Usart1::steal(),
usart2: Usart2::steal(),
usart3: Usart3::steal(),
adc1: Adc1::steal(),
adc2: Adc2::steal(),
adc3: Adc3::steal(),
can1: Can1::steal(),
can2: Can2::steal(),
dac: Dac::steal(),
dbg: Dbg::steal(),
uart4: Uart4::steal(),
uart5: Uart5::steal(),
crc: Crc::steal(),
flash: Flash::steal(),
usb: Usb::steal(),
otg_fs_device: OtgFsDevice::steal(),
otg_fs_global: OtgFsGlobal::steal(),
otg_fs_host: OtgFsHost::steal(),
otg_fs_pwrclk: OtgFsPwrclk::steal(),
ethernet_mmc: EthernetMmc::steal(),
ethernet_mac: EthernetMac::steal(),
ethernet_ptp: EthernetPtp::steal(),
ethernet_dma: EthernetDma::steal(),
scb_actrl: ScbActrl::steal(),
nvic_stir: NvicStir::steal(),
stk: Stk::steal(),
}
}
}
}