stm32f103-pac 0.1.3

Peripheral Access Crate (PAC) for STM32F103
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77

#[doc = "Register `EXTICR4` reader"]
pub type R = crate::R<Exticr4Spec>;
#[doc = "Register `EXTICR4` writer"]
pub type W = crate::W<Exticr4Spec>;
#[doc = "Field `EXTI12` reader - EXTI12 configuration"]
pub type Exti12R = crate::FieldReader;
#[doc = "Field `EXTI12` writer - EXTI12 configuration"]
pub type Exti12W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `EXTI13` reader - EXTI13 configuration"]
pub type Exti13R = crate::FieldReader;
#[doc = "Field `EXTI13` writer - EXTI13 configuration"]
pub type Exti13W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `EXTI14` reader - EXTI14 configuration"]
pub type Exti14R = crate::FieldReader;
#[doc = "Field `EXTI14` writer - EXTI14 configuration"]
pub type Exti14W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `EXTI15` reader - EXTI15 configuration"]
pub type Exti15R = crate::FieldReader;
#[doc = "Field `EXTI15` writer - EXTI15 configuration"]
pub type Exti15W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
    #[doc = "Bits 0:3 - EXTI12 configuration"]
    #[inline(always)]
    pub fn exti12(&self) -> Exti12R {
        Exti12R::new((self.bits & 0x0f) as u8)
    }
    #[doc = "Bits 4:7 - EXTI13 configuration"]
    #[inline(always)]
    pub fn exti13(&self) -> Exti13R {
        Exti13R::new(((self.bits >> 4) & 0x0f) as u8)
    }
    #[doc = "Bits 8:11 - EXTI14 configuration"]
    #[inline(always)]
    pub fn exti14(&self) -> Exti14R {
        Exti14R::new(((self.bits >> 8) & 0x0f) as u8)
    }
    #[doc = "Bits 12:15 - EXTI15 configuration"]
    #[inline(always)]
    pub fn exti15(&self) -> Exti15R {
        Exti15R::new(((self.bits >> 12) & 0x0f) as u8)
    }
}
impl W {
    #[doc = "Bits 0:3 - EXTI12 configuration"]
    #[inline(always)]
    pub fn exti12(&mut self) -> Exti12W<'_, Exticr4Spec> {
        Exti12W::new(self, 0)
    }
    #[doc = "Bits 4:7 - EXTI13 configuration"]
    #[inline(always)]
    pub fn exti13(&mut self) -> Exti13W<'_, Exticr4Spec> {
        Exti13W::new(self, 4)
    }
    #[doc = "Bits 8:11 - EXTI14 configuration"]
    #[inline(always)]
    pub fn exti14(&mut self) -> Exti14W<'_, Exticr4Spec> {
        Exti14W::new(self, 8)
    }
    #[doc = "Bits 12:15 - EXTI15 configuration"]
    #[inline(always)]
    pub fn exti15(&mut self) -> Exti15W<'_, Exticr4Spec> {
        Exti15W::new(self, 12)
    }
}
#[doc = "External interrupt configuration register 4 (AFIO_EXTICR4)\n\nYou can [`read`](crate::Reg::read) this register and get [`exticr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Exticr4Spec;
impl crate::RegisterSpec for Exticr4Spec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`exticr4::R`](R) reader structure"]
impl crate::Readable for Exticr4Spec {}
#[doc = "`write(|w| ..)` method takes [`exticr4::W`](W) writer structure"]
impl crate::Writable for Exticr4Spec {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EXTICR4 to value 0"]
impl crate::Resettable for Exticr4Spec {}