stm32f1/stm32f102/usart1/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5///Field `ADD` reader - Address of the USART node
6pub type ADD_R = crate::FieldReader;
7///Field `ADD` writer - Address of the USART node
8pub type ADD_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
9/**lin break detection length
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum LBDL {
15    ///0: 10-bit break detection
16    Lbdl10 = 0,
17    ///1: 11-bit break detection
18    Lbdl11 = 1,
19}
20impl From<LBDL> for bool {
21    #[inline(always)]
22    fn from(variant: LBDL) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `LBDL` reader - lin break detection length
27pub type LBDL_R = crate::BitReader<LBDL>;
28impl LBDL_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> LBDL {
32        match self.bits {
33            false => LBDL::Lbdl10,
34            true => LBDL::Lbdl11,
35        }
36    }
37    ///10-bit break detection
38    #[inline(always)]
39    pub fn is_lbdl10(&self) -> bool {
40        *self == LBDL::Lbdl10
41    }
42    ///11-bit break detection
43    #[inline(always)]
44    pub fn is_lbdl11(&self) -> bool {
45        *self == LBDL::Lbdl11
46    }
47}
48///Field `LBDL` writer - lin break detection length
49pub type LBDL_W<'a, REG> = crate::BitWriter<'a, REG, LBDL>;
50impl<'a, REG> LBDL_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///10-bit break detection
55    #[inline(always)]
56    pub fn lbdl10(self) -> &'a mut crate::W<REG> {
57        self.variant(LBDL::Lbdl10)
58    }
59    ///11-bit break detection
60    #[inline(always)]
61    pub fn lbdl11(self) -> &'a mut crate::W<REG> {
62        self.variant(LBDL::Lbdl11)
63    }
64}
65/**LIN break detection interrupt enable
66
67Value on reset: 0*/
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum LBDIE {
71    ///0: LIN break detection interrupt disabled
72    Disabled = 0,
73    ///1: LIN break detection interrupt enabled
74    Enabled = 1,
75}
76impl From<LBDIE> for bool {
77    #[inline(always)]
78    fn from(variant: LBDIE) -> Self {
79        variant as u8 != 0
80    }
81}
82///Field `LBDIE` reader - LIN break detection interrupt enable
83pub type LBDIE_R = crate::BitReader<LBDIE>;
84impl LBDIE_R {
85    ///Get enumerated values variant
86    #[inline(always)]
87    pub const fn variant(&self) -> LBDIE {
88        match self.bits {
89            false => LBDIE::Disabled,
90            true => LBDIE::Enabled,
91        }
92    }
93    ///LIN break detection interrupt disabled
94    #[inline(always)]
95    pub fn is_disabled(&self) -> bool {
96        *self == LBDIE::Disabled
97    }
98    ///LIN break detection interrupt enabled
99    #[inline(always)]
100    pub fn is_enabled(&self) -> bool {
101        *self == LBDIE::Enabled
102    }
103}
104///Field `LBDIE` writer - LIN break detection interrupt enable
105pub type LBDIE_W<'a, REG> = crate::BitWriter<'a, REG, LBDIE>;
106impl<'a, REG> LBDIE_W<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    ///LIN break detection interrupt disabled
111    #[inline(always)]
112    pub fn disabled(self) -> &'a mut crate::W<REG> {
113        self.variant(LBDIE::Disabled)
114    }
115    ///LIN break detection interrupt enabled
116    #[inline(always)]
117    pub fn enabled(self) -> &'a mut crate::W<REG> {
118        self.variant(LBDIE::Enabled)
119    }
120}
121/**Last bit clock pulse
122
123Value on reset: 0*/
124#[cfg_attr(feature = "defmt", derive(defmt::Format))]
125#[derive(Clone, Copy, Debug, PartialEq, Eq)]
126pub enum LBCL {
127    ///0: The clock pulse of the last data bit is not output to the CK pin
128    Disabled = 0,
129    ///1: The clock pulse of the last data bit is output to the CK pin
130    Enabled = 1,
131}
132impl From<LBCL> for bool {
133    #[inline(always)]
134    fn from(variant: LBCL) -> Self {
135        variant as u8 != 0
136    }
137}
138///Field `LBCL` reader - Last bit clock pulse
139pub type LBCL_R = crate::BitReader<LBCL>;
140impl LBCL_R {
141    ///Get enumerated values variant
142    #[inline(always)]
143    pub const fn variant(&self) -> LBCL {
144        match self.bits {
145            false => LBCL::Disabled,
146            true => LBCL::Enabled,
147        }
148    }
149    ///The clock pulse of the last data bit is not output to the CK pin
150    #[inline(always)]
151    pub fn is_disabled(&self) -> bool {
152        *self == LBCL::Disabled
153    }
154    ///The clock pulse of the last data bit is output to the CK pin
155    #[inline(always)]
156    pub fn is_enabled(&self) -> bool {
157        *self == LBCL::Enabled
158    }
159}
160///Field `LBCL` writer - Last bit clock pulse
161pub type LBCL_W<'a, REG> = crate::BitWriter<'a, REG, LBCL>;
162impl<'a, REG> LBCL_W<'a, REG>
163where
164    REG: crate::Writable + crate::RegisterSpec,
165{
166    ///The clock pulse of the last data bit is not output to the CK pin
167    #[inline(always)]
168    pub fn disabled(self) -> &'a mut crate::W<REG> {
169        self.variant(LBCL::Disabled)
170    }
171    ///The clock pulse of the last data bit is output to the CK pin
172    #[inline(always)]
173    pub fn enabled(self) -> &'a mut crate::W<REG> {
174        self.variant(LBCL::Enabled)
175    }
176}
177/**Clock phase
178
179Value on reset: 0*/
180#[cfg_attr(feature = "defmt", derive(defmt::Format))]
181#[derive(Clone, Copy, Debug, PartialEq, Eq)]
182pub enum CPHA {
183    ///0: The first clock transition is the first data capture edge
184    First = 0,
185    ///1: The second clock transition is the first data capture edge
186    Second = 1,
187}
188impl From<CPHA> for bool {
189    #[inline(always)]
190    fn from(variant: CPHA) -> Self {
191        variant as u8 != 0
192    }
193}
194///Field `CPHA` reader - Clock phase
195pub type CPHA_R = crate::BitReader<CPHA>;
196impl CPHA_R {
197    ///Get enumerated values variant
198    #[inline(always)]
199    pub const fn variant(&self) -> CPHA {
200        match self.bits {
201            false => CPHA::First,
202            true => CPHA::Second,
203        }
204    }
205    ///The first clock transition is the first data capture edge
206    #[inline(always)]
207    pub fn is_first(&self) -> bool {
208        *self == CPHA::First
209    }
210    ///The second clock transition is the first data capture edge
211    #[inline(always)]
212    pub fn is_second(&self) -> bool {
213        *self == CPHA::Second
214    }
215}
216///Field `CPHA` writer - Clock phase
217pub type CPHA_W<'a, REG> = crate::BitWriter<'a, REG, CPHA>;
218impl<'a, REG> CPHA_W<'a, REG>
219where
220    REG: crate::Writable + crate::RegisterSpec,
221{
222    ///The first clock transition is the first data capture edge
223    #[inline(always)]
224    pub fn first(self) -> &'a mut crate::W<REG> {
225        self.variant(CPHA::First)
226    }
227    ///The second clock transition is the first data capture edge
228    #[inline(always)]
229    pub fn second(self) -> &'a mut crate::W<REG> {
230        self.variant(CPHA::Second)
231    }
232}
233/**Clock polarity
234
235Value on reset: 0*/
236#[cfg_attr(feature = "defmt", derive(defmt::Format))]
237#[derive(Clone, Copy, Debug, PartialEq, Eq)]
238pub enum CPOL {
239    ///0: Steady low value on CK pin outside transmission window
240    Low = 0,
241    ///1: Steady high value on CK pin outside transmission window
242    High = 1,
243}
244impl From<CPOL> for bool {
245    #[inline(always)]
246    fn from(variant: CPOL) -> Self {
247        variant as u8 != 0
248    }
249}
250///Field `CPOL` reader - Clock polarity
251pub type CPOL_R = crate::BitReader<CPOL>;
252impl CPOL_R {
253    ///Get enumerated values variant
254    #[inline(always)]
255    pub const fn variant(&self) -> CPOL {
256        match self.bits {
257            false => CPOL::Low,
258            true => CPOL::High,
259        }
260    }
261    ///Steady low value on CK pin outside transmission window
262    #[inline(always)]
263    pub fn is_low(&self) -> bool {
264        *self == CPOL::Low
265    }
266    ///Steady high value on CK pin outside transmission window
267    #[inline(always)]
268    pub fn is_high(&self) -> bool {
269        *self == CPOL::High
270    }
271}
272///Field `CPOL` writer - Clock polarity
273pub type CPOL_W<'a, REG> = crate::BitWriter<'a, REG, CPOL>;
274impl<'a, REG> CPOL_W<'a, REG>
275where
276    REG: crate::Writable + crate::RegisterSpec,
277{
278    ///Steady low value on CK pin outside transmission window
279    #[inline(always)]
280    pub fn low(self) -> &'a mut crate::W<REG> {
281        self.variant(CPOL::Low)
282    }
283    ///Steady high value on CK pin outside transmission window
284    #[inline(always)]
285    pub fn high(self) -> &'a mut crate::W<REG> {
286        self.variant(CPOL::High)
287    }
288}
289/**Clock enable
290
291Value on reset: 0*/
292#[cfg_attr(feature = "defmt", derive(defmt::Format))]
293#[derive(Clone, Copy, Debug, PartialEq, Eq)]
294pub enum CLKEN {
295    ///0: CK pin disabled
296    Disabled = 0,
297    ///1: CK pin enabled
298    Enabled = 1,
299}
300impl From<CLKEN> for bool {
301    #[inline(always)]
302    fn from(variant: CLKEN) -> Self {
303        variant as u8 != 0
304    }
305}
306///Field `CLKEN` reader - Clock enable
307pub type CLKEN_R = crate::BitReader<CLKEN>;
308impl CLKEN_R {
309    ///Get enumerated values variant
310    #[inline(always)]
311    pub const fn variant(&self) -> CLKEN {
312        match self.bits {
313            false => CLKEN::Disabled,
314            true => CLKEN::Enabled,
315        }
316    }
317    ///CK pin disabled
318    #[inline(always)]
319    pub fn is_disabled(&self) -> bool {
320        *self == CLKEN::Disabled
321    }
322    ///CK pin enabled
323    #[inline(always)]
324    pub fn is_enabled(&self) -> bool {
325        *self == CLKEN::Enabled
326    }
327}
328///Field `CLKEN` writer - Clock enable
329pub type CLKEN_W<'a, REG> = crate::BitWriter<'a, REG, CLKEN>;
330impl<'a, REG> CLKEN_W<'a, REG>
331where
332    REG: crate::Writable + crate::RegisterSpec,
333{
334    ///CK pin disabled
335    #[inline(always)]
336    pub fn disabled(self) -> &'a mut crate::W<REG> {
337        self.variant(CLKEN::Disabled)
338    }
339    ///CK pin enabled
340    #[inline(always)]
341    pub fn enabled(self) -> &'a mut crate::W<REG> {
342        self.variant(CLKEN::Enabled)
343    }
344}
345/**STOP bits
346
347Value on reset: 0*/
348#[cfg_attr(feature = "defmt", derive(defmt::Format))]
349#[derive(Clone, Copy, Debug, PartialEq, Eq)]
350#[repr(u8)]
351pub enum STOP {
352    ///0: 1 stop bit
353    Stop1 = 0,
354    ///1: 0.5 stop bits
355    Stop0p5 = 1,
356    ///2: 2 stop bits
357    Stop2 = 2,
358    ///3: 1.5 stop bits
359    Stop1p5 = 3,
360}
361impl From<STOP> for u8 {
362    #[inline(always)]
363    fn from(variant: STOP) -> Self {
364        variant as _
365    }
366}
367impl crate::FieldSpec for STOP {
368    type Ux = u8;
369}
370impl crate::IsEnum for STOP {}
371///Field `STOP` reader - STOP bits
372pub type STOP_R = crate::FieldReader<STOP>;
373impl STOP_R {
374    ///Get enumerated values variant
375    #[inline(always)]
376    pub const fn variant(&self) -> STOP {
377        match self.bits {
378            0 => STOP::Stop1,
379            1 => STOP::Stop0p5,
380            2 => STOP::Stop2,
381            3 => STOP::Stop1p5,
382            _ => unreachable!(),
383        }
384    }
385    ///1 stop bit
386    #[inline(always)]
387    pub fn is_stop1(&self) -> bool {
388        *self == STOP::Stop1
389    }
390    ///0.5 stop bits
391    #[inline(always)]
392    pub fn is_stop0p5(&self) -> bool {
393        *self == STOP::Stop0p5
394    }
395    ///2 stop bits
396    #[inline(always)]
397    pub fn is_stop2(&self) -> bool {
398        *self == STOP::Stop2
399    }
400    ///1.5 stop bits
401    #[inline(always)]
402    pub fn is_stop1p5(&self) -> bool {
403        *self == STOP::Stop1p5
404    }
405}
406///Field `STOP` writer - STOP bits
407pub type STOP_W<'a, REG> = crate::FieldWriter<'a, REG, 2, STOP, crate::Safe>;
408impl<'a, REG> STOP_W<'a, REG>
409where
410    REG: crate::Writable + crate::RegisterSpec,
411    REG::Ux: From<u8>,
412{
413    ///1 stop bit
414    #[inline(always)]
415    pub fn stop1(self) -> &'a mut crate::W<REG> {
416        self.variant(STOP::Stop1)
417    }
418    ///0.5 stop bits
419    #[inline(always)]
420    pub fn stop0p5(self) -> &'a mut crate::W<REG> {
421        self.variant(STOP::Stop0p5)
422    }
423    ///2 stop bits
424    #[inline(always)]
425    pub fn stop2(self) -> &'a mut crate::W<REG> {
426        self.variant(STOP::Stop2)
427    }
428    ///1.5 stop bits
429    #[inline(always)]
430    pub fn stop1p5(self) -> &'a mut crate::W<REG> {
431        self.variant(STOP::Stop1p5)
432    }
433}
434/**LIN mode enable
435
436Value on reset: 0*/
437#[cfg_attr(feature = "defmt", derive(defmt::Format))]
438#[derive(Clone, Copy, Debug, PartialEq, Eq)]
439pub enum LINEN {
440    ///0: LIN mode disabled
441    Disabled = 0,
442    ///1: LIN mode enabled
443    Enabled = 1,
444}
445impl From<LINEN> for bool {
446    #[inline(always)]
447    fn from(variant: LINEN) -> Self {
448        variant as u8 != 0
449    }
450}
451///Field `LINEN` reader - LIN mode enable
452pub type LINEN_R = crate::BitReader<LINEN>;
453impl LINEN_R {
454    ///Get enumerated values variant
455    #[inline(always)]
456    pub const fn variant(&self) -> LINEN {
457        match self.bits {
458            false => LINEN::Disabled,
459            true => LINEN::Enabled,
460        }
461    }
462    ///LIN mode disabled
463    #[inline(always)]
464    pub fn is_disabled(&self) -> bool {
465        *self == LINEN::Disabled
466    }
467    ///LIN mode enabled
468    #[inline(always)]
469    pub fn is_enabled(&self) -> bool {
470        *self == LINEN::Enabled
471    }
472}
473///Field `LINEN` writer - LIN mode enable
474pub type LINEN_W<'a, REG> = crate::BitWriter<'a, REG, LINEN>;
475impl<'a, REG> LINEN_W<'a, REG>
476where
477    REG: crate::Writable + crate::RegisterSpec,
478{
479    ///LIN mode disabled
480    #[inline(always)]
481    pub fn disabled(self) -> &'a mut crate::W<REG> {
482        self.variant(LINEN::Disabled)
483    }
484    ///LIN mode enabled
485    #[inline(always)]
486    pub fn enabled(self) -> &'a mut crate::W<REG> {
487        self.variant(LINEN::Enabled)
488    }
489}
490impl R {
491    ///Bits 0:3 - Address of the USART node
492    #[inline(always)]
493    pub fn add(&self) -> ADD_R {
494        ADD_R::new((self.bits & 0x0f) as u8)
495    }
496    ///Bit 5 - lin break detection length
497    #[inline(always)]
498    pub fn lbdl(&self) -> LBDL_R {
499        LBDL_R::new(((self.bits >> 5) & 1) != 0)
500    }
501    ///Bit 6 - LIN break detection interrupt enable
502    #[inline(always)]
503    pub fn lbdie(&self) -> LBDIE_R {
504        LBDIE_R::new(((self.bits >> 6) & 1) != 0)
505    }
506    ///Bit 8 - Last bit clock pulse
507    #[inline(always)]
508    pub fn lbcl(&self) -> LBCL_R {
509        LBCL_R::new(((self.bits >> 8) & 1) != 0)
510    }
511    ///Bit 9 - Clock phase
512    #[inline(always)]
513    pub fn cpha(&self) -> CPHA_R {
514        CPHA_R::new(((self.bits >> 9) & 1) != 0)
515    }
516    ///Bit 10 - Clock polarity
517    #[inline(always)]
518    pub fn cpol(&self) -> CPOL_R {
519        CPOL_R::new(((self.bits >> 10) & 1) != 0)
520    }
521    ///Bit 11 - Clock enable
522    #[inline(always)]
523    pub fn clken(&self) -> CLKEN_R {
524        CLKEN_R::new(((self.bits >> 11) & 1) != 0)
525    }
526    ///Bits 12:13 - STOP bits
527    #[inline(always)]
528    pub fn stop(&self) -> STOP_R {
529        STOP_R::new(((self.bits >> 12) & 3) as u8)
530    }
531    ///Bit 14 - LIN mode enable
532    #[inline(always)]
533    pub fn linen(&self) -> LINEN_R {
534        LINEN_R::new(((self.bits >> 14) & 1) != 0)
535    }
536}
537impl core::fmt::Debug for R {
538    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
539        f.debug_struct("CR2")
540            .field("linen", &self.linen())
541            .field("stop", &self.stop())
542            .field("clken", &self.clken())
543            .field("cpol", &self.cpol())
544            .field("cpha", &self.cpha())
545            .field("lbcl", &self.lbcl())
546            .field("lbdie", &self.lbdie())
547            .field("lbdl", &self.lbdl())
548            .field("add", &self.add())
549            .finish()
550    }
551}
552impl W {
553    ///Bits 0:3 - Address of the USART node
554    #[inline(always)]
555    pub fn add(&mut self) -> ADD_W<CR2rs> {
556        ADD_W::new(self, 0)
557    }
558    ///Bit 5 - lin break detection length
559    #[inline(always)]
560    pub fn lbdl(&mut self) -> LBDL_W<CR2rs> {
561        LBDL_W::new(self, 5)
562    }
563    ///Bit 6 - LIN break detection interrupt enable
564    #[inline(always)]
565    pub fn lbdie(&mut self) -> LBDIE_W<CR2rs> {
566        LBDIE_W::new(self, 6)
567    }
568    ///Bit 8 - Last bit clock pulse
569    #[inline(always)]
570    pub fn lbcl(&mut self) -> LBCL_W<CR2rs> {
571        LBCL_W::new(self, 8)
572    }
573    ///Bit 9 - Clock phase
574    #[inline(always)]
575    pub fn cpha(&mut self) -> CPHA_W<CR2rs> {
576        CPHA_W::new(self, 9)
577    }
578    ///Bit 10 - Clock polarity
579    #[inline(always)]
580    pub fn cpol(&mut self) -> CPOL_W<CR2rs> {
581        CPOL_W::new(self, 10)
582    }
583    ///Bit 11 - Clock enable
584    #[inline(always)]
585    pub fn clken(&mut self) -> CLKEN_W<CR2rs> {
586        CLKEN_W::new(self, 11)
587    }
588    ///Bits 12:13 - STOP bits
589    #[inline(always)]
590    pub fn stop(&mut self) -> STOP_W<CR2rs> {
591        STOP_W::new(self, 12)
592    }
593    ///Bit 14 - LIN mode enable
594    #[inline(always)]
595    pub fn linen(&mut self) -> LINEN_W<CR2rs> {
596        LINEN_W::new(self, 14)
597    }
598}
599/**Control register 2
600
601You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
602
603See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#USART1:CR2)*/
604pub struct CR2rs;
605impl crate::RegisterSpec for CR2rs {
606    type Ux = u16;
607}
608///`read()` method returns [`cr2::R`](R) reader structure
609impl crate::Readable for CR2rs {}
610///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
611impl crate::Writable for CR2rs {
612    type Safety = crate::Unsafe;
613}
614///`reset()` method sets CR2 to value 0
615impl crate::Resettable for CR2rs {}
stm32f1/stm32f102/usart1/cr2.rs

stm32f1/stm32f102/usart1/
cr2.rs
