stm32f1/stm32f100/tim1/
ccmr2_output.rs

1///Register `CCMR2_Output` reader
2pub type R = crate::R<CCMR2_OUTPUTrs>;
3///Register `CCMR2_Output` writer
4pub type W = crate::W<CCMR2_OUTPUTrs>;
5///Capture/Compare %s selection
6pub use super::ccmr1_output::CC1S;
7///Field `CCS(3-4)` reader - Capture/Compare %s selection
8pub use super::ccmr1_output::CCS_R;
9///Field `CCS(3-4)` writer - Capture/Compare %s selection
10pub use super::ccmr1_output::CCS_W;
11///Output compare %s clear enable
12pub use super::ccmr1_output::OC1CE;
13///Output compare %s fast enable
14pub use super::ccmr1_output::OC1FE;
15///Output compare %s mode
16pub use super::ccmr1_output::OC1M;
17///Output compare %s preload enable
18pub use super::ccmr1_output::OC1PE;
19///Field `OCCE(3-4)` reader - Output compare %s clear enable
20pub use super::ccmr1_output::OCCE_R;
21///Field `OCCE(3-4)` writer - Output compare %s clear enable
22pub use super::ccmr1_output::OCCE_W;
23///Field `OCFE(3-4)` reader - Output compare %s fast enable
24pub use super::ccmr1_output::OCFE_R;
25///Field `OCFE(3-4)` writer - Output compare %s fast enable
26pub use super::ccmr1_output::OCFE_W;
27///Field `OCM(3-4)` reader - Output compare %s mode
28pub use super::ccmr1_output::OCM_R;
29///Field `OCM(3-4)` writer - Output compare %s mode
30pub use super::ccmr1_output::OCM_W;
31///Field `OCPE(3-4)` reader - Output compare %s preload enable
32pub use super::ccmr1_output::OCPE_R;
33///Field `OCPE(3-4)` writer - Output compare %s preload enable
34pub use super::ccmr1_output::OCPE_W;
35impl R {
36    ///Capture/Compare (3-4) selection
37    ///
38    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC3S` field.</div>
39    #[inline(always)]
40    pub fn ccs(&self, n: u8) -> CCS_R {
41        #[allow(clippy::no_effect)]
42        [(); 2][n as usize];
43        CCS_R::new(((self.bits >> (n * 8)) & 3) as u8)
44    }
45    ///Iterator for array of:
46    ///Capture/Compare (3-4) selection
47    #[inline(always)]
48    pub fn ccs_iter(&self) -> impl Iterator<Item = CCS_R> + '_ {
49        (0..2).map(move |n| CCS_R::new(((self.bits >> (n * 8)) & 3) as u8))
50    }
51    ///Bits 0:1 - Capture/Compare 3 selection
52    #[inline(always)]
53    pub fn cc3s(&self) -> CCS_R {
54        CCS_R::new((self.bits & 3) as u8)
55    }
56    ///Bits 8:9 - Capture/Compare 4 selection
57    #[inline(always)]
58    pub fn cc4s(&self) -> CCS_R {
59        CCS_R::new(((self.bits >> 8) & 3) as u8)
60    }
61    ///Output compare (3-4) fast enable
62    ///
63    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3FE` field.</div>
64    #[inline(always)]
65    pub fn ocfe(&self, n: u8) -> OCFE_R {
66        #[allow(clippy::no_effect)]
67        [(); 2][n as usize];
68        OCFE_R::new(((self.bits >> (n * 8 + 2)) & 1) != 0)
69    }
70    ///Iterator for array of:
71    ///Output compare (3-4) fast enable
72    #[inline(always)]
73    pub fn ocfe_iter(&self) -> impl Iterator<Item = OCFE_R> + '_ {
74        (0..2).map(move |n| OCFE_R::new(((self.bits >> (n * 8 + 2)) & 1) != 0))
75    }
76    ///Bit 2 - Output compare 3 fast enable
77    #[inline(always)]
78    pub fn oc3fe(&self) -> OCFE_R {
79        OCFE_R::new(((self.bits >> 2) & 1) != 0)
80    }
81    ///Bit 10 - Output compare 4 fast enable
82    #[inline(always)]
83    pub fn oc4fe(&self) -> OCFE_R {
84        OCFE_R::new(((self.bits >> 10) & 1) != 0)
85    }
86    ///Output compare (3-4) preload enable
87    ///
88    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3PE` field.</div>
89    #[inline(always)]
90    pub fn ocpe(&self, n: u8) -> OCPE_R {
91        #[allow(clippy::no_effect)]
92        [(); 2][n as usize];
93        OCPE_R::new(((self.bits >> (n * 8 + 3)) & 1) != 0)
94    }
95    ///Iterator for array of:
96    ///Output compare (3-4) preload enable
97    #[inline(always)]
98    pub fn ocpe_iter(&self) -> impl Iterator<Item = OCPE_R> + '_ {
99        (0..2).map(move |n| OCPE_R::new(((self.bits >> (n * 8 + 3)) & 1) != 0))
100    }
101    ///Bit 3 - Output compare 3 preload enable
102    #[inline(always)]
103    pub fn oc3pe(&self) -> OCPE_R {
104        OCPE_R::new(((self.bits >> 3) & 1) != 0)
105    }
106    ///Bit 11 - Output compare 4 preload enable
107    #[inline(always)]
108    pub fn oc4pe(&self) -> OCPE_R {
109        OCPE_R::new(((self.bits >> 11) & 1) != 0)
110    }
111    ///Output compare (3-4) mode
112    ///
113    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3M` field.</div>
114    #[inline(always)]
115    pub fn ocm(&self, n: u8) -> OCM_R {
116        #[allow(clippy::no_effect)]
117        [(); 2][n as usize];
118        OCM_R::new(((self.bits >> (n * 8 + 4)) & 7) as u8)
119    }
120    ///Iterator for array of:
121    ///Output compare (3-4) mode
122    #[inline(always)]
123    pub fn ocm_iter(&self) -> impl Iterator<Item = OCM_R> + '_ {
124        (0..2).map(move |n| OCM_R::new(((self.bits >> (n * 8 + 4)) & 7) as u8))
125    }
126    ///Bits 4:6 - Output compare 3 mode
127    #[inline(always)]
128    pub fn oc3m(&self) -> OCM_R {
129        OCM_R::new(((self.bits >> 4) & 7) as u8)
130    }
131    ///Bits 12:14 - Output compare 4 mode
132    #[inline(always)]
133    pub fn oc4m(&self) -> OCM_R {
134        OCM_R::new(((self.bits >> 12) & 7) as u8)
135    }
136    ///Output compare (3-4) clear enable
137    ///
138    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3CE` field.</div>
139    #[inline(always)]
140    pub fn occe(&self, n: u8) -> OCCE_R {
141        #[allow(clippy::no_effect)]
142        [(); 2][n as usize];
143        OCCE_R::new(((self.bits >> (n * 8 + 7)) & 1) != 0)
144    }
145    ///Iterator for array of:
146    ///Output compare (3-4) clear enable
147    #[inline(always)]
148    pub fn occe_iter(&self) -> impl Iterator<Item = OCCE_R> + '_ {
149        (0..2).map(move |n| OCCE_R::new(((self.bits >> (n * 8 + 7)) & 1) != 0))
150    }
151    ///Bit 7 - Output compare 3 clear enable
152    #[inline(always)]
153    pub fn oc3ce(&self) -> OCCE_R {
154        OCCE_R::new(((self.bits >> 7) & 1) != 0)
155    }
156    ///Bit 15 - Output compare 4 clear enable
157    #[inline(always)]
158    pub fn oc4ce(&self) -> OCCE_R {
159        OCCE_R::new(((self.bits >> 15) & 1) != 0)
160    }
161}
162impl core::fmt::Debug for R {
163    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
164        f.debug_struct("CCMR2_Output")
165            .field("oc3ce", &self.oc3ce())
166            .field("oc4ce", &self.oc4ce())
167            .field("oc3m", &self.oc3m())
168            .field("oc4m", &self.oc4m())
169            .field("oc3pe", &self.oc3pe())
170            .field("oc4pe", &self.oc4pe())
171            .field("oc3fe", &self.oc3fe())
172            .field("oc4fe", &self.oc4fe())
173            .field("cc3s", &self.cc3s())
174            .field("cc4s", &self.cc4s())
175            .finish()
176    }
177}
178impl W {
179    ///Capture/Compare (3-4) selection
180    ///
181    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC3S` field.</div>
182    #[inline(always)]
183    pub fn ccs(&mut self, n: u8) -> CCS_W<CCMR2_OUTPUTrs> {
184        #[allow(clippy::no_effect)]
185        [(); 2][n as usize];
186        CCS_W::new(self, n * 8)
187    }
188    ///Bits 0:1 - Capture/Compare 3 selection
189    #[inline(always)]
190    pub fn cc3s(&mut self) -> CCS_W<CCMR2_OUTPUTrs> {
191        CCS_W::new(self, 0)
192    }
193    ///Bits 8:9 - Capture/Compare 4 selection
194    #[inline(always)]
195    pub fn cc4s(&mut self) -> CCS_W<CCMR2_OUTPUTrs> {
196        CCS_W::new(self, 8)
197    }
198    ///Output compare (3-4) fast enable
199    ///
200    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3FE` field.</div>
201    #[inline(always)]
202    pub fn ocfe(&mut self, n: u8) -> OCFE_W<CCMR2_OUTPUTrs> {
203        #[allow(clippy::no_effect)]
204        [(); 2][n as usize];
205        OCFE_W::new(self, n * 8 + 2)
206    }
207    ///Bit 2 - Output compare 3 fast enable
208    #[inline(always)]
209    pub fn oc3fe(&mut self) -> OCFE_W<CCMR2_OUTPUTrs> {
210        OCFE_W::new(self, 2)
211    }
212    ///Bit 10 - Output compare 4 fast enable
213    #[inline(always)]
214    pub fn oc4fe(&mut self) -> OCFE_W<CCMR2_OUTPUTrs> {
215        OCFE_W::new(self, 10)
216    }
217    ///Output compare (3-4) preload enable
218    ///
219    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3PE` field.</div>
220    #[inline(always)]
221    pub fn ocpe(&mut self, n: u8) -> OCPE_W<CCMR2_OUTPUTrs> {
222        #[allow(clippy::no_effect)]
223        [(); 2][n as usize];
224        OCPE_W::new(self, n * 8 + 3)
225    }
226    ///Bit 3 - Output compare 3 preload enable
227    #[inline(always)]
228    pub fn oc3pe(&mut self) -> OCPE_W<CCMR2_OUTPUTrs> {
229        OCPE_W::new(self, 3)
230    }
231    ///Bit 11 - Output compare 4 preload enable
232    #[inline(always)]
233    pub fn oc4pe(&mut self) -> OCPE_W<CCMR2_OUTPUTrs> {
234        OCPE_W::new(self, 11)
235    }
236    ///Output compare (3-4) mode
237    ///
238    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3M` field.</div>
239    #[inline(always)]
240    pub fn ocm(&mut self, n: u8) -> OCM_W<CCMR2_OUTPUTrs> {
241        #[allow(clippy::no_effect)]
242        [(); 2][n as usize];
243        OCM_W::new(self, n * 8 + 4)
244    }
245    ///Bits 4:6 - Output compare 3 mode
246    #[inline(always)]
247    pub fn oc3m(&mut self) -> OCM_W<CCMR2_OUTPUTrs> {
248        OCM_W::new(self, 4)
249    }
250    ///Bits 12:14 - Output compare 4 mode
251    #[inline(always)]
252    pub fn oc4m(&mut self) -> OCM_W<CCMR2_OUTPUTrs> {
253        OCM_W::new(self, 12)
254    }
255    ///Output compare (3-4) clear enable
256    ///
257    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3CE` field.</div>
258    #[inline(always)]
259    pub fn occe(&mut self, n: u8) -> OCCE_W<CCMR2_OUTPUTrs> {
260        #[allow(clippy::no_effect)]
261        [(); 2][n as usize];
262        OCCE_W::new(self, n * 8 + 7)
263    }
264    ///Bit 7 - Output compare 3 clear enable
265    #[inline(always)]
266    pub fn oc3ce(&mut self) -> OCCE_W<CCMR2_OUTPUTrs> {
267        OCCE_W::new(self, 7)
268    }
269    ///Bit 15 - Output compare 4 clear enable
270    #[inline(always)]
271    pub fn oc4ce(&mut self) -> OCCE_W<CCMR2_OUTPUTrs> {
272        OCCE_W::new(self, 15)
273    }
274}
275/**capture/compare mode register (output mode)
276
277You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
278
279See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CCMR2_Output)*/
280pub struct CCMR2_OUTPUTrs;
281impl crate::RegisterSpec for CCMR2_OUTPUTrs {
282    type Ux = u32;
283}
284///`read()` method returns [`ccmr2_output::R`](R) reader structure
285impl crate::Readable for CCMR2_OUTPUTrs {}
286///`write(|w| ..)` method takes [`ccmr2_output::W`](W) writer structure
287impl crate::Writable for CCMR2_OUTPUTrs {
288    type Safety = crate::Unsafe;
289}
290///`reset()` method sets CCMR2_Output to value 0
291impl crate::Resettable for CCMR2_OUTPUTrs {}
stm32f1/stm32f100/tim1/ccmr2_output.rs

stm32f1/stm32f100/tim1/
ccmr2_output.rs
