stm32f1/stm32f107/
mod.rs

1/*!Peripheral access API for STM32F107 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn WWDG();
21    fn PVD();
22    fn TAMPER();
23    fn RTC();
24    fn FLASH();
25    fn RCC();
26    fn EXTI0();
27    fn EXTI1();
28    fn EXTI2();
29    fn EXTI3();
30    fn EXTI4();
31    fn DMA1_CHANNEL1();
32    fn DMA1_CHANNEL2();
33    fn DMA1_CHANNEL3();
34    fn DMA1_CHANNEL4();
35    fn DMA1_CHANNEL5();
36    fn DMA1_CHANNEL6();
37    fn DMA1_CHANNEL7();
38    fn ADC1_2();
39    fn USB_HP_CAN_TX();
40    fn USB_LP_CAN_RX0();
41    fn CAN_RX1();
42    fn CAN_SCE();
43    fn EXTI9_5();
44    fn TIM1_BRK();
45    fn TIM1_UP();
46    fn TIM1_TRG_COM();
47    fn TIM1_CC();
48    fn TIM2();
49    fn TIM3();
50    fn TIM4();
51    fn I2C1_EV();
52    fn I2C1_ER();
53    fn I2C2_EV();
54    fn I2C2_ER();
55    fn SPI1();
56    fn SPI2();
57    fn USART1();
58    fn USART2();
59    fn USART3();
60    fn EXTI15_10();
61    fn RTCALARM();
62    fn USBWAKEUP();
63    fn TIM8_BRK();
64    fn TIM8_UP();
65    fn TIM8_TRG_COM();
66    fn TIM8_CC();
67    fn ADC3();
68    fn FSMC();
69    fn SDIO();
70    fn TIM5();
71    fn SPI3();
72    fn UART4();
73    fn UART5();
74    fn TIM6();
75    fn TIM7();
76    fn DMA2_CHANNEL1();
77    fn DMA2_CHANNEL2();
78    fn DMA2_CHANNEL3();
79    fn DMA2_CHANNEL4();
80    fn DMA2_CHANNEL5();
81    fn ETH();
82    fn ETH_WKUP();
83    fn CAN2_TX();
84    fn CAN2_RX0();
85    fn CAN2_RX1();
86    fn CAN2_SCE();
87    fn OTG_FS();
88}
89#[doc(hidden)]
90#[repr(C)]
91pub union Vector {
92    _handler: unsafe extern "C" fn(),
93    _reserved: u32,
94}
95#[cfg(feature = "rt")]
96#[doc(hidden)]
97#[link_section = ".vector_table.interrupts"]
98#[no_mangle]
99pub static __INTERRUPTS: [Vector; 68] = [
100    Vector { _handler: WWDG },
101    Vector { _handler: PVD },
102    Vector { _handler: TAMPER },
103    Vector { _handler: RTC },
104    Vector { _handler: FLASH },
105    Vector { _handler: RCC },
106    Vector { _handler: EXTI0 },
107    Vector { _handler: EXTI1 },
108    Vector { _handler: EXTI2 },
109    Vector { _handler: EXTI3 },
110    Vector { _handler: EXTI4 },
111    Vector {
112        _handler: DMA1_CHANNEL1,
113    },
114    Vector {
115        _handler: DMA1_CHANNEL2,
116    },
117    Vector {
118        _handler: DMA1_CHANNEL3,
119    },
120    Vector {
121        _handler: DMA1_CHANNEL4,
122    },
123    Vector {
124        _handler: DMA1_CHANNEL5,
125    },
126    Vector {
127        _handler: DMA1_CHANNEL6,
128    },
129    Vector {
130        _handler: DMA1_CHANNEL7,
131    },
132    Vector { _handler: ADC1_2 },
133    Vector {
134        _handler: USB_HP_CAN_TX,
135    },
136    Vector {
137        _handler: USB_LP_CAN_RX0,
138    },
139    Vector { _handler: CAN_RX1 },
140    Vector { _handler: CAN_SCE },
141    Vector { _handler: EXTI9_5 },
142    Vector { _handler: TIM1_BRK },
143    Vector { _handler: TIM1_UP },
144    Vector {
145        _handler: TIM1_TRG_COM,
146    },
147    Vector { _handler: TIM1_CC },
148    Vector { _handler: TIM2 },
149    Vector { _handler: TIM3 },
150    Vector { _handler: TIM4 },
151    Vector { _handler: I2C1_EV },
152    Vector { _handler: I2C1_ER },
153    Vector { _handler: I2C2_EV },
154    Vector { _handler: I2C2_ER },
155    Vector { _handler: SPI1 },
156    Vector { _handler: SPI2 },
157    Vector { _handler: USART1 },
158    Vector { _handler: USART2 },
159    Vector { _handler: USART3 },
160    Vector {
161        _handler: EXTI15_10,
162    },
163    Vector { _handler: RTCALARM },
164    Vector {
165        _handler: USBWAKEUP,
166    },
167    Vector { _handler: TIM8_BRK },
168    Vector { _handler: TIM8_UP },
169    Vector {
170        _handler: TIM8_TRG_COM,
171    },
172    Vector { _handler: TIM8_CC },
173    Vector { _handler: ADC3 },
174    Vector { _handler: FSMC },
175    Vector { _handler: SDIO },
176    Vector { _handler: TIM5 },
177    Vector { _handler: SPI3 },
178    Vector { _handler: UART4 },
179    Vector { _handler: UART5 },
180    Vector { _handler: TIM6 },
181    Vector { _handler: TIM7 },
182    Vector {
183        _handler: DMA2_CHANNEL1,
184    },
185    Vector {
186        _handler: DMA2_CHANNEL2,
187    },
188    Vector {
189        _handler: DMA2_CHANNEL3,
190    },
191    Vector {
192        _handler: DMA2_CHANNEL4,
193    },
194    Vector {
195        _handler: DMA2_CHANNEL5,
196    },
197    Vector { _handler: ETH },
198    Vector { _handler: ETH_WKUP },
199    Vector { _handler: CAN2_TX },
200    Vector { _handler: CAN2_RX0 },
201    Vector { _handler: CAN2_RX1 },
202    Vector { _handler: CAN2_SCE },
203    Vector { _handler: OTG_FS },
204];
205///Enumeration of all the interrupts.
206#[cfg_attr(feature = "defmt", derive(defmt::Format))]
207#[derive(Copy, Clone, Debug, PartialEq, Eq)]
208#[repr(u16)]
209pub enum Interrupt {
210    ///0 - Window Watchdog interrupt
211    WWDG = 0,
212    ///1 - PVD through EXTI line detection interrupt
213    PVD = 1,
214    ///2 - Tamper interrupt
215    TAMPER = 2,
216    ///3 - RTC global interrupt
217    RTC = 3,
218    ///4 - Flash global interrupt
219    FLASH = 4,
220    ///5 - RCC global interrupt
221    RCC = 5,
222    ///6 - EXTI Line0 interrupt
223    EXTI0 = 6,
224    ///7 - EXTI Line1 interrupt
225    EXTI1 = 7,
226    ///8 - EXTI Line2 interrupt
227    EXTI2 = 8,
228    ///9 - EXTI Line3 interrupt
229    EXTI3 = 9,
230    ///10 - EXTI Line4 interrupt
231    EXTI4 = 10,
232    ///11 - DMA1 Channel1 global interrupt
233    DMA1_CHANNEL1 = 11,
234    ///12 - DMA1 Channel2 global interrupt
235    DMA1_CHANNEL2 = 12,
236    ///13 - DMA1 Channel3 global interrupt
237    DMA1_CHANNEL3 = 13,
238    ///14 - DMA1 Channel4 global interrupt
239    DMA1_CHANNEL4 = 14,
240    ///15 - DMA1 Channel5 global interrupt
241    DMA1_CHANNEL5 = 15,
242    ///16 - DMA1 Channel6 global interrupt
243    DMA1_CHANNEL6 = 16,
244    ///17 - DMA1 Channel7 global interrupt
245    DMA1_CHANNEL7 = 17,
246    ///18 - ADC1 and ADC2 global interrupt
247    ADC1_2 = 18,
248    ///19 - USB High Priority or CAN TX interrupts
249    USB_HP_CAN_TX = 19,
250    ///20 - USB Low Priority or CAN RX0 interrupts
251    USB_LP_CAN_RX0 = 20,
252    ///21 - CAN RX1 interrupts
253    CAN_RX1 = 21,
254    ///22 - CAN SCE interrupt
255    CAN_SCE = 22,
256    ///23 - EXTI Line\[9:5\] interrupts
257    EXTI9_5 = 23,
258    ///24 - TIM1 Break interrupt
259    TIM1_BRK = 24,
260    ///25 - TIM1 Update interrupt
261    TIM1_UP = 25,
262    ///26 - TIM1 Trigger and Commutation interrupts
263    TIM1_TRG_COM = 26,
264    ///27 - TIM1 Capture Compare interrupt
265    TIM1_CC = 27,
266    ///28 - TIM2 global interrupt
267    TIM2 = 28,
268    ///29 - TIM3 global interrupt
269    TIM3 = 29,
270    ///30 - TIM4 global interrupt
271    TIM4 = 30,
272    ///31 - I2C1 event interrupt
273    I2C1_EV = 31,
274    ///32 - I2C1 error interrupt
275    I2C1_ER = 32,
276    ///33 - I2C2 event interrupt
277    I2C2_EV = 33,
278    ///34 - I2C2 error interrupt
279    I2C2_ER = 34,
280    ///35 - SPI1 global interrupt
281    SPI1 = 35,
282    ///36 - SPI2 global interrupt
283    SPI2 = 36,
284    ///37 - USART1 global interrupt
285    USART1 = 37,
286    ///38 - USART2 global interrupt
287    USART2 = 38,
288    ///39 - USART3 global interrupt
289    USART3 = 39,
290    ///40 - EXTI Line\[15:10\] interrupts
291    EXTI15_10 = 40,
292    ///41 - RTC Alarms through EXTI line interrupt
293    RTCALARM = 41,
294    ///42 - USB wakeup from suspend through EXTI line interrupt
295    USBWAKEUP = 42,
296    ///43 - TIM8 Break interrupt
297    TIM8_BRK = 43,
298    ///44 - TIM8 Update interrupt
299    TIM8_UP = 44,
300    ///45 - TIM8 Trigger and Commutation interrupts
301    TIM8_TRG_COM = 45,
302    ///46 - TIM8 Capture Compare interrupt
303    TIM8_CC = 46,
304    ///47 - ADC3 global interrupt
305    ADC3 = 47,
306    ///48 - FSMC global interrupt
307    FSMC = 48,
308    ///49 - SDIO global interrupt
309    SDIO = 49,
310    ///50 - TIM5 global interrupt
311    TIM5 = 50,
312    ///51 - SPI3 global interrupt
313    SPI3 = 51,
314    ///52 - UART4 global interrupt
315    UART4 = 52,
316    ///53 - UART5 global interrupt
317    UART5 = 53,
318    ///54 - TIM6 global interrupt
319    TIM6 = 54,
320    ///55 - TIM7 global interrupt
321    TIM7 = 55,
322    ///56 - DMA2 Channel1 global interrupt
323    DMA2_CHANNEL1 = 56,
324    ///57 - DMA2 Channel2 global interrupt
325    DMA2_CHANNEL2 = 57,
326    ///58 - DMA2 Channel3 global interrupt
327    DMA2_CHANNEL3 = 58,
328    ///59 - DMA2 Channel4 global interrupt
329    DMA2_CHANNEL4 = 59,
330    ///60 - DMA2 Channel5 global interrupt
331    DMA2_CHANNEL5 = 60,
332    ///61 - Ethernet global interrupt
333    ETH = 61,
334    ///62 - Ethernet Wakeup through EXTI line interrupt
335    ETH_WKUP = 62,
336    ///63 - CAN2 TX interrupts
337    CAN2_TX = 63,
338    ///64 - CAN2 RX0 interrupts
339    CAN2_RX0 = 64,
340    ///65 - CAN2 RX1 interrupts
341    CAN2_RX1 = 65,
342    ///66 - CAN2 SCE interrupt
343    CAN2_SCE = 66,
344    ///67 - USB On The Go FS global interrupt
345    OTG_FS = 67,
346}
347unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
348    #[inline(always)]
349    fn number(self) -> u16 {
350        self as u16
351    }
352}
353///Power control
354///
355///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#PWR)
356pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
357impl core::fmt::Debug for PWR {
358    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
359        f.debug_struct("PWR").finish()
360    }
361}
362///Power control
363pub mod pwr;
364///Reset and clock control
365///
366///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RCC)
367pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
368impl core::fmt::Debug for RCC {
369    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
370        f.debug_struct("RCC").finish()
371    }
372}
373///Reset and clock control
374pub mod rcc;
375///General purpose I/O
376///
377///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
378pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4001_0800>;
379impl core::fmt::Debug for GPIOA {
380    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
381        f.debug_struct("GPIOA").finish()
382    }
383}
384///General purpose I/O
385pub mod gpioa;
386///General purpose I/O
387///
388///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
389pub type GPIOB = crate::Periph<gpioa::RegisterBlock, 0x4001_0c00>;
390impl core::fmt::Debug for GPIOB {
391    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
392        f.debug_struct("GPIOB").finish()
393    }
394}
395///General purpose I/O
396pub use self::gpioa as gpiob;
397///General purpose I/O
398///
399///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
400pub type GPIOC = crate::Periph<gpioa::RegisterBlock, 0x4001_1000>;
401impl core::fmt::Debug for GPIOC {
402    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
403        f.debug_struct("GPIOC").finish()
404    }
405}
406///General purpose I/O
407pub use self::gpioa as gpioc;
408///General purpose I/O
409///
410///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
411pub type GPIOD = crate::Periph<gpioa::RegisterBlock, 0x4001_1400>;
412impl core::fmt::Debug for GPIOD {
413    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
414        f.debug_struct("GPIOD").finish()
415    }
416}
417///General purpose I/O
418pub use self::gpioa as gpiod;
419///General purpose I/O
420///
421///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
422pub type GPIOE = crate::Periph<gpioa::RegisterBlock, 0x4001_1800>;
423impl core::fmt::Debug for GPIOE {
424    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
425        f.debug_struct("GPIOE").finish()
426    }
427}
428///General purpose I/O
429pub use self::gpioa as gpioe;
430///General purpose I/O
431///
432///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
433pub type GPIOF = crate::Periph<gpioa::RegisterBlock, 0x4001_1c00>;
434impl core::fmt::Debug for GPIOF {
435    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
436        f.debug_struct("GPIOF").finish()
437    }
438}
439///General purpose I/O
440pub use self::gpioa as gpiof;
441///General purpose I/O
442///
443///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#GPIOA)
444pub type GPIOG = crate::Periph<gpioa::RegisterBlock, 0x4001_2000>;
445impl core::fmt::Debug for GPIOG {
446    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
447        f.debug_struct("GPIOG").finish()
448    }
449}
450///General purpose I/O
451pub use self::gpioa as gpiog;
452///Alternate function I/O
453///
454///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#AFIO)
455pub type AFIO = crate::Periph<afio::RegisterBlock, 0x4001_0000>;
456impl core::fmt::Debug for AFIO {
457    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
458        f.debug_struct("AFIO").finish()
459    }
460}
461///Alternate function I/O
462pub mod afio;
463///EXTI
464///
465///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#EXTI)
466pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
467impl core::fmt::Debug for EXTI {
468    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
469        f.debug_struct("EXTI").finish()
470    }
471}
472///EXTI
473pub mod exti;
474///DMA controller
475///
476///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#DMA1)
477pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
478impl core::fmt::Debug for DMA1 {
479    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
480        f.debug_struct("DMA1").finish()
481    }
482}
483///DMA controller
484pub mod dma1;
485///DMA controller
486///
487///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#DMA1)
488pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
489impl core::fmt::Debug for DMA2 {
490    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
491        f.debug_struct("DMA2").finish()
492    }
493}
494///DMA controller
495pub use self::dma1 as dma2;
496///Real time clock
497///
498///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#RTC)
499pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
500impl core::fmt::Debug for RTC {
501    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
502        f.debug_struct("RTC").finish()
503    }
504}
505///Real time clock
506pub mod rtc;
507///Backup registers
508///
509///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#BKP)
510pub type BKP = crate::Periph<bkp::RegisterBlock, 0x4000_6c04>;
511impl core::fmt::Debug for BKP {
512    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
513        f.debug_struct("BKP").finish()
514    }
515}
516///Backup registers
517pub mod bkp;
518///Independent watchdog
519///
520///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#IWDG)
521pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
522impl core::fmt::Debug for IWDG {
523    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
524        f.debug_struct("IWDG").finish()
525    }
526}
527///Independent watchdog
528pub mod iwdg;
529///Window watchdog
530///
531///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#WWDG)
532pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
533impl core::fmt::Debug for WWDG {
534    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
535        f.debug_struct("WWDG").finish()
536    }
537}
538///Window watchdog
539pub mod wwdg;
540///Advanced timer
541///
542///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM1)
543pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
544impl core::fmt::Debug for TIM1 {
545    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
546        f.debug_struct("TIM1").finish()
547    }
548}
549///Advanced timer
550pub mod tim1;
551///General purpose timer
552///
553///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM2)
554pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
555impl core::fmt::Debug for TIM2 {
556    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
557        f.debug_struct("TIM2").finish()
558    }
559}
560///General purpose timer
561pub mod tim2;
562///General purpose timer
563///
564///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM2)
565pub type TIM3 = crate::Periph<tim2::RegisterBlock, 0x4000_0400>;
566impl core::fmt::Debug for TIM3 {
567    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
568        f.debug_struct("TIM3").finish()
569    }
570}
571///General purpose timer
572pub use self::tim2 as tim3;
573///General purpose timer
574///
575///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM2)
576pub type TIM4 = crate::Periph<tim2::RegisterBlock, 0x4000_0800>;
577impl core::fmt::Debug for TIM4 {
578    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
579        f.debug_struct("TIM4").finish()
580    }
581}
582///General purpose timer
583pub use self::tim2 as tim4;
584///General purpose timer
585///
586///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM2)
587pub type TIM5 = crate::Periph<tim2::RegisterBlock, 0x4000_0c00>;
588impl core::fmt::Debug for TIM5 {
589    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
590        f.debug_struct("TIM5").finish()
591    }
592}
593///General purpose timer
594pub use self::tim2 as tim5;
595///Basic timer
596///
597///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM6)
598pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
599impl core::fmt::Debug for TIM6 {
600    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
601        f.debug_struct("TIM6").finish()
602    }
603}
604///Basic timer
605pub mod tim6;
606///Basic timer
607///
608///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM6)
609pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
610impl core::fmt::Debug for TIM7 {
611    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
612        f.debug_struct("TIM7").finish()
613    }
614}
615///Basic timer
616pub use self::tim6 as tim7;
617///Inter integrated circuit
618///
619///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#I2C1)
620pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
621impl core::fmt::Debug for I2C1 {
622    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
623        f.debug_struct("I2C1").finish()
624    }
625}
626///Inter integrated circuit
627pub mod i2c1;
628///Inter integrated circuit
629///
630///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#I2C1)
631pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
632impl core::fmt::Debug for I2C2 {
633    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
634        f.debug_struct("I2C2").finish()
635    }
636}
637///Inter integrated circuit
638pub use self::i2c1 as i2c2;
639///Serial peripheral interface
640///
641///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SPI1)
642pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
643impl core::fmt::Debug for SPI1 {
644    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
645        f.debug_struct("SPI1").finish()
646    }
647}
648///Serial peripheral interface
649pub mod spi1;
650///Serial peripheral interface
651///
652///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SPI1)
653pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
654impl core::fmt::Debug for SPI2 {
655    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
656        f.debug_struct("SPI2").finish()
657    }
658}
659///Serial peripheral interface
660pub use self::spi1 as spi2;
661///Serial peripheral interface
662///
663///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SPI1)
664pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
665impl core::fmt::Debug for SPI3 {
666    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
667        f.debug_struct("SPI3").finish()
668    }
669}
670///Serial peripheral interface
671pub use self::spi1 as spi3;
672///Universal synchronous asynchronous receiver transmitter
673///
674///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1)
675pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
676impl core::fmt::Debug for USART1 {
677    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
678        f.debug_struct("USART1").finish()
679    }
680}
681///Universal synchronous asynchronous receiver transmitter
682pub mod usart1;
683///Universal synchronous asynchronous receiver transmitter
684///
685///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1)
686pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
687impl core::fmt::Debug for USART2 {
688    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
689        f.debug_struct("USART2").finish()
690    }
691}
692///Universal synchronous asynchronous receiver transmitter
693pub use self::usart1 as usart2;
694///Universal synchronous asynchronous receiver transmitter
695///
696///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USART1)
697pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
698impl core::fmt::Debug for USART3 {
699    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
700        f.debug_struct("USART3").finish()
701    }
702}
703///Universal synchronous asynchronous receiver transmitter
704pub use self::usart1 as usart3;
705///Analog to digital converter
706///
707///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#ADC1)
708pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2400>;
709impl core::fmt::Debug for ADC1 {
710    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
711        f.debug_struct("ADC1").finish()
712    }
713}
714///Analog to digital converter
715pub mod adc1;
716///Analog to digital converter
717///
718///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#ADC2)
719pub type ADC2 = crate::Periph<adc2::RegisterBlock, 0x4001_2800>;
720impl core::fmt::Debug for ADC2 {
721    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
722        f.debug_struct("ADC2").finish()
723    }
724}
725///Analog to digital converter
726pub mod adc2;
727///Controller area network
728///
729///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#CAN1)
730pub type CAN1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
731impl core::fmt::Debug for CAN1 {
732    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
733        f.debug_struct("CAN1").finish()
734    }
735}
736///Controller area network
737pub mod can1;
738///Controller area network
739///
740///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#CAN1)
741pub type CAN2 = crate::Periph<can1::RegisterBlock, 0x4000_6800>;
742impl core::fmt::Debug for CAN2 {
743    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
744        f.debug_struct("CAN2").finish()
745    }
746}
747///Controller area network
748pub use self::can1 as can2;
749///Ethernet: media access control
750///
751///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#Ethernet_MAC)
752pub type ETHERNET_MAC = crate::Periph<ethernet_mac::RegisterBlock, 0x4002_8000>;
753impl core::fmt::Debug for ETHERNET_MAC {
754    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
755        f.debug_struct("ETHERNET_MAC").finish()
756    }
757}
758///Ethernet: media access control
759pub mod ethernet_mac;
760///Ethernet: MAC management counters
761///
762///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#Ethernet_MMC)
763pub type ETHERNET_MMC = crate::Periph<ethernet_mmc::RegisterBlock, 0x4002_8100>;
764impl core::fmt::Debug for ETHERNET_MMC {
765    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
766        f.debug_struct("ETHERNET_MMC").finish()
767    }
768}
769///Ethernet: MAC management counters
770pub mod ethernet_mmc;
771///Ethernet: Precision time protocol
772///
773///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#Ethernet_PTP)
774pub type ETHERNET_PTP = crate::Periph<ethernet_ptp::RegisterBlock, 0x4002_8700>;
775impl core::fmt::Debug for ETHERNET_PTP {
776    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
777        f.debug_struct("ETHERNET_PTP").finish()
778    }
779}
780///Ethernet: Precision time protocol
781pub mod ethernet_ptp;
782///Ethernet: DMA controller operation
783///
784///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#Ethernet_DMA)
785pub type ETHERNET_DMA = crate::Periph<ethernet_dma::RegisterBlock, 0x4002_9000>;
786impl core::fmt::Debug for ETHERNET_DMA {
787    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
788        f.debug_struct("ETHERNET_DMA").finish()
789    }
790}
791///Ethernet: DMA controller operation
792pub mod ethernet_dma;
793///USB on the go full speed
794///
795///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#OTG_FS_GLOBAL)
796pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
797impl core::fmt::Debug for OTG_FS_GLOBAL {
798    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
799        f.debug_struct("OTG_FS_GLOBAL").finish()
800    }
801}
802///USB on the go full speed
803pub mod otg_fs_global;
804///USB on the go full speed
805///
806///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#OTG_FS_HOST)
807pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
808impl core::fmt::Debug for OTG_FS_HOST {
809    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
810        f.debug_struct("OTG_FS_HOST").finish()
811    }
812}
813///USB on the go full speed
814pub mod otg_fs_host;
815///USB on the go full speed
816///
817///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#OTG_FS_DEVICE)
818pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
819impl core::fmt::Debug for OTG_FS_DEVICE {
820    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
821        f.debug_struct("OTG_FS_DEVICE").finish()
822    }
823}
824///USB on the go full speed
825pub mod otg_fs_device;
826///USB on the go full speed
827///
828///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#OTG_FS_PWRCLK)
829pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
830impl core::fmt::Debug for OTG_FS_PWRCLK {
831    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
832        f.debug_struct("OTG_FS_PWRCLK").finish()
833    }
834}
835///USB on the go full speed
836pub mod otg_fs_pwrclk;
837///Digital to analog converter
838///
839///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#DAC)
840pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
841impl core::fmt::Debug for DAC {
842    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
843        f.debug_struct("DAC").finish()
844    }
845}
846///Digital to analog converter
847pub mod dac;
848///Debug support
849///
850///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#DBGMCU)
851pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
852impl core::fmt::Debug for DBGMCU {
853    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
854        f.debug_struct("DBGMCU").finish()
855    }
856}
857///Debug support
858pub mod dbgmcu;
859///Universal asynchronous receiver transmitter
860///
861///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#UART4)
862pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
863impl core::fmt::Debug for UART4 {
864    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
865        f.debug_struct("UART4").finish()
866    }
867}
868///Universal asynchronous receiver transmitter
869pub mod uart4;
870///Universal asynchronous receiver transmitter
871///
872///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#UART4)
873pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
874impl core::fmt::Debug for UART5 {
875    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
876        f.debug_struct("UART5").finish()
877    }
878}
879///Universal asynchronous receiver transmitter
880pub use self::uart4 as uart5;
881///CRC calculation unit
882///
883///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#CRC)
884pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
885impl core::fmt::Debug for CRC {
886    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
887        f.debug_struct("CRC").finish()
888    }
889}
890///CRC calculation unit
891pub mod crc;
892///FLASH
893///
894///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#FLASH)
895pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
896impl core::fmt::Debug for FLASH {
897    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
898        f.debug_struct("FLASH").finish()
899    }
900}
901///FLASH
902pub mod flash;
903///Flexible static memory controller
904///
905///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#FSMC)
906pub type FSMC = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
907impl core::fmt::Debug for FSMC {
908    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
909        f.debug_struct("FSMC").finish()
910    }
911}
912///Flexible static memory controller
913pub mod fsmc;
914///Secure digital input/output interface
915///
916///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SDIO)
917pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_8000>;
918impl core::fmt::Debug for SDIO {
919    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
920        f.debug_struct("SDIO").finish()
921    }
922}
923///Secure digital input/output interface
924pub mod sdio;
925///General purpose timer
926///
927///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM13)
928pub type TIM13 = crate::Periph<tim13::RegisterBlock, 0x4000_1c00>;
929impl core::fmt::Debug for TIM13 {
930    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
931        f.debug_struct("TIM13").finish()
932    }
933}
934///General purpose timer
935pub mod tim13;
936///General purpose timer
937///
938///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM13)
939pub type TIM11 = crate::Periph<tim13::RegisterBlock, 0x4001_5400>;
940impl core::fmt::Debug for TIM11 {
941    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
942        f.debug_struct("TIM11").finish()
943    }
944}
945///General purpose timer
946pub use self::tim13 as tim11;
947///General purpose timer
948///
949///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM13)
950pub type TIM10 = crate::Periph<tim13::RegisterBlock, 0x4001_5000>;
951impl core::fmt::Debug for TIM10 {
952    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
953        f.debug_struct("TIM10").finish()
954    }
955}
956///General purpose timer
957pub use self::tim13 as tim10;
958///General purpose timer
959///
960///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM9)
961pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4c00>;
962impl core::fmt::Debug for TIM9 {
963    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
964        f.debug_struct("TIM9").finish()
965    }
966}
967///General purpose timer
968pub mod tim9;
969///General purpose timer
970///
971///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM9)
972pub type TIM12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
973impl core::fmt::Debug for TIM12 {
974    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
975        f.debug_struct("TIM12").finish()
976    }
977}
978///General purpose timer
979pub use self::tim9 as tim12;
980///Analog to digital converter
981///
982///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#ADC3)
983pub type ADC3 = crate::Periph<adc3::RegisterBlock, 0x4001_3c00>;
984impl core::fmt::Debug for ADC3 {
985    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
986        f.debug_struct("ADC3").finish()
987    }
988}
989///Analog to digital converter
990pub mod adc3;
991///Advanced timer
992///
993///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM1)
994pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_3400>;
995impl core::fmt::Debug for TIM8 {
996    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
997        f.debug_struct("TIM8").finish()
998    }
999}
1000///Advanced timer
1001pub use self::tim1 as tim8;
1002///Universal serial bus full-speed device interface
1003///
1004///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#USB)
1005pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
1006impl core::fmt::Debug for USB {
1007    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1008        f.debug_struct("USB").finish()
1009    }
1010}
1011///Universal serial bus full-speed device interface
1012pub mod usb;
1013///General purpose timer
1014///
1015///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM13)
1016pub type TIM14 = crate::Periph<tim13::RegisterBlock, 0x4000_2000>;
1017impl core::fmt::Debug for TIM14 {
1018    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1019        f.debug_struct("TIM14").finish()
1020    }
1021}
1022///General purpose timer
1023pub use self::tim13 as tim14;
1024///System control block ACTLR
1025///
1026///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#SCB_ACTRL)
1027pub type SCB_ACTRL = crate::Periph<scb_actrl::RegisterBlock, 0xe000_e008>;
1028impl core::fmt::Debug for SCB_ACTRL {
1029    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1030        f.debug_struct("SCB_ACTRL").finish()
1031    }
1032}
1033///System control block ACTLR
1034pub mod scb_actrl;
1035///Nested vectored interrupt controller
1036///
1037///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#NVIC_STIR)
1038pub type NVIC_STIR = crate::Periph<nvic_stir::RegisterBlock, 0xe000_ef00>;
1039impl core::fmt::Debug for NVIC_STIR {
1040    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1041        f.debug_struct("NVIC_STIR").finish()
1042    }
1043}
1044///Nested vectored interrupt controller
1045pub mod nvic_stir;
1046///SysTick timer
1047///
1048///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#STK)
1049pub type STK = crate::Periph<stk::RegisterBlock, 0xe000_e010>;
1050impl core::fmt::Debug for STK {
1051    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1052        f.debug_struct("STK").finish()
1053    }
1054}
1055///SysTick timer
1056pub mod stk;
1057#[no_mangle]
1058static mut DEVICE_PERIPHERALS: bool = false;
1059/// All the peripherals.
1060#[allow(non_snake_case)]
1061pub struct Peripherals {
1062    ///PWR
1063    pub PWR: PWR,
1064    ///RCC
1065    pub RCC: RCC,
1066    ///GPIOA
1067    pub GPIOA: GPIOA,
1068    ///GPIOB
1069    pub GPIOB: GPIOB,
1070    ///GPIOC
1071    pub GPIOC: GPIOC,
1072    ///GPIOD
1073    pub GPIOD: GPIOD,
1074    ///GPIOE
1075    pub GPIOE: GPIOE,
1076    ///GPIOF
1077    pub GPIOF: GPIOF,
1078    ///GPIOG
1079    pub GPIOG: GPIOG,
1080    ///AFIO
1081    pub AFIO: AFIO,
1082    ///EXTI
1083    pub EXTI: EXTI,
1084    ///DMA1
1085    pub DMA1: DMA1,
1086    ///DMA2
1087    pub DMA2: DMA2,
1088    ///RTC
1089    pub RTC: RTC,
1090    ///BKP
1091    pub BKP: BKP,
1092    ///IWDG
1093    pub IWDG: IWDG,
1094    ///WWDG
1095    pub WWDG: WWDG,
1096    ///TIM1
1097    pub TIM1: TIM1,
1098    ///TIM2
1099    pub TIM2: TIM2,
1100    ///TIM3
1101    pub TIM3: TIM3,
1102    ///TIM4
1103    pub TIM4: TIM4,
1104    ///TIM5
1105    pub TIM5: TIM5,
1106    ///TIM6
1107    pub TIM6: TIM6,
1108    ///TIM7
1109    pub TIM7: TIM7,
1110    ///I2C1
1111    pub I2C1: I2C1,
1112    ///I2C2
1113    pub I2C2: I2C2,
1114    ///SPI1
1115    pub SPI1: SPI1,
1116    ///SPI2
1117    pub SPI2: SPI2,
1118    ///SPI3
1119    pub SPI3: SPI3,
1120    ///USART1
1121    pub USART1: USART1,
1122    ///USART2
1123    pub USART2: USART2,
1124    ///USART3
1125    pub USART3: USART3,
1126    ///ADC1
1127    pub ADC1: ADC1,
1128    ///ADC2
1129    pub ADC2: ADC2,
1130    ///CAN1
1131    pub CAN1: CAN1,
1132    ///CAN2
1133    pub CAN2: CAN2,
1134    ///Ethernet_MAC
1135    pub ETHERNET_MAC: ETHERNET_MAC,
1136    ///Ethernet_MMC
1137    pub ETHERNET_MMC: ETHERNET_MMC,
1138    ///Ethernet_PTP
1139    pub ETHERNET_PTP: ETHERNET_PTP,
1140    ///Ethernet_DMA
1141    pub ETHERNET_DMA: ETHERNET_DMA,
1142    ///OTG_FS_GLOBAL
1143    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
1144    ///OTG_FS_HOST
1145    pub OTG_FS_HOST: OTG_FS_HOST,
1146    ///OTG_FS_DEVICE
1147    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
1148    ///OTG_FS_PWRCLK
1149    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
1150    ///DAC
1151    pub DAC: DAC,
1152    ///DBGMCU
1153    pub DBGMCU: DBGMCU,
1154    ///UART4
1155    pub UART4: UART4,
1156    ///UART5
1157    pub UART5: UART5,
1158    ///CRC
1159    pub CRC: CRC,
1160    ///FLASH
1161    pub FLASH: FLASH,
1162    ///FSMC
1163    pub FSMC: FSMC,
1164    ///SDIO
1165    pub SDIO: SDIO,
1166    ///TIM13
1167    pub TIM13: TIM13,
1168    ///TIM11
1169    pub TIM11: TIM11,
1170    ///TIM10
1171    pub TIM10: TIM10,
1172    ///TIM9
1173    pub TIM9: TIM9,
1174    ///TIM12
1175    pub TIM12: TIM12,
1176    ///ADC3
1177    pub ADC3: ADC3,
1178    ///TIM8
1179    pub TIM8: TIM8,
1180    ///USB
1181    pub USB: USB,
1182    ///TIM14
1183    pub TIM14: TIM14,
1184    ///SCB_ACTRL
1185    pub SCB_ACTRL: SCB_ACTRL,
1186    ///NVIC_STIR
1187    pub NVIC_STIR: NVIC_STIR,
1188    ///STK
1189    pub STK: STK,
1190}
1191impl Peripherals {
1192    /// Returns all the peripherals *once*.
1193    #[cfg(feature = "critical-section")]
1194    #[inline]
1195    pub fn take() -> Option<Self> {
1196        critical_section::with(|_| {
1197            if unsafe { DEVICE_PERIPHERALS } {
1198                return None;
1199            }
1200            Some(unsafe { Peripherals::steal() })
1201        })
1202    }
1203    /// Unchecked version of `Peripherals::take`.
1204    ///
1205    /// # Safety
1206    ///
1207    /// Each of the returned peripherals must be used at most once.
1208    #[inline]
1209    pub unsafe fn steal() -> Self {
1210        DEVICE_PERIPHERALS = true;
1211        Peripherals {
1212            PWR: PWR::steal(),
1213            RCC: RCC::steal(),
1214            GPIOA: GPIOA::steal(),
1215            GPIOB: GPIOB::steal(),
1216            GPIOC: GPIOC::steal(),
1217            GPIOD: GPIOD::steal(),
1218            GPIOE: GPIOE::steal(),
1219            GPIOF: GPIOF::steal(),
1220            GPIOG: GPIOG::steal(),
1221            AFIO: AFIO::steal(),
1222            EXTI: EXTI::steal(),
1223            DMA1: DMA1::steal(),
1224            DMA2: DMA2::steal(),
1225            RTC: RTC::steal(),
1226            BKP: BKP::steal(),
1227            IWDG: IWDG::steal(),
1228            WWDG: WWDG::steal(),
1229            TIM1: TIM1::steal(),
1230            TIM2: TIM2::steal(),
1231            TIM3: TIM3::steal(),
1232            TIM4: TIM4::steal(),
1233            TIM5: TIM5::steal(),
1234            TIM6: TIM6::steal(),
1235            TIM7: TIM7::steal(),
1236            I2C1: I2C1::steal(),
1237            I2C2: I2C2::steal(),
1238            SPI1: SPI1::steal(),
1239            SPI2: SPI2::steal(),
1240            SPI3: SPI3::steal(),
1241            USART1: USART1::steal(),
1242            USART2: USART2::steal(),
1243            USART3: USART3::steal(),
1244            ADC1: ADC1::steal(),
1245            ADC2: ADC2::steal(),
1246            CAN1: CAN1::steal(),
1247            CAN2: CAN2::steal(),
1248            ETHERNET_MAC: ETHERNET_MAC::steal(),
1249            ETHERNET_MMC: ETHERNET_MMC::steal(),
1250            ETHERNET_PTP: ETHERNET_PTP::steal(),
1251            ETHERNET_DMA: ETHERNET_DMA::steal(),
1252            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
1253            OTG_FS_HOST: OTG_FS_HOST::steal(),
1254            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
1255            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
1256            DAC: DAC::steal(),
1257            DBGMCU: DBGMCU::steal(),
1258            UART4: UART4::steal(),
1259            UART5: UART5::steal(),
1260            CRC: CRC::steal(),
1261            FLASH: FLASH::steal(),
1262            FSMC: FSMC::steal(),
1263            SDIO: SDIO::steal(),
1264            TIM13: TIM13::steal(),
1265            TIM11: TIM11::steal(),
1266            TIM10: TIM10::steal(),
1267            TIM9: TIM9::steal(),
1268            TIM12: TIM12::steal(),
1269            ADC3: ADC3::steal(),
1270            TIM8: TIM8::steal(),
1271            USB: USB::steal(),
1272            TIM14: TIM14::steal(),
1273            SCB_ACTRL: SCB_ACTRL::steal(),
1274            NVIC_STIR: NVIC_STIR::steal(),
1275            STK: STK::steal(),
1276        }
1277    }
1278}
stm32f1/stm32f107/mod.rs

stm32f1/stm32f107/
mod.rs
