stm32f1/stm32f102/
mod.rs

1/*!Peripheral access API for STM32F102 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn WWDG();
21    fn PVD();
22    fn TAMPER();
23    fn RTC();
24    fn FLASH();
25    fn RCC();
26    fn EXTI0();
27    fn EXTI1();
28    fn EXTI2();
29    fn EXTI3();
30    fn EXTI4();
31    fn DMA1_CHANNEL1();
32    fn DMA1_CHANNEL2();
33    fn DMA1_CHANNEL3();
34    fn DMA1_CHANNEL4();
35    fn DMA1_CHANNEL5();
36    fn DMA1_CHANNEL6();
37    fn DMA1_CHANNEL7();
38    fn ADC1_2();
39    fn USB_HP_CAN_TX();
40    fn USB_LP_CAN_RX0();
41    fn EXTI9_5();
42    fn TIM1_BRK();
43    fn TIM1_UP();
44    fn TIM1_TRG_COM();
45    fn TIM1_CC();
46    fn TIM2();
47    fn TIM3();
48    fn TIM4();
49    fn I2C1_EV();
50    fn I2C1_ER();
51    fn I2C2_EV();
52    fn I2C2_ER();
53    fn SPI1();
54    fn SPI2();
55    fn USART1();
56    fn USART2();
57    fn USART3();
58    fn EXTI15_10();
59    fn RTCALARM();
60    fn USBWAKEUP();
61    fn TIM8_BRK();
62    fn TIM8_UP();
63    fn TIM8_TRG_COM();
64    fn TIM8_CC();
65    fn ADC3();
66    fn FSMC();
67    fn SDIO();
68    fn TIM5();
69    fn SPI3();
70    fn UART4();
71    fn UART5();
72    fn TIM6();
73    fn TIM7();
74    fn DMA2_CHANNEL1();
75    fn DMA2_CHANNEL2();
76    fn DMA2_CHANNEL3();
77    fn DMA2_CHANNEL4_5();
78}
79#[doc(hidden)]
80#[repr(C)]
81pub union Vector {
82    _handler: unsafe extern "C" fn(),
83    _reserved: u32,
84}
85#[cfg(feature = "rt")]
86#[doc(hidden)]
87#[link_section = ".vector_table.interrupts"]
88#[no_mangle]
89pub static __INTERRUPTS: [Vector; 60] = [
90    Vector { _handler: WWDG },
91    Vector { _handler: PVD },
92    Vector { _handler: TAMPER },
93    Vector { _handler: RTC },
94    Vector { _handler: FLASH },
95    Vector { _handler: RCC },
96    Vector { _handler: EXTI0 },
97    Vector { _handler: EXTI1 },
98    Vector { _handler: EXTI2 },
99    Vector { _handler: EXTI3 },
100    Vector { _handler: EXTI4 },
101    Vector {
102        _handler: DMA1_CHANNEL1,
103    },
104    Vector {
105        _handler: DMA1_CHANNEL2,
106    },
107    Vector {
108        _handler: DMA1_CHANNEL3,
109    },
110    Vector {
111        _handler: DMA1_CHANNEL4,
112    },
113    Vector {
114        _handler: DMA1_CHANNEL5,
115    },
116    Vector {
117        _handler: DMA1_CHANNEL6,
118    },
119    Vector {
120        _handler: DMA1_CHANNEL7,
121    },
122    Vector { _handler: ADC1_2 },
123    Vector {
124        _handler: USB_HP_CAN_TX,
125    },
126    Vector {
127        _handler: USB_LP_CAN_RX0,
128    },
129    Vector { _reserved: 0 },
130    Vector { _reserved: 0 },
131    Vector { _handler: EXTI9_5 },
132    Vector { _handler: TIM1_BRK },
133    Vector { _handler: TIM1_UP },
134    Vector {
135        _handler: TIM1_TRG_COM,
136    },
137    Vector { _handler: TIM1_CC },
138    Vector { _handler: TIM2 },
139    Vector { _handler: TIM3 },
140    Vector { _handler: TIM4 },
141    Vector { _handler: I2C1_EV },
142    Vector { _handler: I2C1_ER },
143    Vector { _handler: I2C2_EV },
144    Vector { _handler: I2C2_ER },
145    Vector { _handler: SPI1 },
146    Vector { _handler: SPI2 },
147    Vector { _handler: USART1 },
148    Vector { _handler: USART2 },
149    Vector { _handler: USART3 },
150    Vector {
151        _handler: EXTI15_10,
152    },
153    Vector { _handler: RTCALARM },
154    Vector {
155        _handler: USBWAKEUP,
156    },
157    Vector { _handler: TIM8_BRK },
158    Vector { _handler: TIM8_UP },
159    Vector {
160        _handler: TIM8_TRG_COM,
161    },
162    Vector { _handler: TIM8_CC },
163    Vector { _handler: ADC3 },
164    Vector { _handler: FSMC },
165    Vector { _handler: SDIO },
166    Vector { _handler: TIM5 },
167    Vector { _handler: SPI3 },
168    Vector { _handler: UART4 },
169    Vector { _handler: UART5 },
170    Vector { _handler: TIM6 },
171    Vector { _handler: TIM7 },
172    Vector {
173        _handler: DMA2_CHANNEL1,
174    },
175    Vector {
176        _handler: DMA2_CHANNEL2,
177    },
178    Vector {
179        _handler: DMA2_CHANNEL3,
180    },
181    Vector {
182        _handler: DMA2_CHANNEL4_5,
183    },
184];
185///Enumeration of all the interrupts.
186#[cfg_attr(feature = "defmt", derive(defmt::Format))]
187#[derive(Copy, Clone, Debug, PartialEq, Eq)]
188#[repr(u16)]
189pub enum Interrupt {
190    ///0 - Window Watchdog interrupt
191    WWDG = 0,
192    ///1 - PVD through EXTI line detection interrupt
193    PVD = 1,
194    ///2 - Tamper interrupt
195    TAMPER = 2,
196    ///3 - RTC global interrupt
197    RTC = 3,
198    ///4 - Flash global interrupt
199    FLASH = 4,
200    ///5 - RCC global interrupt
201    RCC = 5,
202    ///6 - EXTI Line0 interrupt
203    EXTI0 = 6,
204    ///7 - EXTI Line1 interrupt
205    EXTI1 = 7,
206    ///8 - EXTI Line2 interrupt
207    EXTI2 = 8,
208    ///9 - EXTI Line3 interrupt
209    EXTI3 = 9,
210    ///10 - EXTI Line4 interrupt
211    EXTI4 = 10,
212    ///11 - DMA1 Channel1 global interrupt
213    DMA1_CHANNEL1 = 11,
214    ///12 - DMA1 Channel2 global interrupt
215    DMA1_CHANNEL2 = 12,
216    ///13 - DMA1 Channel3 global interrupt
217    DMA1_CHANNEL3 = 13,
218    ///14 - DMA1 Channel4 global interrupt
219    DMA1_CHANNEL4 = 14,
220    ///15 - DMA1 Channel5 global interrupt
221    DMA1_CHANNEL5 = 15,
222    ///16 - DMA1 Channel6 global interrupt
223    DMA1_CHANNEL6 = 16,
224    ///17 - DMA1 Channel7 global interrupt
225    DMA1_CHANNEL7 = 17,
226    ///18 - ADC1 and ADC2 global interrupt
227    ADC1_2 = 18,
228    ///19 - USB High Priority or CAN TX interrupts
229    USB_HP_CAN_TX = 19,
230    ///20 - USB Low Priority or CAN RX0 interrupts
231    USB_LP_CAN_RX0 = 20,
232    ///23 - EXTI Line\[9:5\] interrupts
233    EXTI9_5 = 23,
234    ///24 - TIM1 Break interrupt
235    TIM1_BRK = 24,
236    ///25 - TIM1 Update interrupt
237    TIM1_UP = 25,
238    ///26 - TIM1 Trigger and Commutation interrupts
239    TIM1_TRG_COM = 26,
240    ///27 - TIM1 Capture Compare interrupt
241    TIM1_CC = 27,
242    ///28 - TIM2 global interrupt
243    TIM2 = 28,
244    ///29 - TIM3 global interrupt
245    TIM3 = 29,
246    ///30 - TIM4 global interrupt
247    TIM4 = 30,
248    ///31 - I2C event interrupt
249    I2C1_EV = 31,
250    ///32 - I2C errot interrupt
251    I2C1_ER = 32,
252    ///33 - I2C event interrupt
253    I2C2_EV = 33,
254    ///34 - I2C errot interrupt
255    I2C2_ER = 34,
256    ///35 - SPI1 global interrupt
257    SPI1 = 35,
258    ///36 - SPI2 global interrupt
259    SPI2 = 36,
260    ///37 - USART1 global interrupt
261    USART1 = 37,
262    ///38 - USART2 global interrupt
263    USART2 = 38,
264    ///39 - USART3 global interrupt
265    USART3 = 39,
266    ///40 - EXTI Line\[15:10\] interrupts
267    EXTI15_10 = 40,
268    ///41 - RTC Alarms through EXTI line interrupt
269    RTCALARM = 41,
270    ///42 - USB wakeup from suspend through EXTI line interrupt
271    USBWAKEUP = 42,
272    ///43 - TIM8 Break interrupt
273    TIM8_BRK = 43,
274    ///44 - TIM8 Update interrupt
275    TIM8_UP = 44,
276    ///45 - TIM8 Trigger and Commutation interrupts
277    TIM8_TRG_COM = 45,
278    ///46 - TIM8 Capture Compare interrupt
279    TIM8_CC = 46,
280    ///47 - ADC3 global interrupt
281    ADC3 = 47,
282    ///48 - FSMC global interrupt
283    FSMC = 48,
284    ///49 - SDIO global interrupt
285    SDIO = 49,
286    ///50 - TIM5 global interrupt
287    TIM5 = 50,
288    ///51 - SPI3 global interrupt
289    SPI3 = 51,
290    ///52 - UART4 global interrupt
291    UART4 = 52,
292    ///53 - UART5 global interrupt
293    UART5 = 53,
294    ///54 - TIM6 global interrupt
295    TIM6 = 54,
296    ///55 - TIM7 global interrupt
297    TIM7 = 55,
298    ///56 - DMA2 Channel1 global interrupt
299    DMA2_CHANNEL1 = 56,
300    ///57 - DMA2 Channel2 global interrupt
301    DMA2_CHANNEL2 = 57,
302    ///58 - DMA2 Channel3 global interrupt
303    DMA2_CHANNEL3 = 58,
304    ///59 - DMA2 Channel4 and DMA2 Channel5 global interrupt
305    DMA2_CHANNEL4_5 = 59,
306}
307unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
308    #[inline(always)]
309    fn number(self) -> u16 {
310        self as u16
311    }
312}
313///Power control
314///
315///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#PWR)
316pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
317impl core::fmt::Debug for PWR {
318    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
319        f.debug_struct("PWR").finish()
320    }
321}
322///Power control
323pub mod pwr;
324///Reset and clock control
325///
326///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#RCC)
327pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
328impl core::fmt::Debug for RCC {
329    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
330        f.debug_struct("RCC").finish()
331    }
332}
333///Reset and clock control
334pub mod rcc;
335///General purpose I/O
336///
337///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
338pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4001_0800>;
339impl core::fmt::Debug for GPIOA {
340    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
341        f.debug_struct("GPIOA").finish()
342    }
343}
344///General purpose I/O
345pub mod gpioa;
346///General purpose I/O
347///
348///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
349pub type GPIOB = crate::Periph<gpioa::RegisterBlock, 0x4001_0c00>;
350impl core::fmt::Debug for GPIOB {
351    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
352        f.debug_struct("GPIOB").finish()
353    }
354}
355///General purpose I/O
356pub use self::gpioa as gpiob;
357///General purpose I/O
358///
359///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
360pub type GPIOC = crate::Periph<gpioa::RegisterBlock, 0x4001_1000>;
361impl core::fmt::Debug for GPIOC {
362    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
363        f.debug_struct("GPIOC").finish()
364    }
365}
366///General purpose I/O
367pub use self::gpioa as gpioc;
368///General purpose I/O
369///
370///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
371pub type GPIOD = crate::Periph<gpioa::RegisterBlock, 0x4001_1400>;
372impl core::fmt::Debug for GPIOD {
373    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
374        f.debug_struct("GPIOD").finish()
375    }
376}
377///General purpose I/O
378pub use self::gpioa as gpiod;
379///General purpose I/O
380///
381///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
382pub type GPIOE = crate::Periph<gpioa::RegisterBlock, 0x4001_1800>;
383impl core::fmt::Debug for GPIOE {
384    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
385        f.debug_struct("GPIOE").finish()
386    }
387}
388///General purpose I/O
389pub use self::gpioa as gpioe;
390///General purpose I/O
391///
392///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
393pub type GPIOF = crate::Periph<gpioa::RegisterBlock, 0x4001_1c00>;
394impl core::fmt::Debug for GPIOF {
395    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
396        f.debug_struct("GPIOF").finish()
397    }
398}
399///General purpose I/O
400pub use self::gpioa as gpiof;
401///General purpose I/O
402///
403///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
404pub type GPIOG = crate::Periph<gpioa::RegisterBlock, 0x4001_2000>;
405impl core::fmt::Debug for GPIOG {
406    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
407        f.debug_struct("GPIOG").finish()
408    }
409}
410///General purpose I/O
411pub use self::gpioa as gpiog;
412///Alternate function I/O
413///
414///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#AFIO)
415pub type AFIO = crate::Periph<afio::RegisterBlock, 0x4001_0000>;
416impl core::fmt::Debug for AFIO {
417    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
418        f.debug_struct("AFIO").finish()
419    }
420}
421///Alternate function I/O
422pub mod afio;
423///EXTI
424///
425///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#EXTI)
426pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
427impl core::fmt::Debug for EXTI {
428    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
429        f.debug_struct("EXTI").finish()
430    }
431}
432///EXTI
433pub mod exti;
434///DMA controller
435///
436///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#DMA1)
437pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
438impl core::fmt::Debug for DMA1 {
439    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
440        f.debug_struct("DMA1").finish()
441    }
442}
443///DMA controller
444pub mod dma1;
445///DMA controller
446///
447///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#DMA1)
448pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
449impl core::fmt::Debug for DMA2 {
450    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
451        f.debug_struct("DMA2").finish()
452    }
453}
454///DMA controller
455pub use self::dma1 as dma2;
456///Real time clock
457///
458///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#RTC)
459pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
460impl core::fmt::Debug for RTC {
461    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
462        f.debug_struct("RTC").finish()
463    }
464}
465///Real time clock
466pub mod rtc;
467///Independent watchdog
468///
469///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#IWDG)
470pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
471impl core::fmt::Debug for IWDG {
472    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
473        f.debug_struct("IWDG").finish()
474    }
475}
476///Independent watchdog
477pub mod iwdg;
478///Window watchdog
479///
480///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#WWDG)
481pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
482impl core::fmt::Debug for WWDG {
483    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
484        f.debug_struct("WWDG").finish()
485    }
486}
487///Window watchdog
488pub mod wwdg;
489///General purpose timer
490///
491///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM2)
492pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
493impl core::fmt::Debug for TIM2 {
494    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
495        f.debug_struct("TIM2").finish()
496    }
497}
498///General purpose timer
499pub mod tim2;
500///General purpose timer
501///
502///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM2)
503pub type TIM3 = crate::Periph<tim2::RegisterBlock, 0x4000_0400>;
504impl core::fmt::Debug for TIM3 {
505    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
506        f.debug_struct("TIM3").finish()
507    }
508}
509///General purpose timer
510pub use self::tim2 as tim3;
511///Inter integrated circuit
512///
513///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#I2C1)
514pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
515impl core::fmt::Debug for I2C1 {
516    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
517        f.debug_struct("I2C1").finish()
518    }
519}
520///Inter integrated circuit
521pub mod i2c1;
522///Inter integrated circuit
523///
524///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#I2C1)
525pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
526impl core::fmt::Debug for I2C2 {
527    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
528        f.debug_struct("I2C2").finish()
529    }
530}
531///Inter integrated circuit
532pub use self::i2c1 as i2c2;
533///Serial peripheral interface
534///
535///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SPI1)
536pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
537impl core::fmt::Debug for SPI1 {
538    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
539        f.debug_struct("SPI1").finish()
540    }
541}
542///Serial peripheral interface
543pub mod spi1;
544///Universal synchronous asynchronous receiver transmitter
545///
546///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#USART1)
547pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
548impl core::fmt::Debug for USART1 {
549    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
550        f.debug_struct("USART1").finish()
551    }
552}
553///Universal synchronous asynchronous receiver transmitter
554pub mod usart1;
555///Universal synchronous asynchronous receiver transmitter
556///
557///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#USART1)
558pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
559impl core::fmt::Debug for USART2 {
560    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
561        f.debug_struct("USART2").finish()
562    }
563}
564///Universal synchronous asynchronous receiver transmitter
565pub use self::usart1 as usart2;
566///Universal synchronous asynchronous receiver transmitter
567///
568///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#USART1)
569pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
570impl core::fmt::Debug for USART3 {
571    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
572        f.debug_struct("USART3").finish()
573    }
574}
575///Universal synchronous asynchronous receiver transmitter
576pub use self::usart1 as usart3;
577///Analog to digital converter
578///
579///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#ADC1)
580pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2400>;
581impl core::fmt::Debug for ADC1 {
582    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
583        f.debug_struct("ADC1").finish()
584    }
585}
586///Analog to digital converter
587pub mod adc1;
588///Analog to digital converter
589///
590///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#ADC3)
591pub type ADC3 = crate::Periph<adc3::RegisterBlock, 0x4001_3c00>;
592impl core::fmt::Debug for ADC3 {
593    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
594        f.debug_struct("ADC3").finish()
595    }
596}
597///Analog to digital converter
598pub mod adc3;
599///CRC calculation unit
600///
601///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#CRC)
602pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
603impl core::fmt::Debug for CRC {
604    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
605        f.debug_struct("CRC").finish()
606    }
607}
608///CRC calculation unit
609pub mod crc;
610///FLASH
611///
612///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#FLASH)
613pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
614impl core::fmt::Debug for FLASH {
615    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
616        f.debug_struct("FLASH").finish()
617    }
618}
619///FLASH
620pub mod flash;
621///Debug support
622///
623///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#DBGMCU)
624pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
625impl core::fmt::Debug for DBGMCU {
626    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
627        f.debug_struct("DBGMCU").finish()
628    }
629}
630///Debug support
631pub mod dbgmcu;
632///Backup registers
633///
634///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#BKP)
635pub type BKP = crate::Periph<bkp::RegisterBlock, 0x4000_6c04>;
636impl core::fmt::Debug for BKP {
637    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
638        f.debug_struct("BKP").finish()
639    }
640}
641///Backup registers
642pub mod bkp;
643///Flexible static memory controller
644///
645///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#FSMC)
646pub type FSMC = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
647impl core::fmt::Debug for FSMC {
648    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
649        f.debug_struct("FSMC").finish()
650    }
651}
652///Flexible static memory controller
653pub mod fsmc;
654///USB on the go full speed
655///
656///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#OTG_FS_DEVICE)
657pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
658impl core::fmt::Debug for OTG_FS_DEVICE {
659    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
660        f.debug_struct("OTG_FS_DEVICE").finish()
661    }
662}
663///USB on the go full speed
664pub mod otg_fs_device;
665///USB on the go full speed
666///
667///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#OTG_FS_GLOBAL)
668pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
669impl core::fmt::Debug for OTG_FS_GLOBAL {
670    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
671        f.debug_struct("OTG_FS_GLOBAL").finish()
672    }
673}
674///USB on the go full speed
675pub mod otg_fs_global;
676///USB on the go full speed
677///
678///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#OTG_FS_HOST)
679pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
680impl core::fmt::Debug for OTG_FS_HOST {
681    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
682        f.debug_struct("OTG_FS_HOST").finish()
683    }
684}
685///USB on the go full speed
686pub mod otg_fs_host;
687///USB on the go full speed
688///
689///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#OTG_FS_PWRCLK)
690pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
691impl core::fmt::Debug for OTG_FS_PWRCLK {
692    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
693        f.debug_struct("OTG_FS_PWRCLK").finish()
694    }
695}
696///USB on the go full speed
697pub mod otg_fs_pwrclk;
698///Secure digital input/output interface
699///
700///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SDIO)
701pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_8000>;
702impl core::fmt::Debug for SDIO {
703    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
704        f.debug_struct("SDIO").finish()
705    }
706}
707///Secure digital input/output interface
708pub mod sdio;
709///General purpose timer
710///
711///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM13)
712pub type TIM13 = crate::Periph<tim13::RegisterBlock, 0x4000_1c00>;
713impl core::fmt::Debug for TIM13 {
714    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
715        f.debug_struct("TIM13").finish()
716    }
717}
718///General purpose timer
719pub mod tim13;
720///General purpose timer
721///
722///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM13)
723pub type TIM10 = crate::Periph<tim13::RegisterBlock, 0x4001_5000>;
724impl core::fmt::Debug for TIM10 {
725    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
726        f.debug_struct("TIM10").finish()
727    }
728}
729///General purpose timer
730pub use self::tim13 as tim10;
731///General purpose timer
732///
733///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM13)
734pub type TIM11 = crate::Periph<tim13::RegisterBlock, 0x4001_5400>;
735impl core::fmt::Debug for TIM11 {
736    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
737        f.debug_struct("TIM11").finish()
738    }
739}
740///General purpose timer
741pub use self::tim13 as tim11;
742///General purpose timer
743///
744///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM9)
745pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4c00>;
746impl core::fmt::Debug for TIM9 {
747    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
748        f.debug_struct("TIM9").finish()
749    }
750}
751///General purpose timer
752pub mod tim9;
753///General purpose timer
754///
755///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM9)
756pub type TIM12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
757impl core::fmt::Debug for TIM12 {
758    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
759        f.debug_struct("TIM12").finish()
760    }
761}
762///General purpose timer
763pub use self::tim9 as tim12;
764///Advanced timer
765///
766///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM8)
767pub type TIM8 = crate::Periph<tim8::RegisterBlock, 0x4001_3400>;
768impl core::fmt::Debug for TIM8 {
769    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
770        f.debug_struct("TIM8").finish()
771    }
772}
773///Advanced timer
774pub mod tim8;
775///Advanced timer
776///
777///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM8)
778pub type TIM1 = crate::Periph<tim8::RegisterBlock, 0x4001_2c00>;
779impl core::fmt::Debug for TIM1 {
780    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
781        f.debug_struct("TIM1").finish()
782    }
783}
784///Advanced timer
785pub use self::tim8 as tim1;
786///Analog to digital converter
787///
788///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#ADC2)
789pub type ADC2 = crate::Periph<adc2::RegisterBlock, 0x4001_2800>;
790impl core::fmt::Debug for ADC2 {
791    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
792        f.debug_struct("ADC2").finish()
793    }
794}
795///Analog to digital converter
796pub mod adc2;
797///Digital to analog converter
798///
799///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#DAC)
800pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
801impl core::fmt::Debug for DAC {
802    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
803        f.debug_struct("DAC").finish()
804    }
805}
806///Digital to analog converter
807pub mod dac;
808///Universal serial bus full-speed device interface
809///
810///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#USB)
811pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
812impl core::fmt::Debug for USB {
813    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
814        f.debug_struct("USB").finish()
815    }
816}
817///Universal serial bus full-speed device interface
818pub mod usb;
819///Universal asynchronous receiver transmitter
820///
821///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#UART4)
822pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
823impl core::fmt::Debug for UART4 {
824    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
825        f.debug_struct("UART4").finish()
826    }
827}
828///Universal asynchronous receiver transmitter
829pub mod uart4;
830///Universal asynchronous receiver transmitter
831///
832///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#UART4)
833pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
834impl core::fmt::Debug for UART5 {
835    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
836        f.debug_struct("UART5").finish()
837    }
838}
839///Universal asynchronous receiver transmitter
840pub use self::uart4 as uart5;
841///Serial peripheral interface
842///
843///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SPI2)
844pub type SPI2 = crate::Periph<spi2::RegisterBlock, 0x4000_3800>;
845impl core::fmt::Debug for SPI2 {
846    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
847        f.debug_struct("SPI2").finish()
848    }
849}
850///Serial peripheral interface
851pub mod spi2;
852///Serial peripheral interface
853///
854///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SPI2)
855pub type SPI3 = crate::Periph<spi2::RegisterBlock, 0x4000_3c00>;
856impl core::fmt::Debug for SPI3 {
857    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
858        f.debug_struct("SPI3").finish()
859    }
860}
861///Serial peripheral interface
862pub use self::spi2 as spi3;
863///General purpose timer
864///
865///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM2)
866pub type TIM4 = crate::Periph<tim2::RegisterBlock, 0x4000_0800>;
867impl core::fmt::Debug for TIM4 {
868    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
869        f.debug_struct("TIM4").finish()
870    }
871}
872///General purpose timer
873pub use self::tim2 as tim4;
874///General purpose timer
875///
876///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM2)
877pub type TIM5 = crate::Periph<tim2::RegisterBlock, 0x4000_0c00>;
878impl core::fmt::Debug for TIM5 {
879    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
880        f.debug_struct("TIM5").finish()
881    }
882}
883///General purpose timer
884pub use self::tim2 as tim5;
885///Basic timer
886///
887///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM6)
888pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
889impl core::fmt::Debug for TIM6 {
890    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
891        f.debug_struct("TIM6").finish()
892    }
893}
894///Basic timer
895pub mod tim6;
896///Basic timer
897///
898///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM6)
899pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
900impl core::fmt::Debug for TIM7 {
901    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
902        f.debug_struct("TIM7").finish()
903    }
904}
905///Basic timer
906pub use self::tim6 as tim7;
907///General purpose timer
908///
909///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM13)
910pub type TIM14 = crate::Periph<tim13::RegisterBlock, 0x4000_2000>;
911impl core::fmt::Debug for TIM14 {
912    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
913        f.debug_struct("TIM14").finish()
914    }
915}
916///General purpose timer
917pub use self::tim13 as tim14;
918///System control block ACTLR
919///
920///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SCB_ACTRL)
921pub type SCB_ACTRL = crate::Periph<scb_actrl::RegisterBlock, 0xe000_e008>;
922impl core::fmt::Debug for SCB_ACTRL {
923    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
924        f.debug_struct("SCB_ACTRL").finish()
925    }
926}
927///System control block ACTLR
928pub mod scb_actrl;
929///Nested vectored interrupt controller
930///
931///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#NVIC_STIR)
932pub type NVIC_STIR = crate::Periph<nvic_stir::RegisterBlock, 0xe000_ef00>;
933impl core::fmt::Debug for NVIC_STIR {
934    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
935        f.debug_struct("NVIC_STIR").finish()
936    }
937}
938///Nested vectored interrupt controller
939pub mod nvic_stir;
940///SysTick timer
941///
942///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#STK)
943pub type STK = crate::Periph<stk::RegisterBlock, 0xe000_e010>;
944impl core::fmt::Debug for STK {
945    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
946        f.debug_struct("STK").finish()
947    }
948}
949///SysTick timer
950pub mod stk;
951#[no_mangle]
952static mut DEVICE_PERIPHERALS: bool = false;
953/// All the peripherals.
954#[allow(non_snake_case)]
955pub struct Peripherals {
956    ///PWR
957    pub PWR: PWR,
958    ///RCC
959    pub RCC: RCC,
960    ///GPIOA
961    pub GPIOA: GPIOA,
962    ///GPIOB
963    pub GPIOB: GPIOB,
964    ///GPIOC
965    pub GPIOC: GPIOC,
966    ///GPIOD
967    pub GPIOD: GPIOD,
968    ///GPIOE
969    pub GPIOE: GPIOE,
970    ///GPIOF
971    pub GPIOF: GPIOF,
972    ///GPIOG
973    pub GPIOG: GPIOG,
974    ///AFIO
975    pub AFIO: AFIO,
976    ///EXTI
977    pub EXTI: EXTI,
978    ///DMA1
979    pub DMA1: DMA1,
980    ///DMA2
981    pub DMA2: DMA2,
982    ///RTC
983    pub RTC: RTC,
984    ///IWDG
985    pub IWDG: IWDG,
986    ///WWDG
987    pub WWDG: WWDG,
988    ///TIM2
989    pub TIM2: TIM2,
990    ///TIM3
991    pub TIM3: TIM3,
992    ///I2C1
993    pub I2C1: I2C1,
994    ///I2C2
995    pub I2C2: I2C2,
996    ///SPI1
997    pub SPI1: SPI1,
998    ///USART1
999    pub USART1: USART1,
1000    ///USART2
1001    pub USART2: USART2,
1002    ///USART3
1003    pub USART3: USART3,
1004    ///ADC1
1005    pub ADC1: ADC1,
1006    ///ADC3
1007    pub ADC3: ADC3,
1008    ///CRC
1009    pub CRC: CRC,
1010    ///FLASH
1011    pub FLASH: FLASH,
1012    ///DBGMCU
1013    pub DBGMCU: DBGMCU,
1014    ///BKP
1015    pub BKP: BKP,
1016    ///FSMC
1017    pub FSMC: FSMC,
1018    ///OTG_FS_DEVICE
1019    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
1020    ///OTG_FS_GLOBAL
1021    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
1022    ///OTG_FS_HOST
1023    pub OTG_FS_HOST: OTG_FS_HOST,
1024    ///OTG_FS_PWRCLK
1025    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
1026    ///SDIO
1027    pub SDIO: SDIO,
1028    ///TIM13
1029    pub TIM13: TIM13,
1030    ///TIM10
1031    pub TIM10: TIM10,
1032    ///TIM11
1033    pub TIM11: TIM11,
1034    ///TIM9
1035    pub TIM9: TIM9,
1036    ///TIM12
1037    pub TIM12: TIM12,
1038    ///TIM8
1039    pub TIM8: TIM8,
1040    ///TIM1
1041    pub TIM1: TIM1,
1042    ///ADC2
1043    pub ADC2: ADC2,
1044    ///DAC
1045    pub DAC: DAC,
1046    ///USB
1047    pub USB: USB,
1048    ///UART4
1049    pub UART4: UART4,
1050    ///UART5
1051    pub UART5: UART5,
1052    ///SPI2
1053    pub SPI2: SPI2,
1054    ///SPI3
1055    pub SPI3: SPI3,
1056    ///TIM4
1057    pub TIM4: TIM4,
1058    ///TIM5
1059    pub TIM5: TIM5,
1060    ///TIM6
1061    pub TIM6: TIM6,
1062    ///TIM7
1063    pub TIM7: TIM7,
1064    ///TIM14
1065    pub TIM14: TIM14,
1066    ///SCB_ACTRL
1067    pub SCB_ACTRL: SCB_ACTRL,
1068    ///NVIC_STIR
1069    pub NVIC_STIR: NVIC_STIR,
1070    ///STK
1071    pub STK: STK,
1072}
1073impl Peripherals {
1074    /// Returns all the peripherals *once*.
1075    #[cfg(feature = "critical-section")]
1076    #[inline]
1077    pub fn take() -> Option<Self> {
1078        critical_section::with(|_| {
1079            if unsafe { DEVICE_PERIPHERALS } {
1080                return None;
1081            }
1082            Some(unsafe { Peripherals::steal() })
1083        })
1084    }
1085    /// Unchecked version of `Peripherals::take`.
1086    ///
1087    /// # Safety
1088    ///
1089    /// Each of the returned peripherals must be used at most once.
1090    #[inline]
1091    pub unsafe fn steal() -> Self {
1092        DEVICE_PERIPHERALS = true;
1093        Peripherals {
1094            PWR: PWR::steal(),
1095            RCC: RCC::steal(),
1096            GPIOA: GPIOA::steal(),
1097            GPIOB: GPIOB::steal(),
1098            GPIOC: GPIOC::steal(),
1099            GPIOD: GPIOD::steal(),
1100            GPIOE: GPIOE::steal(),
1101            GPIOF: GPIOF::steal(),
1102            GPIOG: GPIOG::steal(),
1103            AFIO: AFIO::steal(),
1104            EXTI: EXTI::steal(),
1105            DMA1: DMA1::steal(),
1106            DMA2: DMA2::steal(),
1107            RTC: RTC::steal(),
1108            IWDG: IWDG::steal(),
1109            WWDG: WWDG::steal(),
1110            TIM2: TIM2::steal(),
1111            TIM3: TIM3::steal(),
1112            I2C1: I2C1::steal(),
1113            I2C2: I2C2::steal(),
1114            SPI1: SPI1::steal(),
1115            USART1: USART1::steal(),
1116            USART2: USART2::steal(),
1117            USART3: USART3::steal(),
1118            ADC1: ADC1::steal(),
1119            ADC3: ADC3::steal(),
1120            CRC: CRC::steal(),
1121            FLASH: FLASH::steal(),
1122            DBGMCU: DBGMCU::steal(),
1123            BKP: BKP::steal(),
1124            FSMC: FSMC::steal(),
1125            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
1126            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
1127            OTG_FS_HOST: OTG_FS_HOST::steal(),
1128            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
1129            SDIO: SDIO::steal(),
1130            TIM13: TIM13::steal(),
1131            TIM10: TIM10::steal(),
1132            TIM11: TIM11::steal(),
1133            TIM9: TIM9::steal(),
1134            TIM12: TIM12::steal(),
1135            TIM8: TIM8::steal(),
1136            TIM1: TIM1::steal(),
1137            ADC2: ADC2::steal(),
1138            DAC: DAC::steal(),
1139            USB: USB::steal(),
1140            UART4: UART4::steal(),
1141            UART5: UART5::steal(),
1142            SPI2: SPI2::steal(),
1143            SPI3: SPI3::steal(),
1144            TIM4: TIM4::steal(),
1145            TIM5: TIM5::steal(),
1146            TIM6: TIM6::steal(),
1147            TIM7: TIM7::steal(),
1148            TIM14: TIM14::steal(),
1149            SCB_ACTRL: SCB_ACTRL::steal(),
1150            NVIC_STIR: NVIC_STIR::steal(),
1151            STK: STK::steal(),
1152        }
1153    }
1154}
stm32f1/stm32f102/mod.rs

stm32f1/stm32f102/
mod.rs
